REGISTER SUMMARY
M68HC16 Z SERIES
D-32
USER’S MANUAL
D.5.5 ADC Control Register 1
ADCTL1 is used to initiate an A/D conversion and to select conversion modes and a
conversion channel or channels. It can be read or written at any time. A write to
ADCTL1 initiates a conversion sequence. If a conversion sequence is already in
progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC
status register.
SCAN — Scan Mode Selection
0 = Single conversion
1 = Continuous conversions
Length of conversion sequence(s) is determined by S8CM.
MULT — Multichannel Conversion
0 = Conversion sequence(s) run on a single channel selected by [CD:CA].
1 = Sequential conversions of four or eight channels selected by [CD:CA].
Length of conversion sequence(s) is determined by S8CM.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
This bit determines the number of conversions in a conversion sequence.
displays the different ADC conversion modes.
Table D-27 Prescaler Output
PRS[4:0]
ADC Clock
Minimum
System Clock
Maximum
System Clock
%00000
Reserved
—
—
%00001
System Clock/4
2.0 MHz
8.4 MHz
%00010
System Clock/6
3.0 MHz
12.6 MHz
%00011
System Clock/8
4.0 MHz
16.8 MHz
…
…
…
…
%11101
System Clock/60
30.0 MHz
—
%11110
System Clock/62
31.0 MHz
—
%11111
System Clock/64
32.0 MHz
—
ADCTL1 — ADC Control Register 1
$YFF70C
15
7
6
5
4
3
2
1
0
NOT USED
SCAN
MULT
S8CM
CD
CC
CB
CA
RESET:
0
0
0
0
0
0
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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