M68HC16 Z SERIES
SYSTEM INTEGRATION MODULE
USER’S MANUAL
5-31
The external bus has 24 address lines and 16 data lines. ADDR[19:0] are normal ad-
dress outputs; ADDR[23:20] follow the output state of ADDR19. The EBI provides dy-
namic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-
word transfers. Port width is the maximum number of bits accepted or provided by the
external memory system during a bus transfer. Widths of eight and sixteen bits are ac-
cessed through the use of asynchronous cycles controlled by the size (SIZ1 and SIZ0)
and data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be
required for dynamically sized transfers.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
is synchronized with EBI transfers. Refer to
5.5.1 Bus Control Signals
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an ad-
dress and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space, the size
of the transfer, and the type of cycle. External devices decode these signals and re-
spond to transfer data and terminate the bus cycle. The EBI can operate in an asyn-
chronous mode for any port width.
5.5.1.1 Address Bus
Bus signals ADDR[19:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.
5.5.1.2 Address Strobe
Address strobe (AS) is a timing signal that indicates the validity of an address on the
address bus and of many control signals.
5.5.1.3 Data Bus
Signals DATA[15:0] form a bidirectional, non-multiplexed parallel bus that transfers
data to or from the MCU. A read or write operation can transfer eight or sixteen bits of
data in one bus cycle. For a write cycle, all sixteen bits of the data bus are driven, re-
gardless of the port width or operand size.
5.5.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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