NXP Semiconductors MC68CK16Z1, User Manual

Page: 307 / 501

M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS
USER’S MANUAL A-23
Table A-17 20.97-MHz AC Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
Num Characteristic Symbol Min Max Unit
F1 Frequency of Operation f — 20.97 MHz
1 Clock Period t
cyc
47.7 — ns
1A ECLK Period t
Ecyc
381 — ns
1B External Clock Input Period
2
t
Xcyc
47.7 — ns
2, 3 Clock Pulse Width
3
t
CW
18.8 — ns
2A, 3A ECLK Pulse Width t
ECW
183 — ns
2B, 3B External Clock Input High/Low Time
2
t
XCHL
23.8 — ns
4, 5 CLKOUT Rise and Fall Time t
Crf
— 5 ns
4A, 5A Rise and Fall Time (All Outputs except CLKOUT) t
rf
— 8 ns
4B, 5B External Clock Input Rise and Fall Time
3
t
XCrf
— 5 ns
6 Clock High to ADDR, FC, SIZE Valid
4
t
CHAV
0 23 ns
7 Clock High to ADDR, Data, FC, SIZE, High Impedance t
CHAZx
0 47 ns
8 Clock High to ADDR, FC, SIZE, Invalid t
CHAZn
0 — ns
9 Clock Low to AS, DS, CS Asserted
4
t
CLSA
0 23 ns
9A AS to DS or CS Asserted (Read)
5
t
STSA
-10 10 ns
11 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted t
AVSA
10 — ns
12 Clock Low to AS, DS, CS Negated t
CLSN
2 23 ns
13 AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) t
SNAI
10 — ns
14 AS, CS (and DS Read) Width Asserted t
SWA
80 — ns
14A DS, CS Width Asserted (Write) t
SWAW
36 — ns
14B AS, CS (and DS Read) Width Asserted (Fast Cycle) t
SWDW
32 — ns
15 AS, DS, CS Width Negated
6
t
SN
32 — ns
16 Clock High to AS, DS, R/W High Impedance t
CHSZ
— 47 ns
17 AS, DS, CS Negated to R/W High t
SNRN
10 — ns
18 Clock High to R/W High t
CHRH
0 23 ns
20 Clock High to R/W Low t
CHRL
0 23 ns
21 R/W High to AS, CS Asserted t
RAAA
10 — ns
22 R/W Low to DS, CS Asserted (Write) t
RASA
54 — ns
23 Clock High to Data Out Valid t
CHDO
— 23 ns
24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) t
DVASN
10 — ns
25 DS, CS Negated to Data Out Invalid (Data Out Hold) t
SNDOI
10 — ns
26 Data Out Valid to DS, CS Asserted (Write) t
DVSA
10 — ns
27 Data In Valid to Clock Low (Data Setup)
4
t
DICL
5 — ns
27A Late BERR, HALT Asserted to Clock Low (Setup Time) t
BELCL
15 — ns
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated t
SNDN
0 60 ns
29 DS, CS Negated to Data In Invalid (Data In Hold)
7
t
SNDI
0 — ns
29A DS, CS Negated to Data In High Impedance
7, 8
t
SHDI
— 48 ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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