ELECTRICAL CHARACTERISTICS
M68HC16 Z SERIES
A-22
USER’S MANUAL
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
t
CLDI
15
—
ns
30A
CLKOUT Low to Data In High Impedance
t
CLDH
—
90
ns
31
DSACK[1:0] Asserted to Data In Valid
9
t
DADI
—
50
ns
33
Clock Low to BG Asserted/Negated
t
CLBAN
—
29
ns
35
BR Asserted to BG Asserted
t
BRAGA
1
—
t
cyc
37
BGACK Asserted to BG Negated
t
GAGN
1
2
t
cyc
39
BG Width Negated
t
GH
2
—
t
cyc
39A
BG Width Asserted
t
GA
1
—
t
cyc
46
R/W Width Asserted (Write or Read)
t
RWA
150
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
t
RWAS
90
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
t
AIST
5
—
ns
47B
Asynchronous Input Hold Time
t
AIHT
15
—
ns
48
DSACK[1:0] Asserted to BERR, HALT Asserted
t
DABA
—
30
ns
53
Data Out Hold from Clock High
t
DOCH
0
—
ns
54
Clock High to Data Out High Impedance
t
CHDH
—
28
ns
55
R/W Asserted to Data Bus Impedance Change
t
RADC
40
—
ns
70
Clock Low to Data Bus Driven (Show Cycle)
t
SCLDD
0
29
ns
71
Data Setup Time to Clock Low (Show Cycle)
t
SCLDS
15
—
ns
72
Data Hold from Clock Low (Show Cycle)
t
SCLDH
10
—
ns
73
BKPT Input Setup Time
t
BKST
15
—
ns
74
BKPT Input Hold Time
t
BKHT
10
—
ns
75
Mode Select Setup Time, DATA[15:0], MODCLK, BKPT pins
t
MSS
20
—
t
cyc
76
Mode Select Hold Time, DATA[15:0], MODCLK, BKPT pins
t
MSH
0
—
ns
77
t
RSTA
4
—
t
cyc
78
t
RSTR
—
10
t
cyc
100
CLKOUT High to Phase 1 Asserted
t
CHP1A
3
40
ns
101
CLKOUT High to Phase 2 Asserted
t
CHP2A
3
40
ns
102
Phase 1 Valid to AS or DS Asserted
t
P1VSA
10
—
ns
103
Phase 2 Valid to AS or DS Asserted
t
P2VSN
10
—
ns
104
AS or DS Valid to Phase 1 Negated
t
SAP1N
10
—
ns
105
AS or DS Negated to Phase 2 Negated
t
SNP2N
10
—
ns
NOTES:
1. Refer to notes in
.
Table A-16 16.78-MHz AC Timing (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10 %, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
Num
Characteristic
Symbol
Min
Max
Unit
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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