NXP Semiconductors LPC11U1x, User Manual

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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 52 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
– Reset from the BOD circuit. In this case, the BOD reset must be enabled in the
BODCTRL register (
Table 36 ).
•
WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register:
– WWDT interrupt using the interrupt wake-up register 1 ( Table 44 ). The WWDT
interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the
WWDT MOD register.
– Reset from the watchdog timer.The WWDT reset must be set in the WWDT MOD
register.
•
USB wake-up signal interrupt wake-up register 1 ( Table 44 ). For details, see
Section 11.7.6 .
•
GPIO group interrupt signal (see Table 44 ).
Remark: If the watchdog oscillator is running in Power-down mode, its frequency
determines the wake-up time.
Remark: If the application in active mode uses a main clock different from the IRC,
reprogram the clock source for the main clock in the MAINCLKSEL register after waking
up.
3.9.6 Deep power-down mode
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin. The Deep power-down mode is controlled by the PMU
(see
Chapter 4 ).
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the general purpose registers of
the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
Remark: Setting bit 3 in the PCON register ( Section 4.3.1 ) prevents the part from entering
Deep-power down mode.
3.9.6.1 Power configuration in Deep power-down mode
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin is powered.
3.9.6.2 Programming Deep power-down mode
The following steps must be performed to enter Deep power-down mode:
1. Pull the WAKEUP pin externally HIGH.
2. Ensure that bit 3 in the PCON register ( Table 54 ) is cleared.
3. Write 0x3 to the PD bits in the PCON register (see Table 54 ).
4. Store data to be retained in the general purpose registers ( Section 4.3.2 ).
5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register.
6. Use the ARM WFI instruction.