NXP Semiconductors LPC11U1x, User Manual

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User manual Rev. 5.5 — 21 December 2016 452 of 523
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Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.3.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler and returns to Thread mode it immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
interrupt occurs.
24.3.5.2 Wake-up from sleep mode
The conditions for the processor to wake-up depend on the mechanism that caused it to
enter sleep mode.
24.3.5.2.1 Wake-up from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority
to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1. If an interrupt arrives that is enabled and has a higher priority than current
exception priority, the processor wakes up but does not execute the interrupt handler until
the processor sets PRIMASK to zero. For more information about PRIMASK, see
Section 24–24.3.1.3.6 .
24.3.5.2.2 Wake-up from WFE
The processor wakes up if:
•
it detects an exception with sufficient priority to cause exception entry
•
in a multiprocessor system, another processor in the system executes a
SEV
instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up the processor, even if the interrupt is disabled or has
insufficient priority to cause exception entry. For more information about the SCR see
Section 24–24.5.3.5 .
24.3.5.3 Power management programming hints
ISO/IEC C cannot directly generate the WFI , WFE , and SEV instructions. The CMSIS
provides the following intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
void __SEV(void) // Send Event
24.4 Instruction set
24.4.1 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 423 lists the
supported instructions.
Remark: In Table 423