UM10462
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User manual
Rev. 5.5 — 21 December 2016
283 of 523
NXP Semiconductors
UM10462
Chapter 13: LPC11U3x/2x/1x SSP/SPI
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is in 3-state mode whenever the SSP is idle. Once the bottom entry
of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to
be transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
13.7.2 SPI frame format
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.
13.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
When the CPOL clock polarity control bit is LOW, it produces a steady state low value on
the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is
placed on the CLK pin when data is not being transferred.
a. Single frame transfer
b. Continuous/back-to-back frames transfer
Fig 32. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer
CLK
FS
DX/DR
4 to 16 bits
MSB
LSB
CLK
FS
DX/DR
LSB
MSB
LSB
MSB
4 to 16 bits
4 to 16 bits
