UM10462
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User manual
Rev. 5.5 — 21 December 2016
364 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
16.7.12 PWM Control Register
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three single edge controlled PWM outputs can be selected
on the MATn.2:0 outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
Table 334: Count Control Register (CTCR, address 0x4001 8070 (CT32B1)) bit description
Bit
Symbol
Value
Description
Reset
value
1:0
CTM
Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or
clear PC and increment Timer Counter (TC).
Remark:
If Counter mode is selected in the CTCR, bits 2:0 in
the Capture Control Register (CCR) must be programmed as
000.
00
0x0
Timer Mode: every rising PCLK edge
0x1
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
3:2
CIS
Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking.
Remark:
If Counter mode is selected in the CTCR, the 3 bits
for that input in the Capture Control Register (CCR) must be
programmed as 000. Values 0x2 to 0x3 are reserved.
00
0x0
CT32B1_CAP0
0x1
CT32B1_CAP1
4
ENCC
Setting this bit to 1 enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
0
7:5
SElCC
When bit 4 is a 1, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is low. Values 0x3 to 0x7 are
reserved.
0x0
Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)
0x1
Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)
0x2
Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)
0x3
Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)
31:8
-
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
-
