UM10462
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© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
270 of 523
NXP Semiconductors
UM10462
Chapter 12: LPC11U3x/2x/1x USART
CSCEN=1 and CCCLR=1. After the USART has sent N clock cycles and thus received a
character, it clears the CSCEN bit. If more characters need to be received thereafter,
software can repeat setting CSCEN and CCCLR.
Aside from such half-duplex operation, the primary use of CSCEN=1 is with SSDIS=0, so
that start bits indicate the transmission of each character in each direction.
12.6 Functional description
12.6.1 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the USART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The USART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each USART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the USART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
RS-485/EIA-485 Auto Address Detection (AAD) mode
When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are
set, the USART is in auto address detect mode.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it
is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.
When a matching address character is detected it will be pushed onto the RXFIFO along
with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate an Rx Data Ready Interrupt.
