UM10462
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
441 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
The processor reserves regions of the
Private peripheral bus
(PPB) address range for
core peripheral registers, see
.
24.3.2.1 Memory regions, types and attributes
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
Normal —
The processor can re-order transactions for efficiency, or perform speculative
reads.
Device —
The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
For the LPC11U3x/2x/1x specific implementation of the memory map, see
Fig 77. Cortex-M0 memory map
([WHUQDOGHYLFH
([WHUQDO5$0
3HULSKHUDO
65$0
&RGH
[))))))))
3ULYDWHSHULSKHUDOEXV
[(
[()))))
[)))))))
[$
[)))))))
[
[)))))))
[
[)))))))
[
[
*%
*%
*%
*%
*%
[')))))))
[(
0%
0%
'HYLFH