UM10462
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
294 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
I2EN
I
2
C Interface Enable. When I2EN is 1, the I
2
C interface is enabled. I2EN can be
cleared by writing 1 to the I2ENC bit in the CONCLR register. When I2EN is 0, the I
2
C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
2
C block is in the “not
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
2
C-bus since, when I2EN is reset, the
I
2
C-bus status is lost. The AA flag should be used instead.
STA
is the START flag. Setting this bit causes the I
2
C interface to enter master mode and
transmit a START condition or transmit a Repeated START condition if it is already in
master mode.
When STA is 1 and the I
2
C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I
2
C interface is
already in master mode and data has been transmitted or received, it transmits a
Repeated START condition. STA may be set at any time, including when the I
2
C interface
is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the CONCLR register. When STA is 0,
no START condition or Repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
2
C-bus if it the
interface is in master mode, and transmits a START condition thereafter. If the I
2
C
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO
is the STOP flag. Setting this bit causes the I
2
C interface to transmit a STOP
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
2
C-bus. When the bus detects
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI
is the I
2
C Interrupt Flag. This bit is set when the I
2
C state changes. However, entering
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in the CONCLR register.
5
STA
START flag.
0
6
I2EN
I
2
C interface enable.
0
31:7
-
Reserved. The value read from a reserved bit is not defined.
-
Table 271. I
2
C Control Set register (CONSET - address 0x4000 0000) bit description
Bit
Symbol
Description
Reset
value
