UM10462
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User manual
Rev. 5.5 — 21 December 2016
352 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
•
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
16.4 Applications
•
Interval timer for counting internal events
•
Pulse Width Demodulator via capture input
•
Free running timer
•
Pulse Width Modulator via match outputs
16.5 General description
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
16.6 Pin description
gives a brief summary of each of the counter/timer related pins.
16.7 Register description
32-bit counter/timer0 contains the registers shown in
and 32-bit counter/timer1
contains the registers shown in
. More detailed descriptions follow.
Table 315. Counter/timer pin description
Pin
Type
Description
CT32B0_CAP[1:0]
CT32B1_CAP[1:0]
Input
Capture Signals:
A transition on a capture pin can be configured to load one of the
Capture Registers with the value in the Timer Counter and
optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock
source instead of the PCLK derived clock. For more details see
Section 16.7.11 “Count Control Register” on page 362
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
Output External Match Output of CT32B0/1:
When a match register MR3:0 equals the timer counter (TC), this
output can either toggle, go LOW, go HIGH, or do nothing. The
External Match Register (EMR) and the PWM Control register
(PWMCON) control the functionality of this output.
