UM10462
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© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
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15.1 How to read this chapter
CT16B0/1 are available on all LPC11U3x/2x/1x parts. The number of capture inputs
depends on package size. See
15.2 Basic configuration
The CT16B0/1 counter/timers are configured through the following registers:
•
Pins: The CT16B0/1 pins must be configured in the IOCON register block.
•
Power: In the SYSAHBCLKCTRL register, set bit 7 and 8 in
•
The peripheral clock is determined by the system clock (see
Remark:
The register offsets and bit offsets for capture channel 1 are different on timers
CT16B0 and CT16B1. The affected registers are:
•
Section 15.7.1 “Interrupt Register”
•
Section 15.7.8 “Capture Control Register”
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Section 15.7.9 “Capture Registers”
•
Section 15.7.11 “Count Control Register”
15.3 Features
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Two 16-bit counter/timers with a programmable 16-bit prescaler.
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Counter or timer operation
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Two 16-bit capture channels that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
•
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
•
Four 16-bit match registers that allow:
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Continuous operation with optional interrupt generation on match.
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Stop timer on match with optional interrupt generation.
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Reset timer on match with optional interrupt generation.
•
Two external outputs corresponding to match registers with the following capabilities:
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Set LOW on match.
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Set HIGH on match.
–
Toggle on match.
–
Do nothing on match.
•
For each timer, up to four match registers can be configured as PWM allowing to use
up to two match outputs as single edge controlled PWM outputs.
UM10462
Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1
Rev. 5.5 — 21 December 2016
User manual