NXP Semiconductors LPC11U1x, User Manual

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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 153 of 523
9.1 How to read this chapter
All GPIO registers refer to 32 pins on each port. Depending on the package type, not all
pins are available, and the corresponding bits in the GPIO registers are reserved (see
Table 136 ).
9.2 Basic configuration
Various register blocks must be enabled to use the GPIO port and pin interrupt features:
•
For the pin interrupts, select up to 8 external interrupt pins from all GPIO port pins in
the SYSCON block (
Table 40 ) and enable the clock to the pin interrupt register block
in the SYSAHBCLKCTRL register ( Table 24 , bit 19). The pin interrupt wake-up feature
is enabled in the STARTERP0 register ( Table 43 ).
•
For the group interrupt feature, enable the clock to the GROUP0 and GROUP1
register interfaces in the SYSAHBCLKCTRL register ((
Table 24 , bit 19). The group
interrupt wake-up feature is enabled in the STARTERP1 register ( Table 44 ).
•
For the GPIO port registers, enable the clock to the GPIO port register in the
SYSAHBCLKCTRL register (
Table 24 , bit 6).
9.3 Features
9.3.1 GPIO pin interrupt features
•
Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive interrupt
requests. Each request creates a separate interrupt in the NVIC.
•
Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
•
Level-sensitive interrupt pins can be HIGH- or LOW-active.
9.3.2 GPIO group interrupt features
•
The inputs from any number of GPIO pins can be enabled to contribute to a combined
group interrupt.
•
The polarity of each input enabled for the group interrupt can be configured HIGH or
LOW.
•
Enabled interrupts can be logically combined through an OR or AND operation.
UM10462
Chapter 9: LPC11U3x/2x/1x GPIO
Rev. 5.5 — 21 December 2016 User manual
Table 136. GPIO pins available
Package GPIO Port 0 GPIO Port 1
HVQFN33 PIO0_0 to PIO0_23 PIO1_15; PIO1_19
LQFPN48 PIO0_0 to PIO0_23 PIO1_13 to PIO1_16; PIO1_19 to PIO1_29; PIO1_31
TFBGA48 PIO0_0 to PIO0_23 PIO1_5; PIO1_13 to PIO1_16; PIO1_19 to PIO1_29
LQFP64 PIO0_0 to PIO0_23 PIO1_0 to PIO1_29