NXP Semiconductors LPC11U1x, User Manual

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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 351 of 523
16.1 How to read this chapter
CT32B0/1 are available on all LPC11U3x/2x/1x parts. The CT32B1_CAP1 input is only
available on the TFBGA48 and LQFP64 packages. The CT32B0_CAP1 input is only
available on LQFP48, TFBGA48, and LQFP64 packages. For all other packages, the
registers controlling the CT32B1_CAP1 and CT32B0_CAP1 inputs are reserved.
16.2 Basic configuration
The CT32B0/1 counter/timers are configured through the following registers:
•
Pins: The CT32B0/1 pins must be configured in the IOCON register block.
•
Power: In the SYSAHBCLKCTRL register, set bit 9 and 10 in Table 24 .
•
The peripheral clock is determined by the system clock (see Table 23 ).
Remark: The register offsets and bit offsets for capture channel 1 are different on timers
CT32B0 and CT32B1. The affected registers are:
•
Section 16.7.1 “Interrupt Register”
•
Section 16.7.8 “Capture Control Register”
•
Section 16.7.9 “Capture Registers”
•
Section 16.7.11 “Count Control Register”
16.3 Features
•
Two 32-bit counter/timers with a programmable 32-bit prescaler.
•
Counter or timer operation.
•
Four 32-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.
•
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
•
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
•
Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
Rev. 5.5 — 21 December 2016 User manual