NXP Semiconductors LPC11U1x, User Manual

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UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 56 of 523
4.1 How to read this chapter
The PMU is identical on all LPC11U3x/2x/1x parts. Also refer to Chapter 5 for power
control.
4.2 Introduction
The PMU controls the Deep power-down mode. Four general purpose register in the PMU
can be used to retain data during Deep power-down mode.
4.3 Register description
4.3.1 Power control register
The power control register selects whether one of the ARM Cortex-M0 controlled
power-down modes (Sleep mode or Deep-sleep/Power-down mode) or the Deep
power-down mode is entered and provides the flags for Sleep or Deep-sleep/Power-down
modes and Deep power-down modes respectively. See
Section 3.9 for details on how to
enter the power-down modes.
UM10462
Chapter 4: LPC11U3x/2x/1x Power Management Unit (PMU)
Rev. 5.5 — 21 December 2016 User manual
Table 53. Register overview: PMU (base address 0x4003 8000)
Name Access Address
offset Description Reset
value Reference
PCON R/W 0x000 Power control register 0x0 Table 54
GPREG0 R/W 0x004 General purpose register 0 0x0 Table 55
GPREG1 R/W 0x008 General purpose register 1 0x0 Table 55
GPREG2 R/W 0x00C General purpose register 2 0x0 Table 55
GPREG3 R/W 0x010 General purpose register 3 0x0 Table 55
GPREG4 R/W 0x014 General purpose register 4 0x0 Table 56
Table 54. Power control register (PCON, address 0x4003 8000) bit description
Bit Symbol Value Description Reset
value
2:0 PM Power mode 000
0x0 Default. The part is in active or sleep mode.
0x1 ARM WFI will enter Deep-sleep mode.
0x2 ARM WFI will enter Power-down mode.
0x3 ARM WFI will enter Deep-power down mode (ARM
Cortex-M0 core powered-down).
3 NODPD A 1 in this bit prevents entry to Deep power-down mode
when 0x3 is written to the PM field above, the
SLEEPDEEP bit is set, and a WFI is executed
This bit is cleared only by power-on reset, so writing a one
to this bit locks the part in a mode in which Deep
power-down mode is blocked. 0