manualshive.com logo in svg

Nuvoton Mini57 Series, Technical Reference Manual

Share
Download
Nuvoton Mini57 Series Technical Reference Manual Download Page 396

 

Mini57 

Apr. 06, 2017 

Page 396 of 475 

Rev.1.00 

 

MINI5

7

 S

E

RI
E

S

 TECH

NIC

A

L R

E

F

E

RE
N

CE
 MA
N

UA

L

 

arbitration lost, the ARBLOIF will be set to 1. 

Note:

  During  I

2

C  communication,  the  SCL  clock  will  be  released  when  writing  ‘1’  to  PTRG 

(UI2C_PROTCTL [5]) in Slave mode. 

S

(PTRG, STA, STO, AA)=(1, 1, 0, 1)
Writing 1 to ACKIF
(Writing 1 to NACKIF)
(Writing 1 to STORIF)

...

...

Switch to not addressed mode
Own SLA will be recognized
Send START when bus free

...

(PTRG, STA, STO, AA)=(1, 0, 0, 0)
Writing 1 to ACKIF
(Writing 1 to NACKIF)
(Writing 1 to STORIF)

Switch to not addressed mode
Own SLA will not be recognized

Become I

2

C 

Master

Bus Free

((PTRG, STA, STO, AA)=(0, 0, 0, 1)

Clear protocol status register

ACKIF = 1

TXDAT

(Data)

TXDAT = Data
(PTRG, STA, STO, AA)=(1, 0, 0, 1)
Writing 1 to ACKIF
(Writing 1 to ARBLOIF)

...

TXDAT

(Data)

TXDAT = Data
(PTRG, STA, STO, AA)=(1, 0, 0, 0)
Writing 1 to ACKIF
(Writing 1 to ARBLOIF)

ACKIF = 1

Switch to not addressed mode

Own SLA will be recognized

TXDAT

(Data)

TXDAT = Data
(PTRG, STA, STO, AA)=(1, 0, 0, 0)
Writing 1 to ACKIF
(Writing 1 to ARBLOIF)

ACKIF = 1

NACKIF = 1

NAK

ARBLOIF = 1

ACKIF = 1

RXDAT

(Data)

(PTRG, STA, STO, AA)=(1, 0, 0, 1)
Writing 1 to ACKIF

RXDAT

(Data)

(PTRG, STA, STO, AA)=(1, 0, 0, 0)
Writing 1 to ACKIF

ACKIF = 1

NACKIF = 1

Arbitration Lost

Master to Slave

Slave to Master

STORIF = 1

ARBLOIF = 1

Sr

Sr

Sr

...

(PTRG, STA, STO, AA)=(1, 0, 0, 1)
Writing 1 to ACKIF
(Writing 1 to NACKIF)
(Writing 1 to STORIF)

Switch to not addressed mode
Own SLA will be recognized

Become I

2

C Slave

STORIF = 1

Sr

TXDAT = Data
(PTRG, STA, STO, AA)=(1, 0, 0, X)
Writing 1 to ACKIF
(Writing 1 to ARBLOIF)

TXDAT = Data

(PTRG, STA, STO, AA)=(1, 0, 0, X)

Writing 1 to ACKIF

(Writing 1 to ARBLOIF)

...

...

Sr

(PTRG, STA, STO, AA)=(1, 0, 0, X)
Writing 1 to ACKIF

(PTRG, STA, STO, AA)=(1, 0, 0, X)
Writing 1 to ACKIF

ACK

NAK

P

ACK

NAK

ACK

RXDAT

(SLA+W)

RXDAT

(SLA+R)

S

ACK

ACK

NAK

P

S

...

...

Switch to not addressed mode
Own SLA will not be recognized
Send START when bus free

Become I

2

C 

Master

(PTRG, STA, STO, AA)=(1, 1, 0, 0)
Writing 1 to ACKIF
(Writing 1 to NACKIF)
(Writing 1 to STORIF)

If slave detect START

STARIF=1

 

Figure 6.14-15 Save Mode Control Flow with 7-bit Address 

If I

2

C is still transmitting and receiving data in addressed Slave mode but got a STOP or Repeat 

Summary of Contents for Mini57 Series

Page 1: ...ectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design Nuvoton assumes no responsibility for errors or omissions All data and specifications are subject to change without notice For additional information or questions please contact Nu...

Page 2: ...1 ARM Cortex M0 Core 40 6 1 1 Overview 40 6 1 2 Features 40 6 2 System Manager 42 6 2 1 Overview 42 6 2 2 System Reset 42 6 2 3 Power Modes and Wake up Sources 48 6 2 4 System Power Architecture 51 6 2 5 System Memory Mapping 52 6 2 6 Register Protection 53 6 2 7 Memory Organization 55 6 2 8 Register Map 58 6 2 9 Register Description 59 6 2 10 System Timer SysTick 79 6 2 11 Nested Vectored Interru...

Page 3: ...88 6 6 4 Basic Configuration 189 6 6 5 Functional Description 189 6 6 6 Register Map 196 6 6 7 Register Description 197 6 7 Enhanced Input Capture Timer ECAP 209 6 7 1 Overview 209 6 7 2 Features 209 6 7 3 Block Diagram 209 6 7 4 Input Noise Filter 210 6 7 5 Operation of Input Capture Timer Counter 211 6 7 6 Input Capture Timer Counter Interrupt Architecture 213 6 7 7 Register Map 214 6 7 8 Regist...

Page 4: ...ew 313 6 12 2 Features 313 6 12 3 Block Diagram 313 6 12 4 Basic Configuration 314 6 12 5 Functional Description 314 6 12 6 Register Map 324 6 12 7 Register Description 325 6 13 USCI SPI Mode 346 6 13 1 Overview 346 6 13 2 Features 346 6 13 3 Block Diagram 347 6 13 4 Basic Configuration 347 6 13 5 Functional Description 348 6 13 6 Register Map 361 6 13 7 Register Description 362 6 14 USCI I 2 C Mo...

Page 5: ...iew 452 6 17 2 Features 452 6 17 3 Block Diagram 453 6 17 4 Basic Configuration 453 6 17 5 Functional Description 454 6 17 6 Comparator Reference Voltage CRV 455 6 17 7 Register Map 456 6 17 8 Register Description 457 6 18 Programmable Gain Amplifier PGA 467 6 18 1 Overview 467 1 1 4 Features 467 1 1 5 Block Diagram 467 1 1 6 Register Map 467 6 18 2 Register Description 468 7APPLICATION CIRCUIT 46...

Page 6: ... 6 Power Mode State Machine 48 Figure 6 2 7 NuMicro Mini57 Series Power Architecture Diagram 51 Figure 6 2 8 NuMicro Mini57 Flash Security and Configuration Map 55 Figure 6 2 9 SRAM Block Diagram 57 Figure 6 3 1 Clock Generator Block Diagram 113 Figure 6 3 2 Clock Generator Global View Diagram 114 Figure 6 3 3 System Clock Block Diagram 115 Figure 6 3 4 SysTick Clock Control Block Diagram 116 Figu...

Page 7: ...2 Figure 6 7 6 Enhanced Input Capture Timer Counter Interrupt Architecture Diagram 213 Figure 6 8 1 EPWM Clock Source 226 Figure 6 8 2 EPWM Block Diagram 227 Figure 6 8 3 EPWM Generator 0 1 Architecture Diagram 227 Figure 6 8 4 EPWM Generator 2 3 Architecture Diagram 227 Figure 6 8 5 EPWM Generator 4 5 Architecture Diagram 228 Figure 6 8 6 EPWM Edge aligned Waveform Output 229 Figure 6 8 7 EPWM Ed...

Page 8: ...Duty Ratio 281 Figure 6 9 10 Paired PWM Output with Dead zone Generation Operation 282 Figure 6 9 11 PWM Interrupt Architecture Diagram 282 Figure 6 10 1 Watchdog Timer Block Diagram 295 Figure 6 10 2 Watchdog Timer Clock Control Diagram 296 Figure 6 10 3 Watchdog Timer Time out Interval and Reset Period Timing 297 Figure 6 11 1 USCI Block Diagram 301 Figure 6 11 2 Input Conditioning for USCIx_DAT...

Page 9: ...USPITV 0x3 354 Figure 6 13 13 Auto Slave Select SUSPITV 0x3 354 Figure 6 13 14 SPI Timing in Master Mode 357 Figure 6 13 15 SPI Timing in Master Mode Alternate Phase of Serial Bus Clock 357 Figure 6 13 16 SPI Timing in Slave Mode 358 Figure 6 13 17 SPI Timing in Slave Mode Alternate Phase of Serial Bus Clock 358 Figure 6 14 1 I 2 C Bus Timing 384 Figure 6 14 2 USCI I C Mode Block Diagram 385 Figur...

Page 10: ...ck Control 431 Figure 6 16 3 Single Mode Conversion Timing Diagram 432 Figure 6 16 4 ADC Hardware Trigger Source 433 Figure 6 16 5 Independent Sample Mode Conversion Timing Diagram 433 Figure 6 16 6 Simultaneous Simple Mode Conversion Timing Diagram 434 Figure 6 16 7 Simultaneous Sequential 4R Mode Conversion Timing Diagram 434 Figure 6 17 1 Analog Comparator Block Diagram 453 Figure 6 17 2 Analog...

Page 11: ...Table Format 86 Table 6 3 1 Peripheral Clock Source Selection Table 118 Table 6 3 2 Power down Mode Control Table 123 Table 6 4 1 Flash Memory Address Map 135 Table 6 4 2 Data Flash Table 136 Table 6 4 3 Boot Selection 145 Table 6 4 4 Boot Selection and Supports Function 145 Table 6 4 5 ISP Command Table 149 Table 6 6 1 Input Capture Mode Operation 193 Table 6 10 1 Watchdog Timer Time out Interval...

Page 12: ...ions which need high CPU performance The Mini57 offers 29 5 Kbytes embedded program Flash size configurable Data Flash shared with program Flash 2 Kbytes Flash for the ISP 1 5 Kbytes SPROM for security and 4 Kbytes SRAM Many system level peripheral functions such as I O Port Timer UART SPI I 2 C PWM ADC Watchdog Timer Analog Comparator and Brown out Detector have been incorporated into the Mini57 ...

Page 13: ...PROM 4 KB SRAM for internal scratch pad RAM SRAM Clock Control Programmable system clock source Switch clock sources on the fly 4 24 MHz external crystal input HXT 32 768 kHz external crystal input LXT for idle wake up and system operation clock 48 MHz internal oscillator HIRC 1 accuracy at 25 0 C 5V Dynamically calibrating the HIRC OSC to 48 MHz 1 from 40 to 105 by external 32 768K crystal oscill...

Page 14: ... capture at most 4 edges continuously on one signal Continuous Capture Timer0 Timer1 and Systick have support Continuous capture function can Continuous Capture 4 edge on one signal Enhanced Input Capture One unit of 24 bit input capture counter Capture surce I O inputs ECAP0 ECAP1 and ECAP2 PWM Trigger ADC Trigger WDT Watchdog Timer Programmable clock source and time out period Supports wake up f...

Page 15: ...ither by software trigger PWM trigger ACMP trigger or external pin trigger Supports temperature sensor for measurement chip temperature Supports Simultaneous and Sequential function to continuous conversion 4 channels maximum Programmable Gain Amplifier PGA Supports 8 level gain selects from 1 2 3 5 7 9 11 and 13 Unity gain frequency up to 8 MHz Analog Comparator Two analog comparators with progra...

Page 16: ...t Detector 8 programmable threshold levels 4 3V 4 0V 3 7V 3 0V 2 7V 2 4V 2 2V 2 0V Supports Brown out interrupt and reset option 96 bit unique ID LVR Low Voltage Reset Operating Temperature 40 105 Reliability EFT 4KV ESD HBM pass 4KV Packages Green package RoHS 20 pin TSSOP 28 pin TSSOP 33 pin QFN ...

Page 17: ... Clock of Advanced High Performance Bus HIRC 48 MHz Internal High Speed RC Oscillator HXT 4 24 MHz External High Speed Crystal Oscillator ICP In Circuit Programming ISP In System Programming ISR Interrupt Service Routine LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator LIRC LXT 32 768 kHz External Low Speed Crystal Oscillator NVIC Nested Vectored Interrupt Controller PCLK The...

Page 18: ...ORMATION LIST AND PIN CONFIGURATION 4 1 NuMicro Mini57 Naming Rule Mini57 X X X ARM Based 32 bit Microcontroller CPU Core Corte M0 Flash ROM 57 29 5 KB Flash ROM Temperature Reserved Package Type F TSSOP 20 E TSSOP 28 T QFN 33 4x4mm E 40o C 105o C Figure 4 1 1 NuMicro Mini57 Series Selection Code ...

Page 19: ...ROM I O Timer Connectivity Comp PWM ADC PGA ISP ICP IAP IRC 10 kHz 48 MHz Package USCI Mini57TDE 29 5 KB 4 KB Configurable 2 5 KB up to 22 2x32 bit 2 2 8 8x12 bit v v v QFN33 4x4 Mini57EDE 29 5 KB 4 KB Configurable 2 5 KB up to 22 2x32 bit 2 2 8 8x12 bit v v v TSSOP28 Mini57FDE 29 5 KB 4 KB Configurable 2 5 KB up to 18 2x32 bit 2 2 8 8x12 bit v v v TSSOP20 Table 4 2 1 NuMicro Mini57 Series Selecti...

Page 20: ...1_MOSI UART1_RXD PA 2 EPWM_CH2 I2C0_SDA SPI0_MOSI SPI1_MISO UART0_RXD PA 3 EPWM_CH3 I2C0_SCL SPI0_CLK SPI1_SS UART0_TXD PB 1 ADC0_CH1 ACMP0_P1 ECAP_P1 PB 2 ADC0_CH2 BPWM_CH1 ACMP0_P2 ECAP_P2 PB 3 ACMP1_N PGA_I TM0 PB 4 ADC1_CH0 ACMP0_N TM1 PC 1 ADC0_CH4 STADC ACMP0_P3 ACMP1_P1 SPI0_MOSI SPI1_MISO PC 3 ACMP1_O PGA_O SPI0_CLK SPI1_SS nRESET PD 1 ICE_CLK ACMP1_P2 I2C0_SCL SPI0_CLK SPI1_SS UART0_TXD P...

Page 21: ...OSI SPI1_MISO UART0_RXD PA 3 EPWM_CH3 I2C0_SCL SPI0_CLK SPI1_SS UART0_TXD PB 1 ADC0_CH1 ACMP0_P1 ECAP_P1 PB 2 ADC0_CH2 BPWM_CH1 ACMP0_P2 ECAP_P2 PB 3 ACMP1_N PGA_I TM0 PB 4 ADC1_CH0 ACMP0_N TM1 PC 0 ADC0_CH3 BPWM_CH0 ACMP1_P0 I2C1_SCL SPI0_SS SPI1_CLK UART1_TXD PC 1 ADC0_CH4 STADC ACMP0_P3 ACMP1_P1 SPI0_MOSI SPI1_MISO PC 3 ACMP1_O PGA_O SPI0_CLK SPI1_SS nRESET PD 1 ICE_CLK ACMP1_P2 I2C0_SCL SPI0_C...

Page 22: ...32 1 24 Mini57 QFN 33 pin 31 30 29 28 27 26 25 23 22 21 20 19 18 17 10 9 11 12 13 14 15 16 2 3 4 5 6 7 8 LDO_CAP VSS VDD PD 6 PB 0 PB 1 PB 2 PB 4 PC 1 nRESET PB 3 PC 2 PD 2 PD 3 NC NC NC NC PD 5 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 PC 4 PC 0 PD 4 PD 1 PC 3 NC NC Figure 4 3 5 NuMicro Mini57 Series QFN 33 pin Diagram ...

Page 23: ...PI0_MISO SPI1_MOSI UART1_RXD PD 2 ICE_DAT ADC1_CH1 CCAP_P0 I2C0_SDA SPI0_MOSI SPI1_MISO UART0_RXD PD 3 BPWM_CH1 UART1_TXD NC NC NC NC PD 5 UART0_TXD PA 5 XT_OUT EPWM_CH5 ACMP0_O PA 4 XT_IN EPWM_CH4 PA 3 EPWM_CH3 I2C0_SCL SPI0_CLK SPI1_SS UART0_TXD PA 2 EPWM_CH2 I2C0_SDA SPI0_MOSI SPI1_MISO UART0_RXD PA 1 EPWM_CH1 I2C1_SDA SPI0_MISO SPI1_MOSI UART1_RXD PA 0 CLKO EPWM_CH0 I2C1_SCL SPI0_SS SPI1_CLK U...

Page 24: ...receiver input pin for UART0 3 PB 0 I O MFP0 General purpose digital I O pin ADC0_CH0 A MFP2 ADC0 channel0 analog input ACMP0_P0 A MFP4 Analog comparator0 positive input pin ECAP_P0 I MFP7 Enhanced Input Capture input pin 4 PB 1 I O MFP0 General purpose digital I O pin ADC0_CH1 A MFP2 ADC0 channel1 analog input ACMP0_P1 A MFP4 Analog comparator0 positive input pin ECAP_P1 I MFP7 Enhanced Input Cap...

Page 25: ...I MFP3 Brake input pin of EPWM CCAP_P1 I MFP7 Timer Continuous Capture input pin I2C1_SDA I O MFP8 I2 C1 data input output pin SPI0_MISO I O MFP9 SPI0 1st MISO Master In Slave Out pin SPI1_MOSI I O MFPA SPI1 MOSI Master Out Slave In pin UART1_RXD I MFPB Data receiver input pin for UART1 11 PD 2 I O MFP0 General purpose digital I O pin ICE_DAT I O MFP1 Serial wired debugger data pin ADC1_CH1 A MFP2...

Page 26: ...PI0_CLK I O MFP9 SPI0 serial clock pin SPI1_SS I O MFPA SPI1 slave select pin UART0_TXD O MFPB Data transmitter output pin for UART0 18 PC 3 I O MFP0 General purpose digital I O pin ACMP1_O O MFP5 Analog comparator1 output PGA_O A MFP6 PGA output pin SPI0_CLK I O MFP9 SPI0 serial clock pin SPI1_SS I O MFPA SPI1 slave select pin 19 PD 5 I O MFP0 General purpose digital I O pin UART0_TXD O MFPB Data...

Page 27: ...al purpose digital I O pin EPWM_CH1 I O MFP3 PWM channel1 output capture input I2C1_SDA I O MFP8 I2 C1 data input output pin SPI0_MISO I O MFP9 SPI0 1st MISO Master In Slave Out pin SPI1_MOSI I O MFPA SPI1 MOSI Master Out Slave In pin UART1_RXD I MFPB Data receiver input pin for UART1 25 PA 0 I O MFP0 General purpose digital I O pin CLKO O MFP1 Clock Out EPWM_CH0 I O MFP3 PWM channel0 output captu...

Page 28: ...ACMP0_P2 A MFP4 Analog comparator0 positive input pin ECAP_P2 I MFP7 Enhanced Input Capture input pin 5 PB 4 I O MFP0 General purpose digital I O pin ADC1_CH0 A MFP2 ADC1 channel0 analog input ACMP0_N A MFP4 Analog comparator0 negative input pin TM1 I O MFP7 Timer1 event counter input toggle output 6 PC 1 I O MFP0 General purpose digital I O pin ADC0_CH4 A MFP2 ADC0 channel4 analog input STADC I M...

Page 29: ...Master Out Slave In pin SPI1_MISO I O MFPA SPI1 MISO Master In Slave Out pin UART0_RXD I MFPB Data receiver input pin for UART0 11 PC 0 I O MFP0 General purpose digital I O pin ADC0_CH3 A MFP2 ADC0 channel3 analog input BPWM_CH0 I O MFP3 PWM channel0 output capture input ACMP1_P0 A MFP5 Analog comparator1 positive input pin I2C1_SCL I O MFP8 I2 C1 clock pin SPI0_SS I O MFP9 SPI0 slave select pin S...

Page 30: ...I1_SS I O MFPA SPI1 slave select pin UART0_TXD O MFPB Data transmitter output pin for UART0 17 PA 2 I O MFP0 General purpose digital I O pin EPWM_CH2 I O MFP3 PWM channel2 output capture input I2C0_SDA I O MFP8 I2 C0 data input output pin SPI0_MOSI I O MFP9 SPI0 1st MOSI Master Out Slave In pin SPI1_MISO I O MFPA SPI1 MISO Master In Slave Out pin UART0_RXD I MFPB Data receiver input pin for UART0 ...

Page 31: ...of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Pin No Pin Name Type MFP Description UART1_TXD O MFPB Data transmitter output pin for UART1 20 VSS A MFP0 Ground pin for digital circuit Table 4 4 2 TSSOP20 Pin Description ...

Page 32: ...ive input pin ECAP_P1 I MFP7 Enhanced Input Capture input pin 7 PB 2 I O MFP0 General purpose digital I O pin ADC0_CH2 A MFP2 ADC0 channel2 analog input BPWM_CH1 I O MFP3 PWM channel1 output capture input ACMP0_P2 A MFP4 Analog comparator0 positive input pin ECAP_P2 I MFP7 Enhanced Input Capture input pin 8 PB 4 I O MFP0 General purpose digital I O pin ADC1_CH0 A MFP2 ADC1 channel0 analog input AC...

Page 33: ...rial wired debugger data pin ADC1_CH1 A MFP2 ADC1 channel1 analog input CCAP_P0 I MFP7 Timer Continuous Capture input pin I2C0_SDA I O MFP8 I2 C0 data input output pin SPI0_MOSI I O MFP9 SPI0 1st MOSI Master Out Slave In pin SPI1_MISO I O MFPA SPI1 MISO Master In Slave Out pin UART0_RXD I MFPB Data receiver input pin for UART0 14 PD 3 I O MFP0 General purpose digital I O pin BPWM_CH1 I O MFP3 PWM ...

Page 34: ...UART0_RXD I MFPB Data receiver input pin for UART0 25 PA 1 I O MFP0 General purpose digital I O pin EPWM_CH1 I O MFP3 PWM channel1 output capture input I2C1_SDA I O MFP8 I2 C1 data input output pin SPI0_MISO I O MFP9 SPI0 1st MISO Master In Slave Out pin SPI1_MOSI I O MFPA SPI1 MOSI Master Out Slave In pin UART1_RXD I MFPB Data receiver input pin for UART1 26 PA 0 I O MFP0 General purpose digital ...

Page 35: ...nput pin for UART1 30 PD 1 I O MFP0 General purpose digital I O pin ICE_CLK I MFP1 Serial wired debugger clock pin ACMP1_P2 A MFP5 Analog comparator1 positive input pin I2C0_SCL I O MFP8 I2 C0 clock pin SPI0_CLK I O MFP9 SPI0 serial clock pin SPI1_SS I O MFPA SPI1 slave select pin UART0_TXD O MFPB Data transmitter output pin for UART0 31 PC 3 I O MFP0 General purpose digital I O pin ACMP1_O O MFP5...

Page 36: ... 1 MFP5 A Comparator1 positive input pin ACMP1_P0 PC 0 MFP5 A Comparator1 positive input pin ADC0 ADC0_CH0 PB 0 MFP2 A ADC0 analog input channel 0 ADC0_CH1 PB 1 MFP2 A ADC0 analog input channel 1 ADC0_CH2 PB 2 MFP2 A ADC0 analog input channel 2 ADC0_CH4 PC 1 MFP2 A ADC0 analog input channel 4 ADC0_CH3 PC 0 MFP2 A ADC0 analog input channel 3 ADC1 ADC1_CH0 PB 4 MFP2 A ADC1 analog input channel 0 ADC...

Page 37: ...rial wired debugger data pin ICE_CLK PD 1 MFP1 I Serial wired debugger clock pin nRESET nRESET I External reset pin internal pull high PGA PGA_I PB 3 MFP6 A PGA analog input pin PGA_O PC 3 MFP6 A PGA analog output pin SPI0 SPI0_MOSI PC 1 MFP9 I O SPI0 MOSI Master Out Slave In pin SPI0_MISO PC 2 MFP9 I O SPI0 MISO Master In Slave Out pin SPI0_MOSI PD 2 MFP9 I O SPI0 MOSI Master Out Slave In pin SPI...

Page 38: ...T0 data receiver input pin UART0_TXD PD 1 MFPB O UART0 data transmitter output pin UART0_TXD PA 3 MFPB O UART0 data transmitter output pin UART0_RXD PA 2 MFPB I UART0 data receiver input pin UART0_TXD PD 5 MFPB O UART0 data transmitter output pin UART0_RXD PD 6 MFPB I UART0 data receiver input pin UART1 UART1_RXD PC 2 MFPB I UART1 data receiver input pin UART1_TXD PC 0 MFPB O UART1 data transmitte...

Page 39: ...Mini57 Apr 06 2017 Page 39 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 5 BLOCK DIAGRAM 5 1 NuMicro Mini57 Block Diagram Figure 5 1 1 NuMicro Mini57 Block Diagram ...

Page 40: ... a result of an exception return Figure 6 1 1 shows the functional controller of processor Cortex M0 Processor Core Nested Vectored Interrupt Controller NVIC Breakpoint and Watchpoint Unit Debugger interface Bus matrix Debug Access Port DAP Debug Cortex M0 Processor Cortex M0 Components Wakeup Interrupt Controller WIC Interrupts Serial Wire or JTAG debug port AHB Lite interface Figure 6 1 1 Functi...

Page 41: ...VIC 32 external interrupt inputs each with four levels of priority Dedicated Non maskable Interrupt NMI input Supports for both level sensitive and pulse sensitive interrupt lines Supports Wake up Interrupt Controller WIC and providing Ultra low Power Sleep mode Debug support Four hardware breakpoints Two watchpoints Program Counter Sampling Register PCSR for non intrusive code profiling Single st...

Page 42: ...d by one of the events listed below These reset event flags can be read from SYS_RSTSTS register to determine the reset source Hardware reset can reset chip through peripheral reset signals Software reset can trigger reset through control registers Hardware Reset Sources Power on Reset POR Low level on the nRESET pin Watchdog Timer Time out Reset WDT Low Voltage Reset LVR Brown out Detector Reset ...

Page 43: ...al of 9 reset sources in the NuMicro family In general CPU reset is used to reset Cortex M0 only the other reset sources will reset Cortex M0 and all peripherals However there are small differences between each reset source and they are listed in Table 6 2 5 Reset Sources Register POR nRESET WDT LVR BOD CHIP MCU CPU SYS_RSTSTS 0x001 Bit 1 1 Bit 2 1 0x001 Bit 4 1 Bit 0 1 Bit 5 1 Bit 7 1 CHIPRST SYS...

Page 44: ...CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 CBS FMC_ISPSTS 2 1 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 VECMAP FMC_ISPSTS 20 9 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on ...

Page 45: ...CU When applying the power to MCU the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation At POR reset the PORF SYS_RSTSTS 0 will be set to 1 to indicate there is a POR reset event The PORF SYS_RSTSTS 0 bit can be cleared by writing 1 to it Figure 6 2 3 shows the waveform of Power On reset VDD VPOR Power On Reset 0 1V Figure 6 ...

Page 46: ... SYS_BODCTL 0 Brown Out Detector function will detect AVDD during system operation When the AVDD voltage is lower than VBOD which is decided by BODEN SYS_BODCTL 0 and BODVL SYS_BODCTL 2 1 and the state keeps longer than De glitch time Max 20 HCLK cycles 1 LIRC cycle chip will be reset The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps lon...

Page 47: ...set Software can check if the reset is caused by watchdog time out to indicate the previous reset is a watchdog reset and handle the failure of MCU after watchdog time out reset by checking WDTRF SYS_RSTSTS 2 6 2 2 6 CPU Reset CHIP Reset and SYSTEM Reset The CPU Reset means only Cortex M0 core is reset and all other peripherals remain the same status after CPU reset User can set the CPURST SYS_IPR...

Page 48: ...s All All except CPU clock LXT and LIRC After Wake up N A CPU back to normal mode CPU back to normal mode Table 6 2 2 Power Mode Difference Table Normal Mode CPU Clock ON HXT HIRC LXT LIRC HCLK PCLK ON Flash ON Power down Mode CPU Clock OFF HXT HIRC HCLK PCLK OFF Flash Halt System reset released CPU executes WFI Interrupts occur Idle Mode CPU Clock OFF HXT HIRC LXT LIRC HCLK PCLK ON Flash Halt 1 S...

Page 49: ...e following wake up sources can wake chip up to normal mode Table 6 2 4 lists the condition about how to enter Power down mode again for each peripheral User needs to wait this condition before setting PDEN CLK_PWRCTL 7 and execute WFI to enter Power down mode Wake Up Source Wake Up Condition System Can Enter Power Down Mode Again Condition BOD Brown Out Detector Interrupt After software writes 1 ...

Page 50: ...0 USCI I2 C Data toggle After software writes 1 to clear WKF UI2C_WKSTS 0 Address match After software writes 1 to clear WKAKDONE UI2C_PROTSTS 16 then writes 1 to clear WKF UI2C_WKSTS 0 ACMP Comparator Power down Wake Up Interrupt After software writes 1 to clear ACMPF0 ACMP_STATUS 0 and ACMPF1 ACMP_STATUS 1 Table 6 2 4 Condition of Entering Power down Mode Again ...

Page 51: ...igital operation A built in capacitor for internal voltage regulator The output of internal voltage regulator LDO does not require an external capacitor and doesn t bond out to external pin Analog power AVDD should be the same voltage level of the digital power VDD V DD V SS 48 MHz HIRC Oscillator 10 kHz LIRC Oscillator SRAM IO Cell POR50 POR15 Temperature Sensor 4 24 MHz or 32 768 kHz crystal osc...

Page 52: ...exer Control 0x5000_0300 INT_BA Clock Control 0x5000_0200 CLK_BA System Global Control 0x5000_0000 SYS_BA 0x4020_0000 0x401F_FFFF 1 GB 0x4000_0000 APB peripherals 0x3FFF_FFFF ECAP Control 0x401B_0000 ECAP_BA USCI1 Control 0x4017_0000 USCI1_BA BPWM Control 0x4014_0000 BPWM_BA PGA Control 0x400F_0000 PGA_BA ADC Control 0x400E_0000 ADC_BA 0x2000_1000 ACMP 0 1 Control 0x400D_0000 ACMP_BA 0x2000_0FFF U...

Page 53: ...te Protect 0 CHIPRST Chip One shot Reset Write Protect SYS_BODCTL 15 LVREN Low Voltage Reset Enable Control Write Protect 6 BODLPM Brown out Detector Low Power Mode Write Protect 4 BODRSTEN Brown out Reset Enable Control Write Protect 3 1 BODVL Brown out Detector Threshold Voltage Selection Write Protect 0 BODEN Brown out Detector Enable Control Write Protect SYS_PORCTL 15 0 POROFF Power on Reset ...

Page 54: ...ICEDEBUG ICE Debug Mode Acknowledge Disable Control Write Protect TIMER1_CTL 31 ICEDEBUG ICE Debug Mode Acknowledge Disable Control Write Protect WDT_CTL 31 ICEDEBUG ICE Debug Mode Acknowledge Disable Control Write Protect 7 WDTEN Watchdog Timer Enable Control Write Protect 6 INTEN Watchdog Timer Time out Interrupt Enable Control Write Protect 4 WKEN Watchdog Timer Time out Wake up Function Contro...

Page 55: ...ction ROM0 SPROM0 512B Security Protection ROM0 SPROM0 512B Reserved Reserved 0x0030_0000 0x0030_0004 User Configuration 8B User Configuration 8B Reserved Reserved 0x0024_0000 0x0024_01FF Security Protection ROM1 SPROM1 512B Security Protection ROM1 SPROM1 512B Reserved Reserved 0x0028_0000 0x0028_01FF Security Protection ROM2 SPROM1 512B Security Protection ROM2 SPROM1 512B Reserved Reserved Figu...

Page 56: ...isters 0x5001_4000 0x5001_7FFF HDIV_BA Hardware Divider Control Register APB Controllers Space 0x4000_0000 0x401F_FFFF 0x4000_4000 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4001_0000 0x4001_3FFF TMR01_BA Timer0 Timer1 Control Registers 0x4004_0000 0x4004_3FFF EPWM_BA Enhance PWM Control Registers 0x4007_0000 0x4007_3FFF USCI0_BA USCI0 Control Registers 0x400D_0000 0x400D_3FFF ACMP_BA A...

Page 57: ...NUAL 6 2 7 3 SRAM Memory Organization The Mini57 supports embedded SRAM with total 4 Kbytes size Supports total 4 Kbytes SRAM Supports byte half word word write Supports oversize response error AHB Bus SRAM 4KB SRAM decoder AHB interface controller Figure 6 2 9 SRAM Block Diagram ...

Page 58: ... 0x0000_80XX SYS_IVSCTL SYS_BA 0x1C R W Internal Voltage Source Control Register 0x0000_0000 SYS_PORCTL SYS_BA 0x24 R W Power On Reset Controller Register 0x0000_00XX SYS_GPA_MFP SYS_BA 0x30 R W GPIOA Multiple Function Control Register 0x0000_0000 SYS_GPB_MFP SYS_BA 0x34 R W GPIOB Multiple Function Control Register 0x0000_0000 SYS_GPC_MFP SYS_BA 0x38 R W GPIOC Multiple Function Control Register 0x...

Page 59: ...art number has a unique default reset value 31 30 29 28 27 26 25 24 PDID 23 22 21 20 19 18 17 16 PDID 15 14 13 12 11 10 9 8 PDID 7 6 5 4 3 2 1 0 PDID Bits Description 31 0 PDID Part Device Identification Number Read Only This register reflects device part number code Software can read this register to identify which device is used NuMicro Mini57 Series Part Device Identification Number Mini57TDE 0...

Page 60: ... 1 to reset Cortex M0 Core and Flash Memory Controller FMC 0 No reset from CPU 1 The Cortex M0 Core and FMC are reset by software setting CPURST to 1 Note Write 1 to clear this bit to 0 6 Reserved Reserved 5 SYSRF System Reset Flag The system reset flag is set by the Reset Signal from the Cortex M0 Core to indicate the previous reset source 0 No reset from Cortex M0 1 The Cortex M0 had issued the ...

Page 61: ...set the system Note1 Write 1 to clear this bit to 0 Note2 Watchdog Timer register RSTF WDT_CTL 2 bit is set if the system has been reset by WDT time out reset Window Watchdog Timer register WWDTRF WWDT_STATUS 1 bit is set if the system has been reset by WWDT time out reset 1 PINRF NRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previou...

Page 62: ...ory Controller FMC and this bit will automatically return to 0 after the 2 clock cycles 0 Processor core normal operation 1 Processor core one shot reset Note This bit is write protected Refer to the SYS_REGLCTL register 0 CHIPRST Chip One shot Reset Write Protect Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 aft...

Page 63: ...16 Reserved EPWMRST Reserved BPWMRST 15 14 13 12 11 10 9 8 Reserved PGARST Reserved CAPRST 7 6 5 4 3 2 1 0 Reserved TMR1RST TMR0RST GPIORST Reserved Bits Description 31 Reserved Reserved 30 ACMPRST ACMP Controller Reset 0 ACMP controller normal operation 1 ACMP controller reset 29 Reserved Reserved 28 ADCRST ADC Controller Reset 0 ADC controller normal operation 1 ADC controller reset 27 26 Reserv...

Page 64: ...tion 1 PGA controller reset 11 9 Reserved Reserved 8 CAPRST ECAP Controller Reset 0 ECAP controller normal operation 1 ECAP controller reset 7 4 Reserved Reserved 3 TMR1RST Timer1 Controller Reset 0 Timer1 controller normal operation 1 Timer1 controller reset 2 TMR0RST Timer0 Controller Reset 0 Timer0 controller normal operation 1 Timer0 controller reset 1 GPIORST GPIO Controller Reset 0 GPIO cont...

Page 65: ...r 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved HCLKWS Bits Description 31 1 Reserved Reserved 0 HCLKWS HCLK Wait State Cycle Control Bit This bit is used to enable disable HCLK wait state when access Flash 0 No wait state 1 One wait state inserted when CPU access Flash Note When HCLK frequency is faster than 4...

Page 66: ... voltage is lower than LVR circuit setting LVR function is enabled by default 0 Low Voltage Reset function Disabled 1 Low Voltage Reset function Enabled Note This bit is write protected Refer to the SYS_REGLCTL register 14 8 Reserved Reserved 7 BODOUT Brown out Detector Output Status 0 Brown out Detector output status is 0 It means the detected voltage is higher than BODVL setting or BODEN is 0 1 ...

Page 67: ...is enabled BODRSTEN low BOD will assert an interrupt if BODOUT is high BOD interrupt will keep till to the BODEN set to 0 BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function set BODEN low BOD will wake CPU up when BODOUT is high in power down mode Note2 This bit is write protected Refer to the SYS_REGLCTL register 3 1 BODVL Brown out Detector Threshold Voltag...

Page 68: ...ved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved VTEMPEN Bits Description 31 1 Reserved Reserved 0 VTEMPEN Temperature Sensor Enable Bit This bit is used to enable disable temperature sensor function 0 Temperature sensor function Disabled default 1 Temperature sensor function Enabled Note After this bit is set to 1 the value of temperature sensor output ...

Page 69: ...rved 15 0 POROFF Power on Reset Enable Bit Write Protect When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field The POR function will be active again when this field is set to another value or...

Page 70: ...Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PA5MFP PA4MFP 15 14 13 12 11 10 9 8 PA3MFP PA2MFP 7 6 5 4 3 2 1 0 PA1MFP PA0MFP Bits Description 31 24 Reserved Reserved 23 20 PA5MFP PA 5 Multi function Pin Selection 19 16 PA4MFP PA 4 Multi function Pin Selection 15 12 PA3MFP PA 3 Multi function Pin Selection 11 8 PA2MFP PA 2 Multi function Pin Selection 7 4 PA...

Page 71: ...IOB Multiple Function Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PB4MFP 15 14 13 12 11 10 9 8 PB3MFP PB2MFP 7 6 5 4 3 2 1 0 PB1MFP PB0MFP Bits Description 31 20 Reserved Reserved 19 16 PB4MFP PB 4 Multi function Pin Selection 15 12 PB3MFP PB 3 Multi function Pin Selection 11 8 PB2MFP PB 2 Multi function Pin Selection 7 4 PB1MFP PB 1 Multi functio...

Page 72: ...IOC Multiple Function Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved PC4MFP 15 14 13 12 11 10 9 8 PC3MFP PC2MFP 7 6 5 4 3 2 1 0 PC1MFP PC0MFP Bits Description 31 20 Reserved Reserved 19 16 PC4MFP PC 4 Multi function Pin Selection 15 12 PC3MFP PC 3 Multi function Pin Selection 11 8 PC2MFP PC 2 Multi function Pin Selection 7 4 PC1MFP PC 1 Multi functio...

Page 73: ...0x0000_0111 31 30 29 28 27 26 25 24 Reserved PD6MFP 23 22 21 20 19 18 17 16 PD5MFP PD4MFP 15 14 13 12 11 10 9 8 PD3MFP PD2MFP 7 6 5 4 3 2 1 0 PD1MFP Reserved Bits Description 31 28 Reserved Reserved 27 24 PD6MFP PD 6 Multi function Pin Selection 23 20 PD5MFP PD 5 Multi function Pin Selection 19 16 PD4MFP PD 4 Multi function Pin Selection 15 12 PD3MFP PD 3 Multi function Pin Selection 11 8 PD2MFP P...

Page 74: ...l be cleared to 00 00 Trim retry count limitation is 64 loops 01 Trim retry count limitation is 128 loops 10 Trim retry count limitation is 256 loops 11 Trim retry count limitation is 512 loops 5 4 LOOPSEL Trim Calculation Loop Selection This field defines that trim value calculation is based on how many 32 768 kHz clock 00 Trim value calculation is based on average difference in 4 32 768 kHz cloc...

Page 75: ...TS 2 is set during auto trim operation an interrupt will be triggered to notify the clock frequency is inaccuracy 0 CLKERRIF SYS_IRCTSTS 2 status to trigger an interrupt to CPU Disabled 1 CLKERRIF SYS_IRCTSTS 2 status to trigger an interrupt to CPU Enabled 1 TFAILIEN Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count ...

Page 76: ...tify the clock frequency is inaccuracy Write 1 to clear this to 0 0 Clock frequency is accuracy 1 Clock frequency is inaccuracy 1 TFAILIF Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn t be locked Once this bit is set the auto trim operation stopped and FREQSEL SYS_iRCTCTL 1 0 will be cleared to 00 by h...

Page 77: ...nd then write any data to the address 0x5000_0100 to enable register protection This register is writen to disable enable register protection and read for the REGLCTL status Register Offset R W Description Reset Value SYS_REGLCTL SYS_BA 0x100 R W Register Write Protection Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7...

Page 78: ...r 0x0XXX_0XXX 31 30 29 28 27 26 25 24 Reserved VTEMP1 23 22 21 20 19 18 17 16 VTEMP1 15 14 13 12 11 10 9 8 Reserved VTEMP0 7 6 5 4 3 2 1 0 VTEMP0 Bits Description 31 28 Reserved Reserved 27 16 VTEMP1 Temperature Sensor Offset Value This field reflects temperature sensor output voltage offset at 125o C 15 12 Reserved Reserved 11 0 VTEMP0 Temperature Sensor Offset Value This field reflects temperatu...

Page 79: ...used to determine if an action completed within a set duration as part of a dynamic clock management control loop When enabled the timer will count down from the value in the SysTick Current Value Register SYST_CVR to 0 and reload wrap to the value in the SysTick Reload Value Register SYST_RVR on the next clock edge and then decrement on subsequent clocks When the counter transitions to 0 the COUN...

Page 80: ...y W write only R W both read and write W C write 1 to clear Register Offset R W Description Reset Value SCS Base Address SCS_BA 0xE000_E000 SYST_CTL SCS_BA 0x10 R W SysTick Control and Status 0x0000_0004 SYST_RVR SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX SYST_CVR SCS_BA 0x18 R W SysTick Current Value Register 0xXXXX_XXXX ...

Page 81: ...Was Read 0 COUNTFLAG is cleared on read or by a write to the Current Value register 1 COUNTFLAG is set by a count transition from 1 to 0 15 3 Reserved Reserved 2 CLKSRC System Tick Clock Source Select Bit 0 Clock source is optional refer to STCLKSEL 1 Core clock used for SysTick timer 1 TICKINT System Tick Interrupt Enable Bit 0 Counting down to 0 will not cause the SysTick exception to be pended ...

Page 82: ...ption Reset Value SYST_RVR SCS_BA 0x14 R W SysTick Reload Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 RELOAD 15 14 13 12 11 10 9 8 RELOAD 7 6 5 4 3 2 1 0 RELOAD Bits Description 31 24 Reserved Reserved 23 0 RELOAD System Tick Reload Value Value to load into the Current Value register when the counter reaches 0 ...

Page 83: ...X_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CURRENT 15 14 13 12 11 10 9 8 CURRENT 7 6 5 4 3 2 1 0 CURRENT Bits Description 31 24 Reserved Reserved 23 0 CURRENT System Tick Current Value Current counter value This is the value of the counter at the time it is sampled The counter does not provide read modify write protection The register is write clear A software write of any val...

Page 84: ...ncluding the registers PC PSR LR R0 R3 R12 to the stack At the end of the ISR the NVIC will restore the mentioned registers from stack and resume the normal execution Thus it will take less and deterministic time to process the interrupt request The NVIC supports Tail Chaining which handles back to back interrupts efficiently without the overhead of states saving and restoration and therefore redu...

Page 85: ...exceptions 16 0 BOD_OUT Brown Out low voltage detected interrupt 17 1 WDTPINT Watchdog Timer interrupt 18 2 USCI0 USCI0 interrupt 19 3 USCI1 USCI1 interrupt 20 4 GP_INT External interrupt from GPA GPD pins 21 5 EPWM_INT EPWM interrupt 22 6 BRAKE0_INT EPWM brake interrupt from PWM0 or PWM_BRAKE pin 23 7 BRAKE1_INT EPWM brake interrupt from PWM1 24 8 BPWM0_INT BPWM0 interrupt 25 9 BPWM1_INT BPWM1 in...

Page 86: ...y point addresses for all exception handlers The vector number on previous page defines the order of entries in the vector table associated with the exception handler entry as illustrated in previous section Vector Table Word Offset Bytes Description 0x00 Initial Stack Pointer Value Exception Number 0x04 Exception Entry Pointer using that Exception Number Table 6 2 10 Vector Table Format 6 2 11 5 ...

Page 87: ...y both registers reading back the current pended state of the corresponding interrupts The Clear Pending Register has no effect on the execution status of an Active interrupt NVIC interrupts are prioritized by updating an 8 bit field within a 32 bit register each register supporting four interrupts The general registers associated with the NVIC are all accessible from a block of memory in the Syst...

Page 88: ...r Pending Control Register 0x0000_0000 NVIC_IPR0 SCS_BA 0x400 R W IRQ0 IRQ3 Interrupt Priority Control Register 0x0000_0000 NVIC_IPR1 SCS_BA 0x404 R W IRQ4 IRQ7 Interrupt Priority Control Register 0x0000_0000 NVIC_IPR2 SCS_BA 0x408 R W IRQ8 IRQ11 Interrupt Priority Control Register 0x0000_0000 NVIC_IPR3 SCS_BA 0x40C R W IRQ12 IRQ15 Interrupt Priority Control Register 0x0000_0000 NVIC_IPR4 SCS_BA 0...

Page 89: ...26 25 24 SETENA 23 22 21 20 19 18 17 16 SETENA 15 14 13 12 11 10 9 8 SETENA 7 6 5 4 3 2 1 0 SETENA Bits Description 31 0 SETENA Interrupt Enable Register Enable one or more interrupts Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Write operation 0 No effect 1 Write 1 to enable associated interrupt Read operation 0 Associated interrupt status Disabled 1 Associated...

Page 90: ... 25 24 CLRENA 23 22 21 20 19 18 17 16 CLRENA 15 14 13 12 11 10 9 8 CLRENA 7 6 5 4 3 2 1 0 CLRENA Bits Description 31 0 CLRENA Interrupt Disable Register Disable one or more interrupts Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Write operation 0 No effect 1 Write 1 to disable associated interrupt Read operation 0 Associated interrupt status Disabled 1 Associate...

Page 91: ...8 27 26 25 24 SETPEND 23 22 21 20 19 18 17 16 SETPEND 15 14 13 12 11 10 9 8 SETPEND 7 6 5 4 3 2 1 0 SETPEND Bits Description 31 0 SETPEND Set Interrupt Pending Register Write operation 0 No effect 1 Write 1 to set pending state Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Read operation 0 Associated interrupt in not in pending status 1 Associated interrupt is in...

Page 92: ...8 27 26 25 24 CLRPEND 23 22 21 20 19 18 17 16 CLRPEND 15 14 13 12 11 10 9 8 CLRPEND 7 6 5 4 3 2 1 0 CLRPEND Bits Description 31 0 CLRPEND Clear Interrupt Pending Register Write operation 0 No effect 1 Write 1 to clear pending state Each bit represents an interrupt number from IRQ0 IRQ31 Vector number from 16 47 Read operation 0 Associated interrupt in not in pending status 1 Associated interrupt i...

Page 93: ... 13 12 11 10 9 8 PRI_1 Reserved 7 6 5 4 3 2 1 0 PRI_0 Reserved Bits Description 31 30 PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes the lowest...

Page 94: ... 13 12 11 10 9 8 PRI_5 Reserved 7 6 5 4 3 2 1 0 PRI_4 Reserved Bits Description 31 30 PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes the lowest...

Page 95: ... 13 12 11 10 9 8 PRI_9 Reserved 7 6 5 4 3 2 1 0 PRI_8 Reserved Bits Description 31 30 PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes the lo...

Page 96: ...3 12 11 10 9 8 PRI_13 Reserved 7 6 5 4 3 2 1 0 PRI_12 Reserved Bits Description 31 30 PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes the ...

Page 97: ...3 12 11 10 9 8 PRI_17 Reserved 7 6 5 4 3 2 1 0 PRI_16 Reserved Bits Description 31 30 PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes the ...

Page 98: ...3 12 11 10 9 8 PRI_21 Reserved 7 6 5 4 3 2 1 0 PRI_20 Reserved Bits Description 31 30 PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes the ...

Page 99: ...3 12 11 10 9 8 PRI_25 Reserved 7 6 5 4 3 2 1 0 PRI_24 Reserved Bits Description 31 30 PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes the ...

Page 100: ...3 12 11 10 9 8 PRI_29 Reserved 7 6 5 4 3 2 1 0 PRI_28 Reserved Bits Description 31 30 PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority 21 16 Reserved Reserved 15 14 PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes the ...

Page 101: ...e specific control registers to facilitate the interrupt functions including NMI source selection and IRQ number identity which are described below R read only W write only R W both read and write Register Offset R W Description Reset Value INT Base Address INT_BA 0x5000_0300 INT_NMICTL INT_BA 0x80 R W NMI Source Interrupt Select Control Register 0x0000_0000 INT_IRQSTS INT_BA 0x84 R W MCU IRQ Numb...

Page 102: ... Reserved NMISELEN 7 6 5 4 3 2 1 0 Reserved NMISEL Bits Description 31 9 Reserved Reserved 8 NMISELEN NMI Interrupt Enable Bit Write Protected 0 NMI interrupt Disabled 1 NMI interrupt Enabled Note This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection Refer to the register SYS_REGLCTL at address SYS_BA 0x100 7 5 Rese...

Page 103: ...ts Description 31 0 IRQ MCU IRQ Source Register The IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex M0 core There is one mode to generate interrupt to Cortex M0 the normal mode The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex M0 When the IRQ n is 0 setting IRQ n to 1 will generate an interru...

Page 104: ...12 System Control Registers Key control and status features of Cortex M0 are managed centrally in a System Control Block within the System Control Registers For more detailed information please refer to the ARM Cortex M0 Technical Reference Manual and ARM v6 M Architecture Reference Manual ...

Page 105: ...CS_BA 0xE000_E000 SCS_CPUID SCS_BA 0xD00 R CPUID Base Register 0x410C_C200 SCS_ICSR SCS_BA 0xD04 R W Interrupt Control State Register 0x0000_0000 SCS_AIRCR SCS_BA 0xD0C R W Application Interrupt and Reset Control Register 0xFA05_0000 SCS_SCR SCS_BA 0xD10 R W System Control Register 0x0000_0000 SCS_SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 SCS_SHPR3 SCS_BA 0xD20 R W Syst...

Page 106: ...ister 0x410C_C200 31 30 29 28 27 26 25 24 IMPLEMENTER 23 22 21 20 19 18 17 16 Reserved PART 15 14 13 12 11 10 9 8 PARTNO 7 6 5 4 3 2 1 0 PARTNO REVISION Bits Description 31 24 IMPLEMENTER Implementer Code Implementer code assigned by ARM ARM 0x41 23 20 Reserved Reserved 19 16 PART Architecture of the Processor Reads as 0xC for ARMv6 M parts 15 4 PARTNO Part Number of the Processor Reads as 0xC20 3...

Page 107: ...priority exception normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit Entering thehandler then clears this bit to 0 This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler 30 29 Reserved Reserved 28 PENDSVSET PendSV Set pending Bit Write Operation 0 No ef...

Page 108: ...ET and write 1 to PENDSTCLR at the same time 24 Reserved Reserved 23 ISRPREEMPT Interrupt Preempt Bit Read Only If set a pending exception will be serviced on exit from the debug halt state 22 ISRPENDING Interrupt Pending Flag Excluding NMI and Faults Read Only 0 Interrupt not pending 1 Interrupt pending 21 Reserved Reserved 20 12 VECTPENDING Exception Number of the Highest Priority Pending Enable...

Page 109: ... writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status Read Operation Read as 0xFA05 15 3 Reserved Reserved 2 SYSRESETREQ System Reset Request Writing this bit 1 will cause a reset signal to be asserted...

Page 110: ...e up theprocessor When an event or interrupt enters pending state the event signal wakes up the processorfrom WFE If the processor is not waiting for an event the event is registered and affectsthe next WFE The processor also wakes up on execution of an SEV instruction or an external event 3 Reserved Reserved 2 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection Controls whether the processor ...

Page 111: ... Value SCS_SHPR2 SCS_BA 0xD1C R W System Handler Priority Register 2 0x0000_0000 31 30 29 28 27 26 25 24 PRI_11 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_11 Priority of System Handler 11 SVCall 0 denotes the highest priority and 3 denotes the lowest priority 29 0 Reserved Reserved ...

Page 112: ...00_0000 31 30 29 28 27 26 25 24 PRI_15 Reserved 23 22 21 20 19 18 17 16 PRI_14 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 30 PRI_15 Priority of System Handler 15 SysTick 0 denotes the highest priority and 3 denotes the lowest priority 29 24 Reserved Reserved 23 22 PRI_14 Priority of System Handler 14 PendSV 0 denotes the highest priority and 3 denotes the ...

Page 113: ...n Power down mode the clock controller turns off the 4 24 MHz external high speed crystal HXT and 48 MHz internal high speed RC oscillator HIRC to reduce the overall system power consumption Figure 6 3 2 shows the clock generator and the overview of the clock source control The clock generator consists of 4 clock sources which are listed below 32 768 kHz external low speed crystal oscillator LXT 4...

Page 114: ... 1 HCLKDIV 1 HCLK 48 MHz CLK_CLKSEL1 10 8 CLK_CLKSEL1 14 12 48 MHz 10 kHz 11 10 CLK_CLKSEL1 1 0 HCLK 1 2048 00 4 24MHz 32 768kHz 11 48 MHz 011 T0 T1 HCLK 4 24 MHz 32 768kHz 48 MHz CLK_CLKSEL1 31 30 11 10 00 HCLK 4 24 MHz 32 768kHz 48 MHz CLK_CLKSEL1 5 4 11 10 00 BOD 10 kHz ADC Clock Output PCLK HCLK 4 24MHz 32 768kHz USCI0_BRGEN 0 1 0 USCI0 PWM 54 HCLK CPUCLK 1 ADCDIV 1 PWM 10 HCLK HCLK USCI1_BRGE...

Page 115: ...YS_IRCTCTL 5 4 trim calculation loop and RETRYCNT SYS_IRCTCTL 7 6 trim value update limitation count to 11 6 3 3 System Clock and SysTick Clock The system clock has three clock sources which were generated from clock generator block The clock source switch depends on the register HCLKSEL CLK_CLKSEL0 1 0 The block diagram is shown in Figure 6 3 3 11 01 4 24 MHz HXT or 32 768 kHz LXT 10 kHz LXT HCLK...

Page 116: ...32 768 kHz LXT HCLK 48 MHz HIRC 00 1 2 1 2 1 2 CLK_CLKSEL0 4 3 1 0 SysTick SYST_CTL 2 CPUCLK Figure 6 3 4 SysTick Clock Control Block Diagram 6 3 4 Peripherals Clock Source Selection The peripheral clock has different clock source switch settings depending on different peripherals Please refer to the CLK_CLKSEL1 and CLK_APBCLK register description in section 6 3 8 Please note that while switching ...

Page 117: ...CKEN CLK_APBCLK 12 EPWMCKEN CLK_APBCLK 20 BPWMCKEN CLK_APBCLK 16 USCI0CKEN CLK_APBCLK 24 USCI1CKEN CLK_APBCLK 25 ADCCKEN CLK_APBCLK 28 ACMPCKEN CLK_APBCLK 30 Frequency Divider PGA EPWM BPWM USCI0 USCI1 ADC ACMP WDTCKEN CLK_APBCLK 0 PCLK Watch Dog Timer ECAP ECAPCKEN CLK_APBCLK 8 UART1CKEN CLK_APBCLK 17 UART1 Figure 6 3 5 Peripherals Bus Clock Source Selection for PCLK ...

Page 118: ...k source is fixed to PCLK 6 3 5 Power down Mode Clock When entering Power down mode system clocks some clock sources and some peripheral clocks are disabled Some clock sources and peripherals clock are still active in Power down mode The clocks still kept active are listed below Clock Generator 10 kHz internal low speed oscillator LIRC clock 32 768 kHz external low speed crystal oscillator LXT clo...

Page 119: ... till divided clock reaches low state and stay in low state if DIV1EN CLK_CLKOCTL 5 set to 1 the frequency divider clock will bypass power of 2 frequency divider The frequency divider clock will be output to CLKO pin directly 11 10 01 00 HCLK Reserved 4 24 MHz HXT or 32 768 kHz LXT 48 MHz HIRC CLKOSEL CLK_CLKSEL1 31 30 CLKOCKEN CLK_APBCLK 6 CLKO_CLK Legend HXT 4 24 MHz external high speed crystal ...

Page 120: ...LK CLK_BA 0x04 R W AHB Devices Clock Enable Control Register 0x0000_0014 CLK_APBCLK CLK_BA 0x08 R W APB Devices Clock Enable Control Register 0x0000_0001 CLK_CLKSEL0 CLK_BA 0x10 R W Clock Source Select Control Register 0 0x0000_001B CLK_CLKSEL1 CLK_BA 0x14 R W Clock Source Select Control Register 1 0xC307_7733 CLK_CLKDIV CLK_BA 0x20 R W Clock Divider Number Register 0x0000_0000 CLK_STATUS CLK_BA 0...

Page 121: ...sed to enlarge the gain of crystal to make sure crystal work normally If gain control is enabled crystal will consume more power than gain control off 00 HXT frequency is lower than from 8 MHz 01 HXT frequency is from 8 MHz to 12 MHz 10 HXT frequency is from 12 MHz to 16 MHz 11 HXT frequency is higher than 16 MHz Note This bit is write protected Refer to the SYS_REGLCTL register 9 PDLXT LXT Alive ...

Page 122: ... wakes up from Power down mode the clock control will delay certain clock cycles to wait system clock stable The delayed clock cycle is 4096 clock cycles when chip works at 4 24 MHz external high speed crystal oscillator HXT and 256 clock cycles when chip works at 48 MHz internal high speed RC oscillator HIRC 0 Clock cycles delay Disabled 1 Clock cycles delay Enabled Note This bit is write protect...

Page 123: ...is disabled Power down mode CPU enters Deep Sleep mode 1 1 YES Most clocks are disabled except LIRC LXT and only RTC WDT Timer peripheral clocks still enable if their clock sources are selected as LIRC LXT Table 6 3 2 Power down Mode Control Table When the chip enters Power down mode user can wake up chip by some interrupt sources User should enable the related interrupt sources and NVIC IRQ enabl...

Page 124: ...ock Enable Control Register 0x0000_0014 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved HDIVCKEN Reserved ISPCKEN Reserved Bits Description 31 5 Reserved Reserved 4 HDIVCKEN Hardware Divider Controller Clock Enable Bit 0 HDIV peripheral clock Disabled 1 HDIV peripheral clock Enabled 3 Reserved Reserved 2 ISPCKEN Flash ISP Co...

Page 125: ... 6 5 4 3 2 1 0 Reserved CLKOCKEN Reserved TMR1CKEN TMR0CKEN Reserved WDTCKEN Bits Description 31 Reserved Reserved 30 ACMPCKEN Analog Comparator Clock Enable Bit 0 Analog comparator clock Disabled 1 Analog comparator clock Enabled 29 Reserved Reserved 28 ADCCKEN Analog digital converter ADC Clock Enable Bit 0 ADC clock Disabled 1 ADC clock Enabled 27 26 Reserved Reserved 25 USCI1CKEN USCI1 Clock E...

Page 126: ...d 7 Reserved Reserved 6 CLKOCKEN CLKO Clock Enable Bit 0 CLKO clock Disabled 1 CLKO clock Enabled 5 4 Reserved Reserved 3 TMR1CKEN Timer1 Clock Enable Bit 0 Timer1 clock Disabled 1 Timer1 clock Enabled 2 TMR0CKEN Timer0 Clock Enable Bit 0 Timer0 clock Disabled 1 Timer0 clock Enabled 1 Reserved Reserved 0 WDTCKEN Watchdog Timer Clock Enable Bit Write Protect 0 Watchdog timer clock Disabled 1 Watchd...

Page 127: ...t If SYST_CTL 2 0 SysTick uses the clock source listed below 00 Clock source from HXT LXT 01 Clock source from HXT or LXT 2 10 Clock source from HCLK 2 11 Clock source from HIRC 2 Other Reserved Note if SysTick clock source is not from HCLK i e SYST_CTL 2 0 SysTick clock source must less than or equal to HCLK 2 Note This bit is write protected Refer to the SYS_REGLCTL register 2 Reserved Reserved ...

Page 128: ...scillator HXT or LXT 01 Reserved 10 Clock source from HCLK 11 Clock source from 48 MHz internal high speed RC oscillator HIRC 29 15 Reserved Reserved 14 12 TMR1SEL TIMER1 Clock Source Selection 000 Clock source from external crystal oscillator HXT or LXT 001 Clock source from 10 kHz internal low speed RC oscillator LIRC 010 Clock source from HCLK 011 Clock source from external clock T1 pin 111 Clo...

Page 129: ...ock source is from HCLK 11 Clock source from 48 MHz internal high speed RC oscillator HIRC 3 2 Reserved Reserved 1 0 WDTSEL Watchdog Timer Clock Source Selection Write Protect 00 Clock source from external crystal oscillator HXT or LXT 01 Reserved 10 Clock source from HCLK0 2048 11 Clock source from 10 kHz internal low speed RC oscillator LIRC Note This bit is write protected Refer to the SYS_REGL...

Page 130: ...00_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 ADCDIV 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved HCLKDIV Bits Description 31 24 Reserved Reserved 23 16 ADCDIV ADC Clock Divide Number From ADC Clock Source ADC clock frequency ADC clock source frequency ADCDIV 1 15 4 Reserved Reserved 3 0 HCLKDIV HCLK Clock Divide Number From HCLK Clock Source HCLK clock frequency HCLK...

Page 131: ... clock source If switch target clock is stable this bit will be set to 0 If switch target clock is not stable this bit will be set to 1 0 Clock switching success 1 Clock switching failure Note Write 1 to clear the bit to 0 6 5 Reserved Reserved 4 HIRCSTB HIRC Clock Source Stable Flag Read Only 0 48 MHz internal high speed RC oscillator HIRC clock is not stable or disabled 1 48 MHz internal high sp...

Page 132: ...0 Reserved DIV1EN CLKOEN FREQSEL Bits Description 31 6 Reserved Reserved 5 DIV1EN Clock Output Divide One Enable Bit 0 Clock Output will output clock with source frequency divided by FREQSEL 1 Clock Output will output clock with source frequency 4 CLKOEN Clock Output Enable Bit 0 Clock Output function Disabled 1 Clock Output function Enabled 3 0 FREQSEL Clock Output Frequency Selection The formula...

Page 133: ...ser in Config1 The Data Flash size is defined by user depending on the application request Security program memory SPROM provides user to protect any program code within SPROM 6 4 2 Features Running up to 48 MHz with one wait state and 24 MHz without wait state for discontinuous address read access 29 5 Kbytes application program memory APROM 2 Kbytes in system programming ISP loader program memor...

Page 134: ...L REFERENCE MANUAL AHB Slave Interface ISP Controller Flash Operation Control Power On Initialization Data Out Control Config Map AHB Bus DFBADR Cortex M0 AHB Lite interface Debug Access Port Serial wire debug interface Figure 6 4 1 Flash Memory Control Block Diagram ...

Page 135: ...lection Brown out voltage level Data Flash base address etc User configuration works like a fuse for power on setting and loaded from Flash memory to its corresponding control register during chip powered on In the NuMicro Family the Flash memory organization is different to system memory map Flash memory organization is used when user using ISP command to read program or erase Flash memory System...

Page 136: ...28_0000 0x0028_01FF Figure 6 4 2 Flash Memory Organization 6 4 4 2 Data Flash The Mini57 series provides Data Flash for user to store data which is read write thru ISP registers The erase unit is 512 bytes When a word will be changed all 128 words need to be copied to another page or SRAM in advance The Data Flash base address is defined by DFBA if DFEN bit in Config0 is enabled For example for 4K...

Page 137: ...m memory for user to store instruction of security It is read write through ISP procedure and ICE and this memory cannot be erased by whole chip erase command but page erase command The last byte of SPROM memory is used to identify the code is secured or non secured Please refer to Table 6 4 4 which shows that security program memory only allows CPU performs instruction fetch and page erase operat...

Page 138: ...Secured code ICE Debug ISP IAP CPU Data CPU Instruction Whole chip erase Page erase Program Read 00h 00h 00h CPU Instruction SPROM0 1 2 0x200000 0x2001FF 0x240000 0x2401FF 0x280000 0x2801FF ISP IAP ICP Writer ICE Lock unLock Lock unLock whole chip erase page erase program read instruction read data 00h 00h ...

Page 139: ... ROM SPROM0 1 0 5KB Security Protection ROM SPROM0 1 0 5KB others Security Protection ROM SPROM0 1 0 5KB Security Protection ROM SPROM0 1 0 5KB SPROM Security Mode SPROM Debug Mode SPROM Non security Mode 0x0020_0000 0x0020_01FF Reserved Security Protection ROM 0 SPROM0 0 5KB 0x0028_0000 0x0028_01FF Security Protection ROM 2 SPROM1 0 5KB Reserved Figure 6 4 4 SPROM Security Mode 6 4 4 4 User Confi...

Page 140: ...Selection 00 Pull low Resistor enabled 01 Pull high Resistor enabled 1x Pull high low Resistor disabled GPA4 set as this state mode after power on 23 22 GPA3RINI POWER oN Pull Resistor Initial State Selection 00 Pull low Resistor enabled 01 Pull high Resistor enabled 1x Pull high low Resistor disabled GPA3 set as this state mode after power on 21 20 GPA2RINI POWER oN Pull Resistor Initial State Se...

Page 141: ...d 7 6 CBS Chip Boot Selection 00 LDROM with IAP function 01 LDROM without IAP function 10 APROM with IAP function 11 APROM without IAP function For the Mini57 series user can set CBS 0 0 to support IAP function When CBS 0 0 the LDROM is mapping to address 0x100000 and APROM is mapping to address 0x0 User could access them by their address without boot switching In other words if IAP function is su...

Page 142: ...475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Config0 Address 0x0030_0000 Bits Description 0 DFEN Data Flash Enabled 0 Data Flash Enabled 1 Data Flash Disabled Note The reserved bits of user configuration should be kept as 1 ...

Page 143: ...5 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DFBA 7 6 5 4 3 2 1 0 DFBA Config1 Address 0x0030_0004 Bits Description 31 14 Reserved Reserved 13 0 DFBA Data Flash Base Address The Data Flash base address is defined by user Since on chip Flash erase unit is 512 bytes it is mandatory to keep bit 8 0 as 0 ...

Page 144: ...0 31 7 Figure 6 4 5 Boot Select BS for Power on Action CBS 1 0 Boot Selection 00 LDROM with IAP function Chip booting from LDROM program executing range including SPROM LDROM and APROM except APROM s first page LDROM address is mapping to 0x0010_0000 0x0010_07FF and the first 512 bytes of LDROM is mapping to the address 0x0000_0000 0x0000_01FF at the same time Both APROM and LDROM are programmable...

Page 145: ...ion and Supports Function 29 5KB APROM CBS 1 0 10 LDROM 2KB APROM CBS 1 0 00 LDROM 2KB 0x0010_0000 0x0010_07FF LDROM page0 0x0000_0000 0x0000_01FF 0x0000_0200 Data Flash 0x0000_0000 LDROM 2KB 29 5KB APROM DFBADR 0x0000_0000 0x0000_07FF CBS 1 0 11 CBS 1 0 01 APROM page0 SPROM0 0 5KB SPROM0 0 5KB 0x0020_0000 0x0020_01FF SPROM0 0 5KB SPROM0 0 5KB 0x0020_0000 0x0020_01FF SPROM1 0 5KB SPROM1 0 5KB 0x00...

Page 146: ...er cannot access the first page of APROM because the first page of executable code range becomes the mirror of the first page of LDROM as set by default Meanwhile the address space of 2 KB LDROM is mapped to 0x0010_0000 0x0010_07FF Please refer to Figure 6 4 7 for the address map while IAP is activating APROM LDROM 2K 0x0000_0000 0x0010_0000 0x0010_07FF Reserved CBS 10 b APROM LDROM 2K 0x0000_0000...

Page 147: ... UART along with the ISP loader in LDROM General speaking PC transfers the new APROM code through serial port Then ISP loader receives it and re programs into APROM through ISP commands ISP Registers Control Procedure The Mini57 series supports booting from APROM or LDROM initially defined by user configuration The change of user configuration needs to reboot system to make it take effect If user ...

Page 148: ...cording to FMC_ISPCMD Finally set ISPGO bit of FMC_ISPTRG control register to perform the relative ISP register function The ISPGO bit is self cleared when ISP register function has been done To make sure ISP register function has been finished before CPU goes ahead ISP instruction is used right after ISPGO setting Several error conditions are checked after ISP register function is completed If an...

Page 149: ...12 bytes page alignment Don t care SPROM Page Erase 0x22 Valid address of Flash memory origination It must be 512 bytes page alignment 0x0055AA03 FLASH Program 0x21 Valid address of Flash memory origination Programming Data FLASH Read 0x00 Valid address of Flash memory origination Return Data Read Unique ID 0x04 0x0000_0000 Unique ID Word 0 0x0000_0004 Unique ID Word 1 0x0000_0008 Unique ID Word 2...

Page 150: ...0000 FMC_ISPADDR FMC_BA 0x04 R W ISP Address Register 0x0000_0000 FMC_ISPDAT FMC_BA 0x08 R W ISP Data Register 0x0000_0000 FMC_ISPCMD FMC_BA 0x0C R W ISP Command Register 0x0000_0000 FMC_ISPTRG FMC_BA 0x10 R W ISP Trigger Register 0x0000_0000 FMC_DFBA FMC_BA 0x14 R Data Flash Start Address 0x0000_3800 FMC_ISPSTS FMC_BA 0x40 R W ISP Status Register 0xXXXX_XXXX FMC_CRCSEED FMC_BA 0x50 R W ISP CRC Se...

Page 151: ...3 SPROM writes to itself if SPUEN is set to 0 4 CONFIG is erased programmed if CFGUEN is set to 0 5 Destination address is illegal such as over an available range Note Write 1 to clear this bit to 0 5 LDUEN LDROM Update Enable Bit Write Protect 0 LDROM cannot be updated 1 LDROM can be updated when the MCU runs in APROM 4 CFGUEN CONFIG Update Enable Bit Write Protect Writing this bit to 1 enables s...

Page 152: ...is bit also functions as chip booting status flag which can be used to check where chip booted from This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset CPURF is 1 or system reset SYSRF is happened 0 Boot from APROM 1 Boot from LDROM 0 ISPEN ISP Enable Bit Write Protect Set this bit to enable ISP function 0 ISP function Disabled 1 ISP functio...

Page 153: ...Description Reset Value FMC_ISPADD R FMC_BA 0x04 R W ISP Address Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPADR 23 22 21 20 19 18 17 16 ISPADR 15 14 13 12 11 10 9 8 ISPADR 7 6 5 4 3 2 1 0 ISPADR Bits Description 31 0 ISPADR ISP Address The Mini57 series supports word program only ISPADR 1 0 must be kept 00 for ISP operation ...

Page 154: ...ription Reset Value FMC_ISPDAT FMC_BA 0x08 R W ISP Data Register 0x0000_0000 31 30 29 28 27 26 25 24 ISPDAT 23 22 21 20 19 18 17 16 ISPDAT 15 14 13 12 11 10 9 8 ISPDAT 7 6 5 4 3 2 1 0 ISPDAT Bits Description 31 0 ISPDAT ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation ...

Page 155: ...30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CMD Bits Description 31 6 Reserved Reserved 5 0 CMD ISP Command ISP commands are shown below 0x00 Read 0x04 Read Unique ID 0x0B Read Company ID 0xDA 0x0D Read CRC32 Checksum Result After Calculating 0x21 Program 0x22 Page Erase 0x2D Run Memory CRC32 Checksum Calculation 0x2E Set V...

Page 156: ... Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ISPGO Bits Description 31 1 Reserved Reserved 0 ISPGO ISP Start Trigger Write Protect Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished 0 ISP operation is finished 1 ISP operation is p...

Page 157: ... 2 1 0 DFBA Bits Description 31 0 DFBA Data Flash Base Address This register indicates Data Flash start address It is a read only register The Data Flash start address is defined by user Since on chip Flash erase unit is 512 bytes it is mandatory to keep bit 8 0 as 0 Example Data Flash 4KB DFEN 0 2KB DFEN 0 1KB DFEN 0 0KB DFEN 1 17 5K Flash DFBA 0x0000_3600 DFBA 0x0000_3E00 DFBA 0x0000_4200 DFEN 1...

Page 158: ...are inactive 001 SPROM0 secured code is active 010 SPROM1 secured code is active 100 SPROM2 secured code is active 111 SPROM0 1 2 Secured code are active 28 21 Reserved Reserved 20 9 VECMAP Vector Page Mapping Address Read Only The current Flash address space 0x0000_0000 0x0000_01FF is mapping to address VECMAP 11 0 9 h000 VECMAP 11 0 9 h1FF 8 7 Reserved Reserved 6 ISPFF ISP Fail Flag Write Protec...

Page 159: ...NCE MANUAL 0 ISPBUSY ISP Start Trigger Read Only Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished 0 ISP operation is finished 1 ISP operation is progressed Note This bit is the same with FMC_ISPTRG bit 0 ...

Page 160: ...0x50 R W ISP CRC Seed Register 0xFFFF_FFFF 31 30 29 28 27 26 25 24 CRCSEED 23 22 21 20 19 18 17 16 CRCSEED 15 14 13 12 11 10 9 8 CRCSEED 7 6 5 4 3 2 1 0 CRCSEED Bits Description 31 0 CRCSEED CRC Seed Data This register was provided to be the initial value for CRC operation Write data to this register before ISP CRC operation Read data from this register after ISP CRC read operation ...

Page 161: ...egister Offset R W Description Reset Value FMC_CRCCV FMC_BA 0x54 R ISP CRC Current Value Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 CRCCV 23 22 21 20 19 18 17 16 CRCCV 15 14 13 12 11 10 9 8 CRCCV 7 6 5 4 3 2 1 0 CRCCV Bits Description 31 0 CRCCV CRC Current Value This register provided current value of CRC durning calculation ...

Page 162: ...f each of I O pins can be configured by software individually as Input Push pull output Open drain output or Quasi bidirectional mode After the chip is reset the I O mode of all pins are depending on CIOIN CONFIG0 10 Each I O pin has a very weakly individual pull up resistor which is about 110 k 300 k for VDD is from 5 0 V to 2 5 V PAD PIN n Px_PIN PULLSEL 0 Px_PUEN PULLSEL 1 Px_PUEN MODE n Px_MOD...

Page 163: ...ts the pull up and pull low resistor enabled in four I O modes GPIOB to GPIOD internal pull up resistor enabled only in Quasi bidirectional I O mode Enabling the pin interrupt function will also enable the wake up function 6 5 3 Block Diagram AHB Bus PA 5 0 PA 5 0 Control Register PB 4 0 Control Register PC 4 0 Control Register PD 6 1 Control Register De bounce Control Register Control Registers I...

Page 164: ... sink current capability The bit value in the corresponding DOUT Px_DOUT n is driven on the pin Port Pin Port Pin N N P P VDD VDD Port Latch Data Port Latch Data Input Data Input Data Figure 6 5 3 Push Pull Output 6 5 5 3 Open drain Mode Set MODEn Px_MODE 2n 1 2n to 10 as the Px n pin is in Open drain mode and the digital output function of I O pin supports only sink current capability an external...

Page 165: ...51 and most of its derivatives If the bit value in the corresponding DOUT Px_DOUT n bit is 0 the pin drive a low output on the pin If the bit value in the corresponding DOUT Px_DOUT n bit is 1 the pin will check the pin value If pin value is high no action takes If pin state is low the pin will drive strong high with 2 clock cycles on the pin and then disable the strong output drive Meanwhile the ...

Page 166: ...he I O status before entering Idle Power down mode When using toggle GPIO to wake up system user must make sure the I O status before entering Idle Power down mode according to the relative wake up settings For example if configuring the wake up event occurred by I O rising edge high level trigger user must make sure the I O status of specified pin is at low level before entering Idle Power down m...

Page 167: ...hmitt Trigger Enable Register 0x0000_0000 PA_SLEWCTL GPIO_BA 0x028 R W PA High Slew Rate Control Register 0x0000_0000 PA_PLEN GPIO_BA 0x02C R W PA Pull Low Control Register 0x0000_0000 PA_PHEN GPIO_BA 0x030 R W PA Pull High Control Register 0x0000_003F PB_MODE GPIO_BA 0x040 R W PB I O Mode Control 0x0000_0XXX PB_DINOFF GPIO_BA 0x044 R W PB Digital Input Path Disable Control 0x0000_0000 PB_DOUT GPI...

Page 168: ...l Register 0x0000_0000 PC_PHEN GPIO_BA 0x0B0 R W PC Pull High Control Register 0x0000_001F PD_MODE GPIO_BA 0x0C0 R W PD I O Mode Control 0x0000_00XX PD_DINOFF GPIO_BA 0x0C4 R W PD Digital Input Path Disable Control 0x0000_0000 PD_DOUT GPIO_BA 0x0C8 R W PD Data Output Value 0x0000_007F PD_DATMSK GPIO_BA 0x0CC R W PD Data Output Write Mask 0x0000_0000 PD_PIN GPIO_BA 0x0D0 R PD Pin Value 0x0000_00XX ...

Page 169: ... PBn_PDIO n 0 1 4 GPIO_BA 0x840 0x04 n R W GPIO PB n Pin Data Input Output Register 0x0000_000X PCn_PDIO n 0 1 4 GPIO_BA 0x880 0x04 n R W GPIO PC n Pin Data Input Output Register 0x0000_000X PDn_PDIO n 0 1 6 GPIO_BA 0x8C0 0x04 n R W GPIO PD n Pin Data Input Output Register 0x0000_000X ...

Page 170: ...6 MODE5 MODE4 7 6 5 4 3 2 1 0 MODE3 MODE2 MODE1 MODE0 Bits Description 31 16 Reserved Reserved 2n 1 2n n 0 1 7 MODEn Port A d I O Pin n Mode Control Determine each I O mode of Px n pins 00 Px n is in Input mode 01 Px n is in Push pull Output mode 10 Px n is in Open drain Output mode 11 Px n is in Quasi bidirectional mode Note1 The initial value of this field is defined by CIOINI CONFIG0 10 If CIOI...

Page 171: ...sable Control 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 DINOFFn 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 24 Reserved Reserved n 16 n 0 1 7 DINOFFn Port A d Pin n Digital Input Path Disable Bits Each of these bits is used to control if the digital input path of corresponding Px n pin is disabled If input is analog signal users can disabl...

Page 172: ... 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DOUTn Bits Description 31 8 Reserved Reserved n n 0 1 7 DOUTn Port A d Pin n Output Value Each of these bits controls the status of a Px n pin when the Px n is configured as Push pull output Open drain output or Quasi bidirectional mode 0 Px n will drive Low if the Px n pin is configured as Push pull output Open drain...

Page 173: ...14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DATMSKn Bits Description 31 8 Reserved Reserved n n 0 1 7 DATMSKn Port A d Pin n Data Output Write Mask These bits are used to protect the corresponding DOUT Px_DOUT n bit When the DATMSK Px_DATMSK n bit is set to 1 the corresponding DOUT Px_DOUT n bit is protected If the write signal is masked writing data to the protect bit is ignored 0 Corresponding D...

Page 174: ...GPIO_BA 0x0D0 R PD Pin Value 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PINn Bits Description 31 8 Reserved Reserved n n 0 1 7 PINn Port A d Pin n Pin Value Each bit of the register reflects the actual status of the respective Px n pin If the bit is 1 it indicates the corresponding pin status is high else the pin sta...

Page 175: ...iption 31 8 Reserved Reserved n n 0 1 7 DBENn Port A d Pin n Input Signal De bounce Enable Bits The DBEN n bit is used to enable the de bounce function for each corresponding bit If the input signal pulse width cannot be sampled by continuous two de bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt The de bounce clock source is controll...

Page 176: ...e or Level Detection Interrupt Trigger Type Control TYPE Px_INTTYPE n bit is used to control the triggered interrupt is by level trigger or by edge trigger If the interrupt is by edge trigger the trigger source can be controlled by de bounce If the interrupt is by level trigger the input source is sampled by one HCLK clock and generates the interrupt 0 Edge trigger interrupt 1 Level trigger interr...

Page 177: ... also enable the pin wake up function When setting the RHIEN Px_INTEN n 16 bit to 1 If the interrupt is level trigger TYPE Px_INTTYPE n bit is set to 1 the input Px n pin will generate the interrupt while this pin state is at high level If the interrupt is edge trigger TYPE Px_INTTYPE n bit is set to 0 the input Px n pin will generate the interrupt while this pin state changed from low to high 0 P...

Page 178: ...PE Px_INTTYPE n bit is set to 0 the input Px n pin will generate the interrupt while this pin state changed from high to low 0 Px n level low or high to low interrupt Disabled 1 Px n level low or high to low interrupt Enabled Note Max n 5 for port A Max n 4 for port B Max n 4 for port C Max n 6 for port D n 0 is reserved ...

Page 179: ... Source Flag 0x0000_00XX PD_INTSRC GPIO_BA 0x0E0 R W PD Interrupt Source Flag 0x0000_00XX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 INTSRCn Bits Description 31 8 Reserved Reserved n n 0 1 7 INTSRCn Port A d Pin n Interrupt Source Flag Write Operation 0 No action 1 Clear the corresponding pending interrupt Read Operation 0 No in...

Page 180: ...BA 0x0A4 R W PC Input Schmitt Trigger Enable Register 0x0000_0000 PD_SMTEN GPIO_BA 0x0E4 R W PD Input Schmitt Trigger Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 SMTENn Bits Description 31 8 Reserved Reserved n n 0 1 7 SMTENn Port A d Pin n Input Schmitt Trigger Enable Bits 0 Px n input schmitt trigger...

Page 181: ...PC_SLEWCTL GPIO_BA 0x0A8 R W PC High Slew Rate Control Register 0x0000_0000 PD_SLEWCTL GPIO_BA 0x0E8 R W PD High Slew Rate Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 HSRENn Bits Description 31 8 Reserved Reserved n n 0 1 7 HSRENn Port A d Pin n High Slew Rate Control 0 Px n output with basic slew rat...

Page 182: ...0000_0000 PD_PLEN GPIO_BA 0x0EC R W PD Pull Low Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PLENn Bits Description 31 8 Reserved Reserved n n 0 1 7 PLENn Port A d Pull low Resistor Control 0 Pull Low Resistor Disabled 1 Pull Low Resistor Enabled Note The initial value of PA_PLEN were defined by GPAn_R...

Page 183: ...0000_001F PD_PHEN GPIO_BA 0x0F0 R W PD Pull High Control Register 0x0000_007F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PHENn Bits Description 31 8 Reserved Reserved n n 0 1 7 PHENn Port A d Pull high Resistor Control 0 Pull High Resistor Enabled 1 Pull High Resistor Disabled Note The initial value of PA_PHEN were defined by GP...

Page 184: ...eserved ICLKON DBCLKSRC DBCLKSEL Bits Description 31 6 Reserved Reserved 5 ICLKON Interrupt Clock on Mode 0 Edge detection circuit is active only if I O pin corresponding RHIEN Px_INTEN n 16 FLIEN Px_INTEN n bit is set to 1 1 All I O pins edge detection circuit is always active after reset Note It is recommended to disable this bit to save system power if no special application concern 4 DBCLKSRC ...

Page 185: ...once per 16 clocks 0101 Sample interrupt input once per 32 clocks 0110 Sample interrupt input once per 64 clocks 0111 Sample interrupt input once per 128 clocks 1000 Sample interrupt input once per 256 clocks 1001 Sample interrupt input once per 2 256 clocks 1010 Sample interrupt input once per 4 256 clocks 1011 Sample interrupt input once per 8 256 clocks 1100 Sample interrupt input once per 16 2...

Page 186: ... Input Output Register 0x0000_000X 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PDIO Bits Description 31 1 Reserved Reserved 0 PDIO GPIO Px N Pin Data Input Output Writing this bit can control one GPIO pin output value 0 Corresponding GPIO pin set to low 1 Corresponding GPIO pin set to high Read this register to get GPIO ...

Page 187: ...h 24 bit up timer and one 8 bit pre scale counter Supports independent clock source for each channel TMR0_CLK TMR1_CLK Supports four timer counting modes one shot periodic toggle and continuous counting Time out period period of timer clock input 8 bit pre scale counter 1 24 bit CMPDAT Supports maximum counting cycle time 1 T MHz 2 8 2 24 T is the period of timer clock 24 bit up counter value is r...

Page 188: ...MERx_CMP 23 0 TIF TIMERx_INTSTS 0 Reset counter CNTDATEN TIMERx_CTL 16 Load CAPDAT TIMERx_CAP 23 0 00 01 10 CAPEDGE TIMERx_EXTCTL 2 1 CAPEN TIMERx_EXTCTL 3 CAPFUNCS TIMERx_EXTCTL 4 CAPIF TIMERx_EINT STS 0 CAPIEN TIMERx_EXTCTL 5 Load INTEN TIMERx_CTL 29 ACMPOx 0 1 Timer Interrupt TWKF TIMERx_INTSTS 1 Timer Wakeup WKEN TIMERx_CTL 23 Figure 6 6 1 Timer Controller Block Diagram 111 010 001 000 011 Leg...

Page 189: ...one shot periodic toggle output and continuous counting operation modes 6 6 5 3 One shot Mode If timer controller is configured at one shot OPMODE TIMERx_CTL 28 27 is 00 and CNTEN TIMERx_CTL 30 bit is set the timer counter starts up counting Once the CNT TIMERx_CNT 23 0 value reaches CMPDAT TIMERx_CMP 23 0 value the TIF TIMERx_INTSTS 0 flag will be set to 1 CNT TIMERx_CNT 23 0 value and CNTEN bit ...

Page 190: ... and CNT value will not goes back to 0 it continues to count 81 82 83 to 2 24 1 0 1 2 3 to 2 24 1 again and again Next if software programs CMPDAT value as 200 and clears TIF flag the TIF flag will set to 1 again when CNT value reaches to 200 At last software programs CMPDAT as 500 and clears TIF flag the TIF flag will set to 1 again when CNT value reaches to 500 In this mode the timer counting is...

Page 191: ...ACMPOx x 0 1 In this mode CAPMODE TIMERx_EXTCTL 8 and CAPFUNCS TIMERx_EXTCTL 4 should be as 0 for select ACMPOx x 0 1 transition is using to trigger capture function and the timer peripheral clock source should be set as HCLK This mode can select edge transition detection of ACMPOx x 0 1 by setting CAPEDGE TIMERx_EXTCTL 2 1 In Free Counting capture mode user does not consider what timer counting o...

Page 192: ...urred CAPIF TIMERx_EINTSTS 0 is set to 1 and the interrupt signal is generated then sent to NVIC to inform CPU if CAPIEN TIMERx_EXTCTL 5 is 1 Function CAPMODE TIMERx_EXTCT L 8 CAPFUNCS TIMERx_EXTCT L 4 CAPEDGE TIMERx_EXTCTL 2 1 Operation Description Free counting Capture Mode 0 0 00 A 1 to 0 transition on ACMPOx x 0 1 pin is detected CNT is captured to CAPDAT 0 0 01 A 0 to 1 transition on ACMPOx x...

Page 193: ...de Timer0 1 provide Continuous Capture mode to obtain timer counter value automatically when edges occurs on input capture signal When CCAPEN TIMER_CCAPCTL 0 set to high the Continuous Capture mode will be enabled CNTSEL TIMER_CCAPCTL 3 2 is 00 means timer0 counter value will be latched when edge of input capture signal changed CNTSEL is 1 means timer1 counter value will be latched After CCAPEN en...

Page 194: ...ECHNICAL REFERENCE MANUAL INV 2 to 1 Mux CAPCHSEL 24 bit TM0 TM1 Counter TIMER_CCAP0 TIMER_CCAP1 TIMER_CCAP2 TIMER_CCAP3 CCAPEN Latch timer counter CAPR1F CAPF1F CAPR2F CAPF2F CNTSEL PD 2 PC 2 Input Capture Signal 0 1 Figure 6 6 6 Continuous Capture Mode Block ...

Page 195: ...to 1 H W loads Timer0 1 s counter value into TIMER_CCAP1 register at the 1st falling edge and set CAPF1F to 1 H W loads Timer0 1 s counter value into TIMER_CCAP2 register at the 2nd rising edge and set CAPR2F to 1 H W clears CCAPEN bit Input Signal H W loads Timer0 1 s counter value into TIMER_CCAP3 register at the 2nd falling edge and set CAPF2F to 1 CCAPEN Figure 6 6 7 Continuous Capture Mode Be...

Page 196: ...ister 0x0000_0000 TIMER1_CTL TMR_BA 0x20 R W Timer1 Control and Status Register 0x0000_0005 TIMER1_CMP TMR_BA 0x24 R W Timer1 Compare Register 0x0000_0000 TIMER1_INTSTS TMR_BA 0x28 R W Timer1 Interrupt Status Register 0x0000_0000 TIMER1_CNT TMR_BA 0x2C R Timer1 Data Register 0x0000_0000 TIMER1_CAP TMR_BA 0x30 R Timer1 Capture Data Register 0x0000_0000 TIMER1_EXTCTL TMR_BA 0x34 R W Timer1 Extended ...

Page 197: ...le Bit 0 Stops Suspends counting 1 Starts counting Note1 In stop status and then set CNTEN to 1 will enable the 24 bit up counter to keep counting from the last stop counting value Note2 This bit is auto cleared by hardware in one shot mode TIMERx_CTL 28 27 00 when the timer interrupt flag TIF is generated 29 INTEN Interrupt Enable Bit 0 Timer Interrupt function Disabled 1 Timer Interrupt function...

Page 198: ...ption 0 External event counter mode Disabled 1 External event counter mode Enabled 23 WKEN Wake up Enable Bit When WKEN is set and the TIF or CAPIF is set the timer controller will generator a wake up trigger event to CPU 0 Wake up trigger event Disabled 1 Wake up trigger event Enabled 22 18 Reserved Reserved 17 CMPCTL TIMERx_CMP Mode Control 0 In One shot or Periodic mode when writing new CMPDAT ...

Page 199: ...AT is a 24 bit compared value register When the internal 24 bit up counter value is equal to CMPDAT value the TIF flag will set to 1 Time out period Period of Timer clock source 8 bit PSC 1 24 bit CMPDAT Note1 Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown state Note2 When Timer is operating at Continuous Counting mode the 24 bit up counter will keep counting continuously...

Page 200: ...d 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TWKF TIF Bits Description 31 2 Reserved Reserved 1 TWKF Timer Wake up Flag This bit indicates the interrupt wake up flag status of Timer 0 Timer does not cause chip wake up 1 Chip wake up from Idle or Power down mode if Timer time out interrupt signal generated Note This bit is cleared by writing 1 to it 0 TIF Timer Interrupt Flag This bit ...

Page 201: ...x0C R Timer0 Data Register 0x0000_0000 TIMER1_CNT TMR_BA 0x2C R Timer1 Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 24 Reserved Reserved 23 0 CNT Timer Data Register If CNTDATEN is set to 1 CNT register value will be updated continuously to monitor 24 bit up counter value ...

Page 202: ...0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAPDAT 15 14 13 12 11 10 9 8 CAPDAT 7 6 5 4 3 2 1 0 CAPDAT Bits Description 31 24 Reserved Reserved 23 0 CAPDAT Timer Capture Data Register When CAPEN TIMERx_EXTCTL 3 bit is set CAPFUNCS TIMERx_EXTCTL 4 bit is 0 and a transition on ACMPOx matched the CAPEDGE TIMERx_EXTCTL 2 1 setting CAPIF TIMERx_EINTSTS 0 will set to 1 and the c...

Page 203: ...nter Input Pin De bounce Enable Bit 0 TMx x 0 1 pin de bounce Disabled 1 TMx x 0 1 pin de bounce Enabled If this bit is enabled the edge detection of TMx x 0 1 pin is detected with de bounce circuit 6 Reserved Reserved 5 CAPIEN Timer Capture Interrupt Enable Bit 0 Timer Capture Interrupt Disabled 1 Timer Capture Interrupt Enabled Note CAPIEN is used to enable timer capture interrupt If CAPIEN enab...

Page 204: ...e Function Enabled 2 1 CAPEDGE Timer Capture Pin Edge Detection 00 A falling edge on ACMPOx will be detected 01 A rising edge on ACMPOx will be detected 10 Either rising or falling edge on ACMPOx will be detected 11 Reserved 0 CNTPHASE Timer External Count Pin Phase Detect Selection This bit indicates the detection phase of TMx x 0 1 pin 0 A falling edge of TMx x 0 1 pin will be counted 1 A rising...

Page 205: ... 4 3 2 1 0 Reserved CAPIF Bits Description 31 1 Reserved Reserved 0 CAPIF Timer Capture Interrupt Flag This bit indicates the timer external capture interrupt flag status 0 Timer Cpautre interrupt did not occur 1 Timer Capture interrupt occurred Note1 This bit is cleared by writing 1 to it Note2 When CAPEN TIMERx_EXTCTL 3 bit is set CAPFUNCS TIMERx_EXTCTL 4 bit is 0 and a transition on ACMPOx matc...

Page 206: ...dege1 and Rising Edge 2 interrupt Enabled 11 Capture Rising Edge 1 Falling dege1 Rising Edge 2 and Falling Edge 2 interrupt Enabled 15 12 Reserved Reserved 11 CAPF2F Capture Falling Edge 2 Flag Second falling edge already captured this bit will be set to 1 0 None 1 CAPDAT TIMER_CCAP3 23 0 data is ready for read Note This bit is cleared by hardware automatically when writing 1 to this bit 10 CAPR2F...

Page 207: ... Channel Selection Select the channel to be the continuous capture event 0 PD 2 1 PC 2 3 2 CNTSEL Capture Timer Selection Select the timer to continuous capture the input signal 00 TIMER0 01 TIMER1 10 SysTick 11 Reserved 1 INV Input Signal Inverse Invert the input signal which be captured 0 None 1 Inverse 0 CCAPEN Continuous Capture Enable Bit This bit is to be enabled the continuous capture funct...

Page 208: ...inuous Capture Data Register 2 0x0000_0000 TIMER_CCAP3 TMR_BA 0x50 R Timer Continuous Capture Data Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAPDAT 15 14 13 12 11 10 9 8 CAPDAT 7 6 5 4 3 2 1 0 CAPDAT Bits Description 31 24 Reserved Reserved 23 0 CAPDAT Timer Continuous Capture Data Register TIMER_CCAP0 store the timer count value of first rising edge TIMER_CCA...

Page 209: ...end of input ports Edge detector with three options Rising edge detection Falling edge detection Both edge detection Supports ADC compare output and ACMP output as input sources Captured events reset and or reload capture counter Supports compare match function Supports interrupt function 6 7 3 Block Diagram Noise Filter IC1EN Input Capture Control Unit ECAP_CNT ECAP_CNTCMP ECAP_HLD0 ECAP_HLD1 ECA...

Page 210: ...pare output ADC_ECAP also can be internally routed to the capture inputs by setting the register ECAP_CTL0 CAPSEL0 CAPSEL 2 6 7 4 Input Noise Filter Figure 6 7 3 shows the architecture of Noise Filter with four sampling rate options NFCLKS ECAP_CTL0 1 0 Noise Filter CLK ECAP_CLK 00 11 10 01 ECAP_CLK 2 ECAP_CLK 4 ECAP_CLK 16 Figure 6 7 3 Noise Filter Sampling Clock Selection If enabled the capture ...

Page 211: ...h CPTST and the clock source of the clock divider which can be set by CAPDIV 2 0 to divide clock by 1 4 16 32 64 96 112 and 128 is programmable by setting CNTSRC 1 0 to be from system clock source ECAP_CLK or input channel CAP0 CAP2 In reload mode ECAP_CNTCMP serves as a reload register while in compare mode ECAP_CNTCMP serves as a compare register The Input Capture Timer Counter Enable bit CAPEN ...

Page 212: ... CNTSRC CAP1 CAP2 CAPCMPIEN 0 1 1 1 1 0 0 0 CAP1 CAP0 ECAP_CLK CAP2 CAPTF0 ECAP_HLD1 CAPEDG1 ECAP_HLD2 CAPEDG2 CAP0 CAPPHGEN CAP0_PCHG CAP1 CAP1_PCHG CAP2 CAP2_PCHG Figure 6 7 5 Enhanced Input Capture Timer Counter Functions Block 6 7 5 2 Compare Mode The compare function is enabled by setting the CMPEN ECAP_CTL0 28 bit to 1 and ECAP_CNTCMP will serve as a compare register As ECAP_CNT counting up ...

Page 213: ...uted 6 7 6 Input Capture Timer Counter Interrupt Architecture Figure 6 7 6 demonstrates the architecture of Input Capture Timer Counter interrupt module There are 5 interrupt sources OVF_INT CMP_INT CAPTF0_INT CAPTF2_INT which are logical OR together in a input capture unit and each one has an interrupt flag CAPOVF CAPCMPF CAPTF0 CAPTF2 which can trigger Interrupt ECAP_INT as well as an the enable...

Page 214: ...P_BA 0x04 R W Input Capture Counter Hold Register 0 0x0000_0000 ECAP_HLD1 ECAP_BA 0x08 R W Input Capture Counter Hold Register 1 0x0000_0000 ECAP_HLD2 ECAP_BA 0x0C R W Input Capture Counter Hold Register 2 0x0000_0000 ECAP_CNTCMP ECAP_BA 0x10 R W Input Capture Counter Compare Register 0x0000_0000 ECAP_CTL0 ECAP_BA 0x14 R W Input Capture Control Register 0 0x0000_0000 ECAP_CTL1 ECAP_BA 0x18 R W Inp...

Page 215: ...set Value ECAP_CNT ECAP_BA 0x00 R W Input Capture Counter 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 24 Reserved Reserved 23 0 CNT Input Capture Timer Counter The input Capture Timer Counter is a 24 bit up counting counter The clock source for the counter is from thme clock divider ...

Page 216: ... ECAP_BA 0x0C R W Input Capture Counter Hold Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 HOLD 15 14 13 12 11 10 9 8 HOLD 7 6 5 4 3 2 1 0 HOLD Bits Description 31 24 Reserved Reserved 23 0 HOLD Input Capture Counter Hold Register When an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding re...

Page 217: ... 25 24 Reserved 23 22 21 20 19 18 17 16 CNTCMP 15 14 13 12 11 10 9 8 CNTCMP 7 6 5 4 3 2 1 0 CNTCMP Bits Description 31 24 Reserved Reserved 23 0 CNTCMP Input Capture Counter Compare Register If the compare function is enabled CMPEN 1 t this register ECAP_CNTCMP is used to compare with the capture counter ECAP_CNT If the reload control is enabled RLDEN 1 an overflow event or capture events will tri...

Page 218: ...N Input Capture Timer Counter Enable Bit 0 Input Capture function Disabled 1 Input Capture function Enabled 28 CMPEN The Compare Function Enable Bit The compare function in input capture timer counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set 0 Compare function Disabled 1 Compare function Ena...

Page 219: ...nterrupt 1 Enabling flag CAPOVF can trigger Input Capture interrupt 19 Reserved Reserved 18 CAPTF2IEN Enable Input Capture Channel 2 Interrupt 0 Disabling flag CAPTF2 can trigger Input Capture interrupt 1 Enabling flag CAPTF2 can trigger Input Capture interrupt 17 CAPTF1IEN Enable Input Capture Channel 1 Interrupt 0 Disabling flag CAPTF1 can trigger Input Capture interrupt 1 Enabling flag CAPTF1 c...

Page 220: ...apture Unit Disabled 1 IC2 input to Input Capture Unit Enabled 5 IC1EN Enable Port Pin IC1 Input to Input Capture Unit 0 IC1 input to Input Capture Unit Disabled 1 IC1 input to Input Capture Unit Enabled 4 IC0EN Enable Port Pin IC0 Input to Input Capture Unit 0 IC0 input to Input Capture Unit Disabled 1 IC0 input to Input Capture Unit Enabled 3 CAPNFDIS Disable Input Capture Noise Filter 0 Noise f...

Page 221: ...d CAPDIV Reserved CPRLDS 7 6 5 4 3 2 1 0 Reserved CAPEDG2 CAPEDG1 CAPEDG0 Bits Description 31 18 Reserved Reserved 17 16 CNTSRC Capture Timer Counter Clock Source Selection Select the capture timer counter clock source 00 ECAP_CLK Default 01 CAP0 10 CAP1 11 CAP2 15 Reserved Reserved 14 12 CAPDIV Capture Timer Clock Divide Selection The capture timer clock has a pre divider with four divided option...

Page 222: ...tion Input capture can detect falling edge change only rising edge change only or one of both edge change 00 Detect rising edge 01 Detect falling edge 1x Detect either rising or falling edge 3 2 CAPEDG1 Channel 1 Captured Edge Selection Input capture can detect falling edge change only rising edge change only or one of both edge change 00 Detect rising edge 01 Detect falling edge 1x Detect either ...

Page 223: ... status The bit is read only and write is ignored 8 CAP0 Input Capture Pin 0 Status Read Only Input capture pin 0 ECAP_P0 status The bit is read only and write is ignored 7 6 Reserved Reserved 5 CAPOVF Input Capture Counter Overflow Flag Flag is set by hardware when counter ECAP_CNT overflows from 0x00FF_FFFF to zero 0 No overflow event has occurred since last clear 1 Overflow event s has have occ...

Page 224: ...annel 1 Captured Flag When the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high 0 No valid edge change has been detected at CAP1 input since last clear 1 At least a valid edge change has been detected at CAP1 input since last clear Note This bit is only cleared by writing 1 to it 0 CAPTF0 Input Capture Channel 0 Captured Flag When the input capture ...

Page 225: ...rator are implemented with double buffer When user writes data to counter comparator buffer registers the updated value will be loaded into the 16 bit counter comparator at the end of current period The double buffering feature avoids glitch at PWM outputs Besides PWM Motor controlling also need Timer ACMP and ADC to work together To control motor more precisely some registers are provided to conf...

Page 226: ... Period Control PERIOD EPWM_PERIOD 15 0 HCLK PWM Clock Divider 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 EPWM_CH01 Function EPWM_CH23 Function EPWM_CH45 Function BRAKE Function BRAKE PC 2 ACMP0_PBRK ACMP1_PBRK ADC_PBRK to ADC see ADCnTRGSOR EPWM Output Waveform EPWM Phase Change MASK Control EPWM Interrupt Function EPWM_INT BRK1IF signal PIF CIF signal CMPUIF4 5 CMPDIF4 5 signal CMPUIF2 3 CMPDIF2 3...

Page 227: ...WM_CH0 GPIO Output Mode 1 0 3 0 PA0MFP SYS_GPA_MFP 3 0 PA 0 GPIO bit MODE0 PA_MODE 1 0 to ADC EPWM_CH0 signal DTCNT01 EPWM_CTL 24 CAP0_PCHG CAP1_PCHG CAP2_PCHG from ECAP EPWM_CH1 signal Figure 6 8 3 EPWM Generator 0 1 Architecture Diagram CLKDIV EPWM_CLKDIV 3 0 0000 0001 1 1 2 1 4 1 8 1 16 0010 0011 0100 EPWM Counter0 Logic EPWM Counter1 Logic DTCNT23 EPWM_DTCTL 15 8 HCLK PWM clock Generator EPWM_...

Page 228: ...P2_PCHG to ADC from ECAP EPWM_CH4 signal EPWM_CH5 signal Figure 6 8 5 EPWM Generator 4 5 Architecture Diagram 6 8 4 Basic Configuration The PWM pin functions are configured in SYS_GPA_MFP registers The PWM clock can be enabled in CLK_APBCLK 20 The PWM clock source is HCLK 6 8 5 Functional Description 6 8 5 1 PWM Timer Operation This device supports two operation modes Edge aligned and Center align...

Page 229: ...nd operation flow PERIOD new CMPDATn old PERIOD old CMPDATn new New Duty Cycle PWM period New PWM period New CMPDATn is written New PERIOD is written If 16 bit down counter underflow 1 Update new duty cycle register CMPDATn if CNTMODE 1 2 Update new period cycle register PERIOD if CNTMODE 1 PWMn generator ouput 16 bit PWM counter Figure 6 8 6 EPWM Edge aligned Type PERIOD 7FF CMPDATn 3FF PWMn gene...

Page 230: ...ERIOD 99 Period PERIOD 1 99 1 100 99 98 97 2 1 0 period Edge Aligned mode Period PERIOD 1 clock cycle Duty ratio CMPDAT PERIOD 1 CMRDAT PERIOD always High CMRDAT 0 always Low 3 CMRDAT 1 CMRDAT 0 CMRDAT 2 CMRDAT 98 CMRDAT 97 CMRDAT 3 CMRDAT 99 CMRDAT 100 Figure 6 8 7 EPWM Edge aligned Mode Operation Timing ...

Page 231: ... Page 231 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL PWM_PERIOD PWM_CMPDATn PWM period PWM generator ouput 16 bit PWM counter PIEN PIF CMPDIENn CMPDIFn n 0 5 Figure 6 8 8 EPWM Edge aligned Interrupt Diagram ...

Page 232: ...and PERIOD to working registers Down counting start from PERIOD PWMn output 0 if counter CMPDATn 1 if counter CMPDATn 0 if counter 0 EPWM_CHn output Low Counter down counting Counter CMPDATn EPWM_CHn output toggle CMPDIFn flag set Counter continue down counting Counter 0 EPWM_CHn output toggle PIF flag set CNTMODE 1 H w will load in new PERIOD CMPDATn value to working registers No No No Yes Yes Ye...

Page 233: ...divider PERIOD 1 Period PERIOD 1 unit Duty ratio CMPDAT PERIOD 1 CMPDAT PERIOD PWM output is always high CMPDAT PERIOD PWM output high duty CMPDAT unit CMPDAT 0 PWM always low Note 1 Unit one PWM clock cycle PWM Timer Comparator Output CMPDATn Update new CMPDATn Start Initialize PWM PWM Ouput PERIOD 1 CMPDATn PERIOD PERIOD CMPDATn Note n 0 5 Figure 6 8 10 EPWM Legend of Internal Comparator Output ...

Page 234: ...ter PERIOD new and duty cycle register CMPDATn new with CNTMODE 1 In Center aligned mode the EPWM has 4 types interrupt as Period interrupt PIF Up interrupt CMPUIF Central interrupt CIF and Down interrupt CMPDIF PWM frequency HCLK clock divider 2 PERIOD 1 Period 2 x PERIOD 1 unit Duty ratio 2 x CMPDAT PERIOD 1 CMPDAT PERIOD PWM output is always high CMPDAT PERIOD PWM output high duty 2 x CMPDAT un...

Page 235: ...PERIOD 1 2 99 1 200 99 98 97 2 1 0 0 1 2 97 98 99 central period CMRDAT 1 CMRDAT 0 Central Aligned mode Period 2 PERIOD 1 clock cycle Duty ratio 2 CMRDAT PERIOD 1 CMRDAT PERIOD always High CMRDAT 0 always Low 3 3 CMRDAT 2 CMRDAT 98 CMRDAT 97 CMRDAT 3 CMRDAT 99 CMRDAT 100 Figure 6 8 13 EPWM Center aligned Mode Operation Timing ...

Page 236: ...IF s w clear CIF PWM Period PWMn generator ouput s w clear s w clear s w clear s w clear Figure 6 8 14 EPWM Center aligned Waveform Output PWM_PERIODn PWM_CMPDATn PWM generator ouput 16 bit PWM counter PWM period CIEN CIF CMPUIENn CMPUIFn PIEN PIF CMPDIENn CMPDIFn n 0 5 Figure 6 8 15 EPWM Center aligned Interrupt Diagram ...

Page 237: ...counter CMPDATn 1 if counter CMPDATn EPWM_CHn output Low Counter down counting Counter CMPDATn Counter continue down counting Counter up counting No Yes Yes EPWM Counter change to Up Counting and start count from 0 CIF flag set EPWM_CHn output toggle CMPDIFn flag set Counter 0 No Yes Counter CMPDATn No Counter continue up counting PIF flag set EPWM_CHn output toggle CMPUIFn flag set Counter PERIOD...

Page 238: ... be the complement of EPWM_CH0 EPWM_CH3 will be the complement of EPWM_CH2 and EPWM_CH5 will be the complement of EPWM_CH4 6 8 5 5 Synchronized Mode Synchronized mode is enabled when MODE EPWM_CTL 29 28 10 In this mode there are three PWM channel duty cycle by setting EPWM_CH0 EPWM_CH2 and EPWM_CH4 The total six PWM outputs are grouped into output pairs of even and odd numbered outputs In synchron...

Page 239: ... EPWM_CH0 EPWM_CH1 which imply EPWM_CH4 EPWM_CH2 EPWM_CH0 EPWM_CH5 EPWM_CH3 EPWM_CH1 invert EPWM_CH0 if Complementary mode is enabled when MODE EPWM_CTL 29 28 01 Note For applications please do not use Group and Synchronous mode simultaneously because the Synchronous mode will be inactive 6 8 5 8 Asymmetric Mode Asymmetric mode only works under Center aligned type Asymmetric mode is enabled when A...

Page 240: ...n EPWM start run is set Figure 6 8 19 shows one shot mode status period CMRDAT PERIOD CMRDAT 0 CMRDAT PERIOD 0 PWM Start period Figure 6 8 19 EPWM One Shot Mode Architecture 6 8 5 10 Polarity Control Each PWM port from PWM0_CH0 to PWM0_CH5 has independent polarity control to configure the polarity of active state of PWM output By default the PWM output is active high Figure 6 8 20 shows the initia...

Page 241: ... to period interrupt flag CIF EPWM_INTSTS 18 PWM counter counts to central point of center aligned type interrupt flag CMPDIFn EPWM_INTSTS 29 24 PWM counter down counts to CMPn EPWM_CMPDATn 15 0 interrupt flag CMPUIFn EPWM_INTSTS 13 8 PWM counter up counts to CMPUn EPWM_CMPDATn 31 16 interrupt flag if operating in asymmetric type it up count to CMPUn PWM_CMPDATn 31 16 BRK0IF PWM_INTSTS 16 Brake0 i...

Page 242: ...IF3 EPWM_INTSTS 27 CMPDIEN3 EPWM_INTEN 27 CMPUIF2 EPWM_INTSTS 10 CMPUIEN2 EPWM_INTEN 10 CMPDIF2 EPWM_INTSTS 26 CMPDIEN2 EPWM_INTEN 26 PIF EPWM_INTSTS 0 PIEN EPWM_INTEN 0 CIF EPWM_INTSTS 18 CIEN EPWM_INTEN 18 1 0 IFAEN EPWM_IFA 0 EPWM_INT IFCNT Figure 6 8 21 EPWM Interrupt Architecture Note For the BRKnIF s interrupt architecture illustration see Figure 6 8 22 6 8 5 12 EPWM Brake This device suppor...

Page 243: ...nal The BRK1 block has resume function when BRK1 brake active it will resume by itself with 12 bits delay counter Since both brake conditions being asserted will automatically cause BRKnIF n 0 1 flag to be set the user program can poll these brake flag bits or enable EPWM s brake interrupt EPWM_INTEN to determine which condition will cause a brake to occur 6 8 5 13 EPWM Phase Change Function The p...

Page 244: ... on the PWM channel 3 phase load PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 Symbol of a typical 3 phase inverter n 0 5 0 2 4 1 3 5 MSKENn 0 2 4 1 3 5 MSKDATn 3 phase load PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 Symbol of a typical 3 phase inverter 0 2 4 1 3 5 PWMnME 0 2 4 1 3 5 PWMnMD n 0 5 Figure 6 8 23 EPWM 3 phase Motor Mask Diagram For example 1 Motor activating path is path 0 connects path 3 and path 0 is used as E...

Page 245: ...sed as EPWM2 and path 5 is ON short PWM channel 2 follow PWM generator PWM channels 0 1 3 5 are masked by MSKENn bits PWM channels 0 1 3 5 outputs are determined by state of MSKDATn bits Switch 0 Off MSKDAT0 0 Switch 1 Off MSKDAT1 0 Switch 2 On Off Control by EPWM2 EPWM2 frequency duty generator Switch 3 Off MSKDAT3 0 Switch 4 Off MSKDAT4 0 Switch 5 On MSKDAT5 1 Current path 2 5 PWM0MD PWM1MD PWM2...

Page 246: ... also direct check Hall sensor state to change motor phase When TRGSEL 011b EPWM_PHCHGNXT 22 20 trigger by next Hall state the Phase Change controller will check CAPn_PCHG n 0 2 status If matched HALLSTS EPWM_PHCHGNXT 18 16 setting value then EPWM output data can be copied to EPWM_PHCHG from EPWM_PHCHGNEXT and change status of MOTOR simultaneously ...

Page 247: ...M_CMPDAT3 EPWM_BA 0x30 R W EPWM Comparator Register 3 0x0000_0000 EPWM_CMPDAT4 EPWM_BA 0x34 R W EPWM Comparator Register 4 0x0000_0000 EPWM_CMPDAT5 EPWM_BA 0x38 R W EPWM Comparator Register 5 0x0000_0000 EPWM_CNT EPWM_BA 0x3C R EPWM Data Register 0x0000_0000 EPWM_INTEN EPWM_BA 0x54 R W EPWM Interrupt Enable Register 0x0000_0000 EPWM_INTSTS EPWM_BA 0x58 R W EPWM Interrupt Status Register 0x0000_000...

Page 248: ...it controls polarity active state of real PWM output 0 PWM output is active high 1 PWM output is active low 4 NEGPOLAR4 PWM4 Negative Polarity Control The register bit controls polarity active state of real PWM output 0 PWM output is active high 1 PWM output is active low 3 NEGPOLAR3 PWM3 Negative Polarity Control The register bit controls polarity active state of real PWM output 0 PWM output is a...

Page 249: ...75 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 0 NEGPOLAR0 PWM0 Negative Polarity Control The register bit controls polarity active state of real PWM output 0 PWM output is active high 1 PWM output is active low ...

Page 250: ...000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CLKDIV Bits Description 31 4 Reserved Reserved 3 0 CLKDIV EPWM Clock Divider 9 Step Divider Select clock input for PWM timer 0000 1 HCLK 2 0 0001 1 2 HCLK 2 1 0010 1 4 HCLK 2 2 0011 1 8 HCLK 2 3 0100 1 16 HCLK 2 4 0101 1 32 HCLK 2 5 0110 1 64 HCLK 2 6 0111 1 128 HCLK 2 7 10...

Page 251: ...signals timing of PWM0 PWM2 and PWM4 in the same phase which is controlled by PWM0 29 28 MODE PWM Operating Mode Selection 00 Independent mode 01 Complementary mode 10 Reserved 11 Reserved 27 CNTCLR Clear PWM Counter Control Bit 0 Do not clear PWM counter 1 16 bit PWM counter cleared to 0x000 Note It is automatically cleared by hardware 26 DTCNT45 Dead zone 4 Generator Enable Disable PWM4 and PWM5...

Page 252: ...er aligned type 19 18 Reserved Reserved 17 16 HCUPDT Half Cycle Update Enable for Center aligned Type 00 Update PERIOD CMP at pwm_counter PERIOD Period 01 Update PERIOD CMP at pwm_counter 0 10 Update PERIOD CMP at half cycle counter 0 PERIOD both update 11 Update PERIOD CMP at pwm_counter PERIOD Period 15 9 Reserved Reserved 8 CNTMODE PWM timer Auto reload One shot Mode 0 One shot mode 1 Auto relo...

Page 253: ...17 Page 253 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 0 CNTEN0 PWM timer 0 Enable Disable Start Run 0 Corresponding PWM timer running Stopped 1 Corresponding PWM timer start run Enabled ...

Page 254: ...nding on the selected PWM channel PWM frequency PWMxy_CLK HCLK clock divider EPWM_CLKDIV PWM Clock Cycle 1 PWM Freq Period PWM Clock Cycle PERIOD 1 Duty PWM Clock Cycle CMPn Duty ratio CMPn PERIOD 1 CMPn PERIOD PWM output is always high CMPn PERIOD PWM low width PERIODn CMPn unit PWM high width CMP unit CMPn 0 PWM always output low Center aligned mode where xy could be 01 23 45 depending on the se...

Page 255: ...PDAT3 EPWM_BA 0x30 R W EPWM Comparator Register 3 0x0000_0000 EPWM_CMPDAT4 EPWM_BA 0x34 R W EPWM Comparator Register 4 0x0000_0000 EPWM_CMPDAT5 EPWM_BA 0x38 R W EPWM Comparator Register 5 0x0000_0000 31 30 29 28 27 26 25 24 CMPU 23 22 21 20 19 18 17 16 CMPU 15 14 13 12 11 10 9 8 CMP 7 6 5 4 3 2 1 0 CMP Bits Description 31 16 CMPU PWM Comparator Register for UP Counter in Center aligned Asymmetric ...

Page 256: ...RIOD 1 unit Duty ratio CMP PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM output high duty CMP unit CMP 0 PWM always low Center aligned mode where xy could be 01 23 45 depending on the selected PWM channel Period 2 x PERIOD 1 unit Duty ratio 2 x CMP PERIOD CMP PERIOD PWM output is always high CMP PERIOD PWM output high duty 2 x CMP unit CMP 0 PWM always low Unit One PWM clock cycle N...

Page 257: ...R EPWM Data Register 0x0000_0000 31 30 29 28 27 26 25 24 CNTDIR Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 CNTDIR PWM Counter Up Down Direction 0 PWM counter is down counting 1 PWM counter is up counting 30 16 Reserved Reserved 15 0 CNT PWM Data User can monitor CNT to know the current value in 16 bit down counter ...

Page 258: ...isabled 1 Interrupt when EPWM_CH5 PWM DOWN counter reaches EPWM_CMPDAT5 Enabled 28 CMPDIEN4 PWM Channel 4 DOWN Interrupt Enable Bit DOWN for Edge aligned and Center aligned 0 Interrupt compare Disabled 1 interrupt when EPWM_CH4 PWM DOWN counter reaches EPWM_CMPDAT4 Enabled 27 CMPDIEN3 PWM Channel 3 DOWN Interrupt Enable Bit DOWN for Edge aligned and Center aligned 0 Interrupt compare Disabled 1 in...

Page 259: ... UP counter reaches EPWM_CMPDAT5 Enabled 12 CMPUIEN4 PWM Channel 4 UP Interrupt Enable Bit UP for Center aligned only 0 EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Disabled 1 EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4 interrupt Enabled 11 CMPUIEN3 PWM Channel 3 UP Interrupt Enable Bit UP for Center aligned only 0 EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3 interrupt Disabled 1 EPWM_C...

Page 260: ...ev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 7 1 Reserved Reserved 0 PIEN PWM Channel 0 Period Interrupt Enable Bit for Edge aligned and Center aligned 0 EPWM Period interrupt Disabled 1 EPWM Period interrupt Enabled ...

Page 261: ...g is set by hardware when a channel 4 PWM DOWN counter reaches EPWM_CMPDAT4 Software can write 1 to clear this bit 27 CMPDIF3 PWM Channel 3 DOWN Interrupt Flag Flag is set by hardware when a channel 3 PWM DOWN counter reaches EPWM_CMPDAT3 Software can write 1 to clear this bit 26 CMPDIF2 PWM Channel 2 DOWN Interrupt Flag Flag is set by hardware when a channel 2 PWM DOWN counter reaches EPWM_CMPDAT...

Page 262: ...er reaches PWM_CMPDAT4 Software can write 1 to clear this bit 11 CMPUIF3 PWM Channel 3 UP Interrupt Flag Flag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT3 Software can write 1 to clear this bit 10 CMPUIF2 PWM Channel 2 UP Interrupt Flag Flag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT2 Software can write 1 to clear this bit 9 CMPUIF1 PWM Channel 1...

Page 263: ...set R W Description Reset Value EPWM_RESD LY EPWM_BA 0x5C R W EPWM BRK Low Voltage Detect Resume Delay 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DELAY 7 6 5 4 3 2 1 0 DELAY Bits Description 31 12 Reserved Reserved 11 0 DELAY PWM BRK Low Voltage Detect Resume Delay 12 bits Down Counter ...

Page 264: ...KOD5 PWM Channel 5 Brake Output Selection 0 PWM output low when fault brake conditions asserted 1 PWM output high when fault brake conditions asserted 28 BKOD4 PWM Channel 4 Brake Output Selection 0 PWM output low when fault brake conditions asserted 1 PWM output high when fault brake conditions asserted 27 BKOD3 PWM Channel 3 Brake Output Selection 0 PWM output low when fault brake conditions ass...

Page 265: ... BRK1 Source From ACMP1 Enabled 10 BRK1A0EN BRK1 Source From ACMP0 Enable Bit 0 BRK1 Source From ACMP0 Disabled 1 BRK1 Source From ACMP0 Enabled 9 SWBRK Software Break 0 Software break and back to normal PWM function Disabled 1 Issue Software break Enabled 8 6 Reserved Reserved 5 BRK0PEN BRK0 Source From External Pin Enable Bit 0 BRK0 Source From External Pin Disabled 1 BRK0 Source From External P...

Page 266: ...zone Interval Register for Pair of Channel4 and Channel5 PWM4 and PWM5 Pair These 8 bits determine dead zone length The unit time of dead zone length is received from corresponding EPWM_CLKDIV bits 15 8 DTCNT23 Dead zone Interval Register for Pair of Channel2 and Channel3 PWM2 and PWM3 Pair These 8 bits determine dead zone length The unit time of dead zone length is received from corresponding EPW...

Page 267: ... Trigger Function Enable Bit 0 ACMP1 trigger PWM function Disabled 1 ACMP1 trigger PWM function Enabled 28 ACMP0TEN ACMP0 Trigger Function Enable Bit 0 ACMP0 trigger PWM function Disabled 1 ACMP0 trigger PWM function Enabled 27 26 A1POSSEL Alternative Comparator 1 Positive Input Selection Select the positive input source of ACMP1 00 Select ACMP1_P0 PC 0 as the input of ACMP1 01 Select ACMP1_P1 PC ...

Page 268: ...MSKEN5 Enable PWM5 Mask Function 0 PWM5 Mask Function Disabled 1 PWM5 Mask Function Enabled 12 MSKEN4 Enable PWM4 Mask Function 0 PWM4 Mask Function Disabled 1 PWM4 Mask Function Enabled 11 MSKEN3 Enable PWM3 Mask Function 0 PWM3 Mask Function Disabled 1 PWM3 Mask Function Enabled 10 MSKEN2 Enable PWM2 Mask Function 0 PWM2 Mask Function Disabled 1 PWM2 Mask Function Enabled 9 MSKEN1 Enable PWM1 Ma...

Page 269: ...iption 2 MSKDAT2 Enable PWM2 Mask Data 0 PWM2 state is masked with zero 1 PWM2 state is masked with one 1 MSKDAT1 Enable PWM1 Mask Data 0 PWM1 state is masked with zero 1 PWM1 state is masked with one 0 MSKDAT0 Enable PWM0 Mask Data 0 PWM0 state is masked with zero 1 PWM0 state is masked with one ...

Page 270: ...set Bit This bit will be load to bit ACMP1TEN in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW for detailed definition 28 ACMP0TEN ACMP0 Trigger Function Control Preset Bit This bit will be load to bit ACMP0TEN in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW for detailed definition 27 26 A1POSSEL Alternative Comparator 1 Positive Input Selecti...

Page 271: ...KEN5 in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW for detailed definition 12 MSKEN4 Enable PWM4 Mask Function Preset Bit This bit will be load to bit MSKEN4 in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW for detailed definition 11 MSKEN3 Enable PWM3 Mask Function Preset Bit This bit will be load to bit MSKEN3 in PHCHG_NOW when load trigge...

Page 272: ...on occurs Refer to register PHCHG_NOW for detailed definition 2 MSKDAT2 Enable PWM2 Mask Data Preset Bit This bit will be load to bit MSKDAT2 in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW for detailed definition 1 MSKDAT1 Enable PWM1 Mask Data Preset Bit This bit will be load to bit MSKDAT1 in PHCHG_NOW when load trigger condition occurs Refer to register PHCHG_NOW fo...

Page 273: ...2 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POSCTL1 POSCTL0 Bits Description 31 2 Reserved Reserved 1 POSCTL1 Positive Input Control for ACMP1 0 The input of ACMP1 is controlled by ACMP_CTL1 1 The input of ACMP1 is controlled by A1POSSEL in PHCHG_NOW register Note Register ACMP_CTL1 is describe in Comparator Controller chapter 0 POSCTL0 Positive Input Control for ACMP0 0 The input of ACMP0 is co...

Page 274: ...ion 31 16 Reserved Reserved 15 12 IFDAT Period Interrupt Down counter Data Register Read Only When IFAEN is set IFDAT will decrease when every PWM Interrupt flag is set and when IFDAT reaches 0 the PWM interrupt will occurred and IFCNT will reload to IFDAT 11 8 Reserved Reserved 7 4 IFCNT Period Interrupt Accumulation Counter Value Setting Register Write Only 16 step Down Counter value setting reg...

Page 275: ... to Figure 6 9 1 PWM Clock Source Control To prevent PWM driving output pin from glitches the 16 bit period down counter and 16 bit comparator are implemented with double buffer When user writes data to counter comparator buffer registers the updated value will be load into the 16 bit down counter comparator at the time down counter reaching zero The double buffering feature avoids glitch at PWM o...

Page 276: ...M_CMPDAT0 BPWM_CTL BPWM_PERIOD1 BPWM_CMPDAT1 BPWM_CTL BPWM_CNT1 BPWM_CNT0 PIEN0 BPWM_INTEN 0 DIEN0 BPWM_INTEN 8 PIEN1 BPWM_INTEN 1 DIEN1 BPWM_INTEN 9 PIF1 BPWM_INTSTS 1 DIF1 BPWM_INTSTS 9 POEN0 BPWM_POEN 0 POEN1 BPWM_POEN 1 CLKDIV0 BPWM_CLKDIV 2 0 CLKDIV1 BPWM_CLKDIV 6 4 Figure 6 9 2 PWM Architecture Diagram 6 9 4 PWM Timer Operation The PWM controller supports two operation types Edge aligned and...

Page 277: ...WM Timer Comparator is shown as Figure 6 9 3 Note that the corresponding GPIO pins must be configured as BPWM function when enable BPWM_POEN for the corresponding BPWM channel PWM frequency BPWM_CLK prescale 1 clock divider PERIOD 1 Duty ratio CMP 1 PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM low width PERIOD CMP unit 1 PWM high width CMP 1 unit CMP 0 PWM low width PERIOD unit PWM...

Page 278: ...al setting H W update value PIFx is set by H W PIFx is set by H W Note x 0 1 Figure 6 9 4 PWM Timer Operation Timing PERIOD 7FF CMP 3FF PIF s w clear PWMn generator ouput s w clear DIF s w clear s w clear PWM period PWM period Note n 0 1 BPWM_INTSTS 0 1 BPWM_INTSTS 8 9 BPWM_CMPDATn 15 0 BPWM_PERIODn 15 0 Figure 6 9 5 PWM Edge aligned Interrupt Generate Timing Waveform 6 9 4 2 Center aligned PWM up...

Page 279: ...ounter underflow if PINTTYPE BPWM_INTEN 16 0 i e at start end of each PWM cycle or at up counter matching with PERIOD if PINTTYPE BPWM_INTEN 16 1 i e at center point of PWM cycle PWM frequency BPWM_CLK prescale 1 clock divider 2 PERIOD 1 Duty ratio 2 x CMP 1 2 x PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM low width 2 x PERIOD CMP 1 unit 1 PWM high width 2 x CMP 1 unit CMP 0 PWM lo...

Page 280: ...mode before set CNTEN0 bit to 1 to enable PWM0 counter start running because the content of BPWM_PERIOD0 and BPWM_CMPDAT0 will be cleared to 0 to reset the PWM0 period and duty setting when PWM0 operating mode is changed As PWM0 operate in One shot mode BPWM_CMPDAT0 and BPWM_PERIOD0 should be written first and then set CNTEN0 bit to 1 to enable PWM0 counter start running After PWM0 counter down co...

Page 281: ...ion allows CMP written at any point in current cycle The loaded value will take effect from next cycle Modulate PWM controller ouput duty ratio PERIOD 150 Write CMP 100 Write CMP 50 Write CMP 0 1 PWM cycle 151 1 PWM cycle 151 1 PWM cycle 151 101 51 1 Figure 6 9 9 PWM Controller Output Duty Ratio 6 9 4 5 Dead Zone Generator The PWM controller is implemented with Dead zone generator They are built f...

Page 282: ...IEN1 DIEN1 BPWM_INT Figure 6 9 11 PWM Interrupt Architecture Diagram 6 9 4 7 PWM Timer Start Procedure The following procedure is recommended for starting a PWM drive 1 Set clock source divider select register BPWM_CLKDIV 2 Set prescaler BPWM_CLKPSC 3 Set inverter on off Dead zone generator on off Auto reload One shot mode and Stop PWM timer BPWM_CTL 4 Set comparator register BPWM_CMPDAT for setti...

Page 283: ... PERIOD PWM wave will be generated 6 9 4 9 PWM Timer Stop Procedure Method 1 Set 16 bit counter PERIOD as 0 and monitor CNT current value of 16 bit down counter When CNT reaches to 0 disable PWM Timer CNTENx in BPWM_CTL x 0 or 1 Recommended Method 2 Set 16 bit counter PERIOD as 0 When interrupt request happened disable PWM Timer CNTENx in BPWM_CTL x 0 or 1 Recommended Method 3 Disable PWM Timer di...

Page 284: ...Register 0x0000_0000 BPWM_PERIOD0 BPWM_BA 0x0C R W Basic PWM Period Counter Register 0 0x0000_0000 BPWM_CMPDAT0 BPWM_BA 0x10 R W Basic PWM Comparator Register 0 0x0000_0000 BPWM_CNT0 BPWM_BA 0x14 R Basic PWM Data Register 0 0x0000_0000 BPWM_PERIOD1 BPWM_BA 0x18 R W Basic PWM Period Counter Register 1 0x0000_0000 BPWM_CMPDAT1 BPWM_BA 0x1C R W Basic PWM Comparator Register 1 0x0000_0000 BPWM_CNT1 BP...

Page 285: ...4 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CLKPSC01 Bits Description 31 24 Reserved Reserved 23 16 DTI01 Dead zone Interval for Pair of Channel 0 and Channel 1 These 8 bit determine the Dead zone length The unit time of Dead zone length prescale 1 clock source divider BPWM_CLK 15 8 Reserved Reserved 7 0 CLKPSC01 Clock Prescaler Clock input is divided by CLKPSC01 1 before it is fed to the correspon...

Page 286: ... 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CLKDIV1 Reserved CLKDIV0 Bits Description 31 7 Reserved Reserved 6 4 CLKDIV1 PWM Timer 1 Clock Source Divider Selection Select clock source divider for PWM timer 1 000 1 2 001 1 4 010 1 8 011 1 16 100 1 3 Reserved Reserved 2 0 CLKDIV0 PWM Timer 0 Clock Source Divider Selection...

Page 287: ...pe 29 12 Reserved Reserved 11 CNTMODE1 PWM timer 1 Auto reload One shot Mode 0 One shot mode 1 Auto reload mode Note If there is a transition at this bit it will cause BPWM_PERIOD1 and BPWM_CMPDAT1 be cleared 10 CMPINV1 PWM timer 1 Output Inverter Enable Bit 0 Inverter Disabled 1 Inverter Enabled 9 PINV1 PWM timer 1 Output Polar Inverse Enable Bit 0 PWM1 output polar inverse Disabled 1 PWM1 output...

Page 288: ...at this bit it will cause BPWM_PERIOD0 and BPWM_CMPDAT0 be cleared 2 CMPINV0 PWM timer 0 Output Inverter Enable Bit 0 Inverter Disabled 1 Inverter Enabled 1 PINV0 PWM timer 0 Output Polar Inverse Enable Bit 0 PWM0 output polar inverse Disabled 1 PWM0 output polar inverse Enabled 0 CNTEN0 PWM timer 0 Enable Bit 0 The corresponding PWM Timer stops running 1 The corresponding PWM Timer starts running...

Page 289: ...LK prescale 1 clock divider PERIOD 1 Duty ratio CMP 1 PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM low width PERIOD CMP unit PWM high width CMP 1 unit CMP 0 PWM low width PERIOD unit PWM high width 1 unit For Center aligned type PWM frequency BPWM_CLK prescale 1 clock divider 2 PERIOD 1 Duty ratio 2 x CMP 1 2 x PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM low width ...

Page 290: ...ermines the PWM duty PWM frequency BPWM_CLK prescale 1 clock divider PERIOD 1 For Edge aligned type PWM frequency BPWM_CLK prescale 1 clock divider PERIOD 1 Duty ratio CMP 1 PERIOD 1 CMP PERIOD PWM output is always high CMP PERIOD PWM low width PERIOD CMP unit PWM high width CMP 1 unit CMP 0 PWM low width PERIOD unit PWM high width 1 unit For Center aligned type PWM frequency BPWM_CLK prescale 1 c...

Page 291: ...WM_CNT0 BPWM_BA 0x14 R Basic PWM Data Register 0 0x0000_0000 BPWM_CNT1 BPWM_BA 0x20 R Basic PWM Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 16 Reserved Reserved 15 0 CNT PWM Data Register User can monitor CNT to know the current value in 16 bit counter ...

Page 292: ...counter underflow 1 PIFn will be set if BPWM counter matches PERIODn register Note This bit is effective when BPWM in Center aligned type only 15 10 Reserved Reserved 9 DIEN1 BPWM Channel 1 Duty Interrupt Enable Bit 0 BPWM Channel 1 Duty Interrupt Disabled 1 BPWM Channel 1 Duty Interrupt Enabled 8 DIEN0 BPWM Channel 0 Duty Interrupt Enable Bit 0 BPWM Channel 0 Duty Interrupt Disabled 1 BPWM Channe...

Page 293: ... is not working in Edge aligned type selection 8 DIF0 BPWM Channel 0 Duty Interrupt Flag Flag is set by hardware when channel 0 BPWM counter down count and reaches BPWM_CMPDAT 0 software can clear this bit by writing a one to it Note If CMP equal to PERIOD this flag is not working in Edge aligned type selection 7 2 Reserved Reserved 1 PIF1 BPWM Channel 1 Period Interrupt Status This bit is set by ...

Page 294: ...ved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved POEN1 POEN0 Bits Description 31 2 Reserved Reserved 1 POEN1 Channel 1 Output Enable Register 0 BPWM channel 1 output to pin Disabled 1 BPWM channel 1 output to pin Enabled Note The corresponding GPIO pin must also be switched to BPWM function 0 POEN0 Channel 0 Output Enable Register 0 BPWM channel 0 output to pin Disabled 1 BPWM channel 0...

Page 295: ... of 1 WDT_CLK 63 Supports Watchdog Timer time out wake up function only if WDT clock source is selected as 10 kHz 6 10 3 Block Diagram Internal 18 bit WDT Up Counter 0 15 3 16 17 000 001 110 111 WDT_CLK Time out Interval Period Select Reset Delay Period Select 3 Watchdog Interrupt RSTEN WDT_CTL 1 Watchdog Reset 1 RSTCNT WDT_CTL 0 Reset WDT Counter INTEN WDT_CTL 6 WDTEN WDT_CTL 7 IF WDT_CTL 3 RSTF ...

Page 296: ...me out interval period can be selected by setting TOUTSEL WDT_CTL 10 9 When the WDT up counter reaches the TOUTSEL WDT_CTL 10 9 settings WDT time out interrupt will occur then IF WDT_CTL 3 flag will be set to 1 immediately 6 10 6 2 WDT Reset Delay Period and Reset System There is a specified TRSTD delay period follows the IF WDT_CTL 3 flag is setting to 1 User must enabled RSTCNT WDT_CTL 0 bit to ...

Page 297: ...nterrupt or not TOUTSEL Time Out Interval Period TTIS Reset Delay Period TRSTD 000 24 TWDT 1024 TWDT 001 26 TWDT 1024 TWDT 010 28 TWDT 1024 TWDT 011 210 TWDT 1024 TWDT 100 212 TWDT 1024 TWDT 101 214 TWDT 1024 TWDT 110 216 TWDT 1024 TWDT 111 218 TWDT 1024 TWDT Table 6 10 1 Watchdog Timer Time out Interval Period Selection TTIS WDT reset low reset TRSTD TRST TWDT TWDT Watchdog Clock Time Period TTIS...

Page 298: ... SERIES TECHNICAL REFERENCE MANUAL 6 10 7 Registers Map R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0x4000_4000 WDT_CTL WDT_BA 0x00 R W Watchdog Timer Control Register 0x0000_0700 ...

Page 299: ...bug Mode Acknowledge Disabl Bit Write Protect 0 ICE debug mode acknowledgement effects WDT counting WDT up counter will be kept while CPU is hanging by ICE 1 ICE debug mode acknowledgement Disabled WDT up counter will keep going no matter CPU is hanging by ICE or not 30 11 Reserved Reserved 10 8 TOUTSEL Watchdog Timer Interval Selection These three bits select the time out interval for the Watchdo...

Page 300: ...if WDT clock source is selected to 10 kHz oscillator 3 IF Watchdog Timer Time out Interrupt Flag This bit will be set to 1 while WDT up counter value reaches the selected WDT time out interval 0 WDT time out interrupt did not occur 1 WDT time out interrupt occurred Note This bit is cleared by writing 1 to it 2 RSTF Watchdog Timer Time out Reset Flag This bit indicates the system has been reset by ...

Page 301: ...ds The following protocols are supported UART SPI I 2 C To increase readability the registers of USCI have different alias names that depending on the selected protocol For example register USCI_CTL has alias name UUART_CTL for protocol UART has alias name USPI_CTL for protocol SPI and has alias name UI2C_CTL for protocol I 2 C 6 11 3 Block Diagram The basic configurations of USCI are as Figure 6 ...

Page 302: ...UART SPI and I 2 C They can be selected by FUNMODE USCI_CTL 2 0 Note that the FUNMODE must be set to 0 before changing protocol 6 11 4 1 I O Processer Input Signal All input stages offer the similar feature set They are used for all protocols Table 6 11 1 lists the relative input signals for each selected protocol Each input signal is handled by an input processor for signal conditioning such as s...

Page 303: ...figurations of control clock and data input structures are in USCI_CTLIN0 USCI_CLKIN and USCI_DATIN0 registers respectively EDGEDET USCI_DATIN0 4 3 is used to select the edge detection condition Note that the EDGEDET for USCI_DATIN0 must be set to 2 b10 in UART mode The programmable edge detection indicates that the desired event has occurred by activating the trigger signal ININV USCI_DATIN0 2 US...

Page 304: ... SPIx_MOSI I2Cx_SDA USCIx_DAT1 UARTx_TX SPIx_MISO Table 6 11 2 Output Signals for Different Protocols Note1 x 0 1 Note2 The description of protocol specific items are given in the related protocol chapters 6 11 4 2 Data Buffering The data handling of the USCI controller is based on a Data Shift Unit DSU and a buffer structure Both of the data shift and buffer registers are 16 bit wide The inputs o...

Page 305: ...f data to be transmitted The received data is stored in the receiver buffers including RX_BUF0 and RX_BUF1 User need no care about the reception sequence The receive buffer can be accessed by reading USCI_RXDAT register The first received data is read out first and the next received data becomes visible in USCI_RXDAT and can be read out next Transmitted data can be loaded to TX_BUF by writing to t...

Page 306: ...gnal if it is valid for transmission Note Slave cannot define the start itself but has to react The timing of loading data from transmit buffer to data shift unit depends on protocol configurations UART A transmission of the data word in transmit buffer can be started if TXEMPTY 0 in normal operation SPI In Master mode data transmission will be started when TXEMPTY USCI_BUFSTS 8 is 0 In Slave mode...

Page 307: ...automatically from register USCI_RXDAT USCI_LINECTL Shift Control Status Serial Bus Clock Input Control Input Shift Data Input RX_BUF0 RX_BUF1 Control 16 RX_SFTR Data Receive Buffer USCI_RXDAT Figure 6 11 7 Receive Data Path 6 11 4 3 Protocol Control and Status The protocol related control and status information are located in the protocol control register USCI_PROTCTL and in the protocol status r...

Page 308: ... generation based on an external signal Note that the external clock is half of system clock frequency because the external clock is sampled by system clock The basic clock divider counter provides the protocol relative clock signal and other protocol related signals fSAMP_CLK and fDS_CLK The timing measurement counter for time interval measurement e g baud rate detection on UART protocol The outp...

Page 309: ...ception or transmission can continue while the timer is performing timing measurements The timer counts the length of protocol related signals with fPROT_CLK or fDIV_CLK It stops counting when it reaches the user specified value Divider by 2 0 1 fREF_CLK PTCTLSEL USCI_BRGEN 1 Up Counter fPROT_CLK Protocol Relation Definition Clear 0 1 fDIV_CLK FUNMODE USCI_CTL 2 0 TMCNTSRC USCI_BRGEN 5 TMCNTEN USC...

Page 310: ...UNMODE USCI_CTL 2 0 is set to 0 the USCI is disabled When FUNMODE USCI_CTL 2 0 is set for a protocol port the internal states will be controlled by logic hardware of the selected protocol Transmit start interrupt event to indicate that a data word has been started A transmit start interrupt event occurs when the data is loaded into transmitted shift register It is indicated by flag TXSTIF USCI_PRO...

Page 311: ...XENDIEN RXSTIEN TXENDIEN and TXSTIEN of USCI_INTEN 4 1 The events are including receive end interrupt event receive start interrupt event transmit end interrupt event and transmit start interrupt event For protocol specific interrupt it is specified in each protocol interrupt enable register If a defined condition is met an event is detected and an event indication flag becomes automatically set T...

Page 312: ... up functional information is located in the Wake up Control Register USCI_WKCTL and in the Wake up Status Register USCI_WKSTS These registers are shared between the available protocols As a consequence the meaning of the bit positions in these registers is different within the protocols Event Indication Flag Indication Cleared By Interrupt Enabled By Protocol specific events in UART mode USCI_PRO...

Page 313: ...e LIN function There is incoming data to wake up the system 6 12 2 Features Supports one transmit buffer and two receive buffer for data payload Supports programmable baud rate generator Supports 9 Bit Data Transfer Supports LIN function Supports baud rate detection by built in capture event of baud rate generator Supports Wake up function 6 12 3 Block Diagram Peripheral Device User Interface Cont...

Page 314: ...iption Please refer to section 6 11 4 for detailed information 6 12 5 2 Signal Description An UART connection is characterized by the use of a single connection line between a transmitter and a receiver The receiver input signal RXD is handled by the input stage USCIx_DAT0 and the transmit output TXD signal is handled by the output stage of USCIx_DAT1 For full duplex communication an independent c...

Page 315: ... for UART Protocols Output Signals For UART protocol up to each protocol related output signals are available The number of actually used outputs depends on the selected protocol They can be classified according to their meaning for the protocols Selected Protocol UART Control Output USCI_CTL0 X USCI_CTL1 X Data Output s USCI_DAT0 X USCI_DAT1 TX Table 6 12 2 Output Signals for Different Protocols ...

Page 316: ...rame base The type of parity can be selected by bit field PARITYEN UUART_PROTCTL 1 and EVENPARITY UUART_PROTCTL 2 common for transmission and reception no parity even or odd parity If the parity handling is disabled the UART frame does not contain any parity bit For consistency reasons all communication partners have to be programmed to the same parity mode After the last data bit of the data fiel...

Page 317: ...er to section 6 12 5 for detailed description Frame format configuration The word length the stop bit number and the parity mode has to be set up according to the application requirements by programming UUART_LINECTL and the UUART_PROTCTL register It is required by the application the data input and output signals can be inverted The data transmission order is LSB first by setting LSB UUART_LINECT...

Page 318: ... of the sample clock fSAMP_CLK PDSCNT UUART_BRGEN 9 8 to define the length of a data sample time division of fREF_CLK by 1 2 3 or 4 DSCNT UUART_BRGEN 14 10 to define the number of data sample time per bit time The standard setting is given by RCLKSEL 0 fREF_CLK fPCLK PTCLKSEL 0 fPROT_CLK fREF_CLK and SPCLKSEL 0x0 fSAMP_CLK fDIV_CLK Under these conditions the baud rate is given by To generate slowe...

Page 319: ...RT_BRGEN 25 16 will be revised by BRDETITV UUART_PROTCTL 25 16 after the auto baud rate function done the time of 4 th falling edge of input signal If the user want to receive the next successive frame correctly it is better to set the value of CLKDIV UUART_BRGEN 25 16 and DSCNT UUART_BRGEN 14 10 as the same value the value shall be among the rang of 0xF and 0x5 because the DSCNT is used to define...

Page 320: ...led in UART mode Each single LIN symbol represents a complete UART frame The LIN bus is a master slave bus system with a single master and multiple slaves for the exact definition please refer to the official LIN specification A complete LIN frame contains the following symbols Synchronization Break The master sends a synchronization break to signal at the beginning of a new frame It contains 13 c...

Page 321: ...e includes incoming data Incoming data wake up source description as follows Incoming data wake up When system is in power down and both of the WKEN UUART_WKCTL 0 and DATWKEN UUART_PROTCTL 9 are set the toggle of incoming data pin can wake up the system In order to receive the incoming data after the system wake up the WAKECNT UUART_PROTCTL 14 11 shall be set These bits field of WAKECNT UUART_PROT...

Page 322: ...tection The auto baud rate interrupt ABRDETIF UUART_PROTSTS 9 indicates that the timing measurement counter has getting 2 bit duration for auto baud rate capture function The controller wil issue an interrupt if ABRIEN UUART_PROTIEN 1 is also set to 1 The auto baud rate detection function will be enabled in the first falling edge of receiver signal The auto baud rate detection function is measurem...

Page 323: ...10 and PDSCNT UUART_BRGEN 9 8 to determine the baud rate divider 3 Write line control register UUART_LINECTL and protocol control register UUART_PROTCTL to configure the transmission data format and UART protocol setting 1 Program data field length in DWIDTH UUART_LINECTL 11 8 2 Enable parity bit and determine the parity bit type by setting EVENPARITY UUART_PROTCTL 2 and PARITYEN UUART_PROTCTL 1 3...

Page 324: ...t Clock Signal Configuration Register 0x0000_0000 UUART_LINECTL x 0 1 UUARTx_BA 0x2C R W USCI Line Control Register 0x0000_0000 UUART_TXDAT x 0 1 UUARTx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 UUART_RXDAT x 0 1 UUARTx_BA 0x34 R USCI Receive Data Register 0x0000_0000 UUART_BUFCTL x 0 1 UUARTx_BA 0x38 R W USCI Transmit Receive Buffer Control Register 0x0000_0000 UUART_BUFSTS x 0 1 UUARTx_B...

Page 325: ...scription 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 0x0 The USCI is disabled Al...

Page 326: ...neration in case of a receive finish event 0 The receive end interrupt Disabled 1 The receive end interrupt Enabled 3 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled 2 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation ...

Page 327: ...abled The revised value is the average bit time between bit 5 and bit 6 The user can use revised CLKDIV and new BRDETITV UUART_PROTCTL 24 16 to calculate the precise baud rate 15 Reserved Reserved 14 10 DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 Note The maximum value of DSCNT is 0xF on U...

Page 328: ...l processor 00 fSAMP_CLK fDIV_CLK 01 fSAMP_CLK fPROT_CLK 10 fSAMP_CLK fSCLK 11 fSAMP_CLK fREF_CLK 1 PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral devi...

Page 329: ...e activates the trigger event of input data signal 10 A falling edge activates the trigger event of input data signal 11 Both edges activate the trigger event of input data signal Note In UART function mode it is suggested to set this bit field as 10 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will ...

Page 330: ...cription 31 3 Reserved Reserved 2 ININV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted or t...

Page 331: ...5 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal can be used as input for the data shift unit 0 The un synchronized signal can be taken as input ...

Page 332: ...16 bits located at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 Note In UART protocol the length can be configured as 6 13 bits 7 CTLOINV Control Signal Output Inverse Selection This bit defines t...

Page 333: ...CAL REFERENCE MANUAL 4 1 Reserved Reserved 0 LSB LSB First Transmission Selection 0 The MSB which bit of transmit receive data buffer depends on the setting of DWIDTH is transmitted received first 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 334: ...ption Reset Value UUART_TXDAT x 0 1 UUARTx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission ...

Page 335: ...34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note RXDAT 15 13 indicate the same frame status of BREAK FRMERR and PARITYERR UUART_PROTSTS 7 5 ...

Page 336: ...e PCLK cycle Note 2 It is suggest to check the RXBUSY UUART_PROTSTS 10 before this bit will be set to 1 16 TXRST Transmit Reset 0 No effect 1 Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note It is cleared automatically after one PCLK cycle 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared filling level is clea...

Page 337: ...e 337 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL pointer value Should only be used while the buffer is not taking part in data traffic Note It is cleared automatically after one PCLK cycle 6 0 Reserved Reserved ...

Page 338: ...XFULL Transmit Buffer Full Indicator 0 Transmit buffer is not full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty 7 4 Reserved Reserved 3 RXOVIF Receive Buffer Over run Error Interrupt Status This bit indicates that a receive buffer overrun error event has been detected If RXOVIEN UUART_BUFCTL 14 is enabled the correspo...

Page 339: ...2 1 0 Reserved PDBOPT Reserved WKEN Bits Description 31 3 Reserved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transfer wil...

Page 340: ...ue UUART_WKSTS x 0 1 UUARTx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 341: ...is bit is set to logic 1 the serial data output TX is forced to the Spacing State logic 0 This bit acts only on TX line and has no effect on the transmitter logic 27 Reserved Reserved 26 STICKEN Stick Parity Enable Bit 0 Stick parity Disabled 1 Stick parity Enabled 25 Reserved Reserved 24 16 BRDETITV Baud Rate Detection Interval This bit fields indicate how many clock cycle selected by TMCNTSRC UU...

Page 342: ...sent out before the 1st data be transmitted 6 ABREN Auto baud Rate Detect Enable Bit 0 Auto baud rate detect function Disabled 1 Auto baud rate detect function Enabled Note When the auto baud rate detect operation finishes hardware will clear this bit The associated interrupt ABRDETIF USCI_PROTST 9 will be generated If ARBIEN UUART_PROTIEN 1 is enabled 5 4 Reserved Reserved 3 Reserved Reserved 2 E...

Page 343: ...5 4 3 2 1 0 Reserved RLSIEN ABRIEN BRKIEN Bits Description 31 3 Reserved Reserved 2 RLSIEN Receive Line Status Interrupt Enable Bit 0 Receive line status interrupt Disabled 1 Receive line status interrupt Enabled Note UUART_PROTSTS 7 5 indicates the current interrupt event for receive line status interrupt 1 ABRIEN Auto baud Rate Interrupt Enable Bit 0 Auto baud rate interrupt Disabled 1 Auto baud...

Page 344: ...t overrun 1 Auto baud rate detect counter is overrun Note 1 This bit is set at the same time of ABRDETIF Note 2 This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS 10 RXBUSY RX Bus Status Flag Read Only This bit indicates the busy status of the receiver 0 The receiver is Idle 1 The receiver is BUSY 9 ABRDETIF Auto baud Rate Interrupt Flag This bit is set when auto baud rate detection is d...

Page 345: ... This bit is set to logic 1 whenever the received character does not have a valid parity bit 0 No parity error is generated 1 Parity error is generated Note This bit can be cleared by write 1 among the BREAK FRMERR and PARITYERR bits 4 RXENDIF Receive End Interrupt Flag 0 A receive finish interrupt status has not occurred 1 A receive finish interrupt status has occurred Note It is cleared by softw...

Page 346: ... mode by setting the SLAVE USPI_PROTCTL 0 to communicate with the off chip SPI Slave or master device The application block diagrams in master and Slave mode are shown as Figure 6 13 1 and Figure 6 13 2 SPI Slave Device Master Transmit Data Master Receive Data Serial Bus Clock Slave Select SPI_MOSI USCIx_DAT0 SPI_MISO USCIx_DAT1 SPI_CLK USCIx_CLK SPI_SS USCIx_CTL SPI_MOSI SPI_MISO USCI SPI Master ...

Page 347: ... Slave mode 6 13 3 Block Diagram Peripheral Device User Interface Control Register Data Buffer Data Shift Unit SPI Protocol Processor Unit Input Processor Buffer Control Interrupt Generation USCIx_DAT0 1 To Interrupt Signal USCIx_CLK USCIx_CTL0 Wake up Control Protocol Relative Clock Generator fPCLK Output Configuration Note x 0 1 Figure 6 13 3 USCI SPI Mode Block Diagram 6 13 4 Basic Configuratio...

Page 348: ...nd the end of a data transfer and the master device can use it to enable the transmitting or receiving operations of slave device Slave device receives the SPI bus clock and optionally a slave select signal for data transaction The signals for SPI communication are shown as Table 6 13 1 SPI Mode Receive Data Transmit Data Serial Bus Clock Slave Select Full duplex SPI Master SPI_MISO USCIx_DAT1 SPI...

Page 349: ...protocol relative clock generator In slave mode the SPI bus clock is provided by an off chip Master device The peripheral clock frequency fPCLK of SPI Slave device must be 5 times faster than the serial bus clock rate of the SPI Master device connected together i e the clock rate of serial bus clock 1 5 peripheral clock in Slave mode In SPI protocol SCLKMODE USPI_PROTCTL 7 6 defines not only the i...

Page 350: ...TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n SLAVE USPI_PROTCTL 0 0 SCLKMODE USPI_PROTCTL 7 6 0x0 ININV USPI_CTLIN0 2 1 LSB USPI_LINECTL 0 0 CTLOINV USPI_LINECTL 7 1 Note x 0 1 Data N Data N 1 Data Frame SPI_SS USCIx_CTL0 SPI_MOSI USCIx_DAT0 SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 RX n 1 MSB RX n MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX ...

Page 351: ...NV USPI_CTLIN0 2 setting of slave device should be set to 1 for the inversion of input control signal If USCI operates as SPI Master mode the output slave select inversion CTLOINV USPI_LINECTL 7 is also Data N Data N 1 Data Frame SPI_SS USCIx_CTL0 SPI_MOSI USCIx_DAT0 SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB RX n MSB TX n TX n 1 LSB TX 0 LSB RX 0 RX n 1 MSB...

Page 352: ... transmitting and receiving data in SPI communication The LSB bit USPI_LINECTL 0 defines the order of transfer data bit If the LSB bit is set to 1 the transmission data sequence is LSB first If the LSB bit is cleared to 0 the transmission data sequence is MSB first SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 SPI_MOSI USCIx_DAT0 TX 14 TX 8 TX 7 TX 6 LSB TX 0 RX 14 RX 8 RX 6 LSB RX 0 MSB RX 15 RX 7 MSB TX...

Page 353: ...eans that the slave select signal will be asserted by the USCI controller when the SPI data transfer is started by writing to the transmit buffer And it will be de asserted after either all transaction is finished or one word transaction done if the value of SUSPITV USPI_PROTCTL 11 8 is equal to or great than 3 If the AUTOSS bit USPI_PROTCTL 3 is cleared the slave selected on USCIx_CTL0 pin will b...

Page 354: ...PROTCTL 2 One word transaction One word transaction Note Automatic slave select is enabled Figure 6 13 13 Auto Slave Select SUSPITV 0x3 6 13 5 8 Slave 3 wire Mode When the SLV3WIRE USPI_PROTCTL 1 is set by software to enable the Slave 3 wire mode the USCI SPI communication can work with no slave select signal in Slave mode The SLV3WIRE USPI_PROTCTL 1 only takes effect in SPI Slave mode Only three ...

Page 355: ...mit end interrupt The interrupt event TXENDIF USPI_PROTSTS 2 is set after the start of the last data bit of the last transmit data which has been stored in transmit buffer It can be cleared only by writing 1 to it The controller wil issue an interrupt if TENDIEN USPI_INTEN 2 is also set to 1 Receive start interrupt The interrupt event RXSTIF USPI_PROTSTS 3 is set after the start of the first data ...

Page 356: ...6 before one word transaction is done the Slave time out interrupt event occurs and the SLVTOIF USPI_PROTSTS 5 will be set to 1 Buffer Related Interrupts The buffer related interrupts are available if there is transmit receive buffer in USCI controller Receive buffer overrun interrupt If there is receive buffer overrun event RXOVIF USPI_BUFSTS 3 will be set as 1 It can be cleared by write 1 into i...

Page 357: ...ode FUNMODE 0x1 SLAVE 0 LSB 0 DWIDTH 0x8 SCLKMODE 0x2 CTLOINV 0 CTLOINV 1 Note x 0 1 Figure 6 13 14 SPI Timing in Master Mode SPI_CLK USCIx_CLK SPI_MISO USCIx_DAT1 SPI_MOSI USCIx_DAT0 TX 1 TX 3 TX 4 TX 5 MSB TX 7 RX 1 RX 3 RX 5 MSB RX 7 LSB RX 0 RX 4 LSB TX 0 SPI_SS USCIx_CTL0 SCLKMODE 0x1 TX 2 RX 2 TX 6 RX 6 SCLKMODE 0x3 Master Mode FUNMODE 0x1 SLAVE 0 LSB 1 DWIDTH 0x8 CTLOINV 0 CTLOINV 1 Note x ...

Page 358: ...PI_MISO USCIx_DAT1 SPI_MOSI USCIx_DAT0 TX0 1 TX0 7 TX1 0 TX1 1 MSB TX1 7 RX0 1 RX0 7 RX1 1 MSB RX1 7 LSB RX0 0 RX1 0 LSB TX0 0 SPI_SS USCIx_CTL0 SCLKMODE 0x1 SCLKMODE 0x3 Slave Mode FUNMODE 0x1 SLAVE 1 SLV3WIRE 0 LSB 1 DWIDTH 0x8 CTLOINV 0 CTLOINV 1 Note x 0 1 Figure 6 13 17 SPI Timing in Slave Mode Alternate Phase of Serial Bus Clock 6 13 5 12Programming flow This section describes the programmin...

Page 359: ...r 9 User can get the received data by reading USPI_RXDAT register as long as RXEMPTY USPI_BUFSTS 0 is 0 The SPI data transfer can be triggered by writing USPI_TXDAT register as long as TXFULL USPI_BUFSTS 9 is 0 For Slave mode 1 Enable USCI peripheral clock by setting CLK_APBCLK register 2 Configure user specified pins as USCI function pins by setting corresponding multiple function control registe...

Page 360: ...of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 6 13 5 13Wake up Function The USCI Controller in SPI mode supports wake up system function The wake up source in SPI protocol is the transition of input slave select signal ...

Page 361: ...x 0 1 USPIx_BA 0x28 R W USCI Input Clock Signal Configuration Register 0x0000_0000 USPI_LINECTL x 0 1 USPIx_BA 0x2C R W USCI Line Control Register 0x0000_0000 USPI_TXDAT x 0 1 USPIx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 USPI_RXDAT x 0 1 USPIx_BA 0x34 R USCI Receive Data Register 0x0000_0000 USPI_BUFCTL x 0 1 USPIx_BA 0x38 R W USCI Transmit Receive Buffer Control Register 0x0000_0000 US...

Page 362: ...ription 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 0x0 The USCI is disabled All ...

Page 363: ...ration in case of a receive finish event 0 The receive end interrupt Disabled 1 The receive end interrupt Enabled 3 RXSTIEN Receive Start Interrupt Enable Bit This bit enables the interrupt generation in case of a receive start event 0 The receive start interrupt Disabled 1 The receive start interrupt Enabled 2 TXENDIEN Transmit End Interrupt Enable Bit This bit enables the interrupt generation in...

Page 364: ...lock divider frequency fDIV_CLK fDIV_CLK fPROT_CLK CLKDIV 1 15 10 Reserved Reserved 9 6 Reserved Reserved 5 TMCNTSRC Time Measurement Counter Clock Source Selection 0 Time measurement counter with fPROT_CLK 1 Time measurement counter with fDIV_CLK 4 TMCNTEN Time Measurement Counter Enable Bit This bit enables the 10 bit timing measurement counter 0 Time measurement counter Disabled 1 Time measurem...

Page 365: ...6 2017 Page 365 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 0 RCLKSEL Reference Clock Source Selection This bit selects the source of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 HXT LXT ...

Page 366: ... This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted Note In SPI protocol we suggested this bit should be set as 0 1 Reserved Reserved 0 SYNCSEL Input Signal Synchronization Selection This bit selects if the un synchronized input signal with optionally inverted or the synch...

Page 367: ...INV Input Signal Inverse Selection This bit defines the inverter enable of the input asynchronous signal 0 The un synchronized input signal will not be inverted 1 The un synchronized input signal will be inverted 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal with optionally inverted or the synchronized and optionally filte...

Page 368: ...6 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SYNCSEL Bits Description 31 1 Reserved Reserved 0 SYNCSEL Input Synchronization Signal Selection This bit selects if the un synchronized input signal or the synchronized and optionally filtered signal can be used as input for the data shift unit 0 The un synchronized signal can be taken as input for the data shift unit 1 The synchr...

Page 369: ...The data word contains 16 bits located at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions 14 0 7 CTLOINV Control Signal Output Inverse Selection This bit defines the relation between the internal control ...

Page 370: ...CAL REFERENCE MANUAL 4 1 Reserved Reserved 0 LSB LSB First Transmission Selection 0 The MSB which bit of transmit receive data buffer depends on the setting of DWIDTH is transmitted received first 1 The LSB the bit 0 of data buffer will be transmitted received first ...

Page 371: ...gister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission In order to avoid overwriting the transmit data user have to check TXEMPTY USPI_BUFSTS 8 status before writing transmit ...

Page 372: ...iption Reset Value USPI_RXDAT x 0 1 USPIx_BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer ...

Page 373: ...data buffer Note It is cleared automatically after one PCLK cycle 16 TXRST Transmit Reset 0 No effect 1 Reset the transmit related counters state machine and the content of transmit shift register and data buffer Note It is cleared automatically after one PCLK cycle 15 RXCLR Clear Receive Buffer 0 No effect 1 The receive buffer is cleared Should only be used while the buffer is not taking part in ...

Page 374: ...age 374 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 6 TXUDRIEN Slave Transmit Under run Interrupt Enable Bit 0 Transmit under run interrupt Disabled 1 Transmit under run interrupt Enabled 5 0 Reserved Reserved ...

Page 375: ... is activated It is cleared by software writes 1 to this bit 0 A transmit buffer under run event has not been detected 1 A transmit buffer under run event has been detected 10 Reserved Reserved 9 TXFULL Transmit Buffer Full Indicator 0 Transmit buffer is not full 1 Transmit buffer is full 8 TXEMPTY Transmit Buffer Empty Indicator 0 Transmit buffer is not empty 1 Transmit buffer is empty and availa...

Page 376: ...Mini57 Apr 06 2017 Page 376 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 1 Receive buffer is full ...

Page 377: ... 1 0 Reserved PDBOPT Reserved WKEN Bits Description 31 3 Reserved Reserved 2 PDBOPT Power Down Blocking Option 0 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring MCU will stop the transfer and enter Power down mode immediately 1 If user attempts to enter Power down mode by executing WFI while the protocol is in transferring the on going transfer will...

Page 378: ...lue USPI_WKSTS x 0 1 USPIx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 379: ...1 if TX under run event occurs 27 26 Reserved Reserved 25 16 SLVTOCNT Slave Mode Time out Period Slave Only In Slave mode this bit field is used for Slave time out period This bit field indicates how many clock periods selected by TMCNTSRC USPI_BRGEN 5 between the two edges of input SCLK will assert the Slave time out event Writing 0x0 into this bit field will disable the Slave time out function E...

Page 380: ...ed with rising edge and received with falling edge MODE3 The idle state of SPI clock is high level Data is transmitted with falling edge and received with rising edge 5 4 Reserved Reserved 3 AUTOSS Automatic Slave Select Function Enable Master Only 0 Slave select signal will be controlled by the setting value of SS USPI_PROTCTL 2 bit 1 Slave select signal will be generated automatically The slave ...

Page 381: ...ng of DWIDTH USPI_LINECTL 11 8 Bit count error event occurs 0 Slave mode bit count error interrupt Disabled 1 Slave mode bit count error interrupt Enabled 2 SLVTOIEN Slave Time out Interrupt Enable Bit In SPI protocol this bit enables the interrupt generation in case of a Slave time out event 0 Slave time out interrupt Disabled 1 Slave time out interrupt Enabled 1 SSACTIEN Slave Select Active Inte...

Page 382: ...8 or not 0 Slave transmit under run event does not occur 1 Slave transmit under run event occurs 17 BUSY Busy Status Read Only 0 SPI is in idle state 1 SPI is in busy state The following listing are the bus busy conditions a USPI_PROTCTL 31 1 and the TXEMPTY 0 b For SPI Master mode the TXEMPTY 1 but the current transaction is not finished yet c For SPI Slave mode the USPI_PROTCTL 31 1 and there is...

Page 383: ...event does not occur 1 Slave bit count error event occurs Note It is cleared by software writes 1 to this bit 5 SLVTOIF Slave Time out Interrupt Flag for Slave Only 0 Slave time out event does not occur 1 Slave time out event occurs Note It is cleared by software writes 1 to this bit 4 RXENDIF Receive End Interrupt Flag 0 Receive end event does not occur 1 Receive end event occurs Note It is clear...

Page 384: ...ed START tSU_STA tSU_STO STOP tr Figure 6 14 1 I 2 C Bus Timing The device on chip I 2 C provides the serial interface that meets the I 2 C bus standard mode specification The I 2 C port handles byte transfers autonomously The I 2 C mode is selected by FUNMODE UI2C_CTL 2 0 0100B When this port is enabled the USCI interfaces to the I 2 C bus via two pins SDA and SCL When I O pins are used as I 2 C ...

Page 385: ...s follows USCI0 pins are configured on SYS_GPA_MFP SYS_GPC_MFP SYS_GPD_MFP registers Enable USCI0 clock USCI0CKEN on CLK_APBCLK 24 register Reset USCI0 controller USCI0RST on SYS_IPRST1 24 register Enable I2C function FUNMODE 100 on UI2C_CTL 2 0 register The basic configurations of USCI1 for I 2 C are as follows USCI1 pins are configured on SYS_GPA_MFP SYS_GPC_MFP SYS_GPD_MFP registers Enable USCI...

Page 386: ...defined as a HIGH to LOW transition on the SDA line while SCL is HIGH The START signal denotes the beginning of a new data transmission A Repeated START is not a STOP signal between two START signals and usually referred to as the Sr bit The master uses this method to communicate with another slave or the same slave in a different transfer direction e g from writing to a device to reading from a d...

Page 387: ...re compared to the programmed slave address UI2C_DEVADDR0 6 0 If these bits match the slave sends an acknowledge In addition if the slave address is programmed to 1111 0XXB the XX bits are compared to the bits UI2C_DEVADDR0 9 8 to check for address match and also sends an acknowledge when ADDR10EN UI2C_PROTCTL 4 is set The slave waits for a second address byte compares it with UI2C_DEVADDR0 7 0 an...

Page 388: ...igure 6 14 6 Acknowledge on I 2 C Bus 6 14 5 6 Clock Baud Rate Bits For this section please refer to Figure 6 11 9 The data baud rate of I 2 C is determines by UI2C_BRGEN register when I 2 C is in Master Mode and it is not necessary in a Slave mode In the Slave mode I 2 C will automatically synchronize it with any clock frequency from master I 2 C device The bits RCLKSEL SPCLKSEL PDSCNT and DSCNT ...

Page 389: ...5 8 Master Arbitration In some applications there are two or more masters on the same I 2 C bus to access slaves and the masters may transmit data simultaneously The I 2 C supports multi master by including collision detection and arbitration to prevent data corruption If two masters sometimes initiate I 2 C command at the same time the arbitration procedure determines which master wins and can co...

Page 390: ...ing the arbitration phase and while a slave is transmitting the resulting loop delay of the transmission chain can limit the reachable maximal baud rate strongly depending on the bus characteristics bus load module frequency etc The shift clock SCL is generated by the master device output on the wire then it passes through the input stage and the input filter Now the edges can be detected and the ...

Page 391: ...C control flow has to be done while FUNMODE UI2C_CTL 2 0 000B to avoid unintended edges of the input signals and the I 2 C mode can be enabled by FUNMODE UI2C_CTL 2 0 100B afterwards Step 1 Set FUNMODE UI2C_CTL 2 0 000B Step 2 Set FUNMODE UI2C_CTL 2 0 100B Pin connections The pins used for SDA and SCL have to be set to open drain mode by USCI controller to support the wired AND structure of the I ...

Page 392: ...according to current status of UI2C_PROTSTS register In other words for each I 2 C bus action user needs to check current status by UI2C_PROTSTS register and then set UI2C_PROTCTL UI2C_PROTIEN TXDAT registers to take bus action Finally check the response status by UI2C_PROTSTS The bits STA STO and AA in UI2C_PROTCTL register are used to control the next state of the I 2 C hardware after interrupt ...

Page 393: ...rt transmitting data after the slave returns acknowledge to the master 1 read S SLAVE ADDRESS R W A DATA A DATA A A P data transfer n bytes acknowlegde Figure 6 14 10 Master Reads Data from Slave with a 7 bit Address Figure 6 14 11 shows a master transmits data to slave by 10 bit address A master addresses a slave with a 10 bit address First byte contains 10 bit address indicator 5 b11110 and 2 bi...

Page 394: ...ear protocol status register ACKIF 1 NACKIF 1 ACKIF 1 NACKIF 1 TXDAT Data PTRG STA STO AA 1 0 0 x Writing 1 to ACKIF Writing 1 to NACKIF STARIF 1 PTRG STA STO AA 1 1 0 x Writing 1 to ACKIF Writing 1 to NACKIF STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to ACKIF Writing 1 to NACKIF STARIF 1 PTRG STA STO AA 1 1 1 x Writing 1 to ACKIF Writing 1 to NACKIF TXDAT SLA W ARBLOIF 1 TXDAT SLA W PTRG STA STO ...

Page 395: ...TXDAT SLA R S NAK S ACK NAK STORIF 1 Writing 1 to STORIF Writing 1 to STORIF TXDAT SLA R TXDAT SLA R PTRG STA STO AA 1 0 0 1 ARBLOIF 1 ACK To corresponding states in slave mode Figure 6 14 14 Master Receiver Mode Control Flow with 7 bit Address If the I 2 C is in Master mode and gets arbitration lost the bit of ARBLOIF UI2C_PROTSTS 11 will be set User may writing 1 to ARBLOIF UI2C_PROTSTS 11 and s...

Page 396: ...0 Writing 1 to ACKIF Writing 1 to ARBLOIF ACKIF 1 NACKIF 1 NAK ARBLOIF 1 ACKIF 1 RXDAT Data PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF RXDAT Data PTRG STA STO AA 1 0 0 0 Writing 1 to ACKIF ACKIF 1 NACKIF 1 Arbitration Lost Master to Slave Slave to Master STORIF 1 ARBLOIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 1 Writing 1 to ACKIF Writing 1 to NACKIF Writing 1 to STORIF Switch to not addressed mode Own S...

Page 397: ... switch to not address mode and own SLA will not be recognized If setting this interrupt flag slave will not receive any I 2 C signal or address from master At this status I 2 C should be reset by setting FUNMODE UI2C_CTL 2 0 000B to leave this status General Call GC Mode If the GCFUNC bit UI2C_PROTCTL 0 is set the I 2 C port hardware will respond to General Call address 00H User can clear GC bit ...

Page 398: ...ORIF Switch to not addressed mode Own SLA will be recognized Become I2 C Slave Become I2 C Slave RXDAT SLA W 0x00 ARBLOIF 1 Arbitraion Lost Arbitraion Lost Master to Slave Master to Slave Slave to Master Slave to Master STORIF 1 Sr Sr Sr PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF PTRG STA STO AA 1 0 0 X Writing 1 to ACKIF Writing 1 to ARBLOIF S ACK NAK ACK NAK P STARIF 1 Figur...

Page 399: ...een I2C Baud Rate and PCLKshows the relationship between I 2 C baud rate and PCLK the number of table represent one clock duty contain how many PCLKs Setup and hold time configuration even can program some extreme values in our design but user should follow I 2 C protocol standard I2 C Baud Rate PCLK 100k 200k 400k 12MHz 120 60 30 24MHz 240 120 60 48MHz 480 240 120 Table 6 14 1 Relationship betwee...

Page 400: ... counter and re start up counting after TOIF is cleared Refer to Figure 6 14 19 for the time out counter TOCNT UI2C_PROTCTL 25 16 TTOCNT TOCNT UI2C_PROTCTL 25 16 1 x32 5 bit x TPCLK Note that the time counter clock source TMCNTSRC USCI_ BRGEN 5 must be set zero Internal counter TOIF Clear Counter TOIEN Interrupt signal Enable fSAMP_CLK Writing TOIF 1 TOCNT I2 C interrupt signal ACKIF NACKIF Figure...

Page 401: ... indicate this event User needs write 1 to clear this bit I 2 C also support data toggle mode When system is in power down and the WKEN UI2C_WKCTL 0 set to 1 and WKADDREN UI2C_WKCTL 1 set to 0 the toggle of incoming data pin can wake up the system Example for Random Read on EEPROM The following steps are used to configure the USCI0_I 2 C related registers when using I 2 C protocol to read data fro...

Page 402: ...Writing 1 to NACKIF TXDAT SLA W PTRG STA STO AA 1 0 0 x Write 1 to STARIF ACKIF 1 NAK NACKIF 1 TXDAT ROM Address Low Byte ACK ACKIF 1 I2C_DAT ROM Address Low Byte PTRG STA STO AA 1 0 0 x P STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to NACKIF NAK NACKIF 1 TXDAT Data NAK NACKIF 1 Read I2C_DAT to Get Data PTRG STA STO AA 1 0 0 0 Writing 1 to ACKIF P STORIF 1 PTRG STA STO AA 1 0 1 x Writing 1 to NACKI...

Page 403: ...it Data Register 0x0000_0000 UI2C_RXDAT UI2Cx_BA 0x34 R USCI Receive Data Register 0x0000_0000 UI2C_DEVADDR0 UI2Cx_BA 0x44 R W USCI Device Address Register 0 0x0000_0000 UI2C_ADDRMSK0 UI2Cx_BA 0x4C R W USCI Device Address Mask Register 0 0x0000_0000 UI2C_WKCTL UI2Cx_BA 0x54 R W USCI Wake up Control Register 0x0000_0000 UI2C_WKSTS UI2Cx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 UI2C_PROT...

Page 404: ...tion 31 3 Reserved Reserved 2 0 FUNMODE Function Mode This bit field selects the protocol for this USCI controller Selecting a protocol that is not available or a reserved combination disables the USCI When switching between two protocols the USCI has to be disabled before selecting a new protocol Simultaneously the USCI will be reset when user write 000 to FUNMODE 000 The USCI is disabled All pro...

Page 405: ...lue is the average bit time between bit 5 and bit 6 The user can use revised CLKDIV and new BRDETITV UI2C_PROTCTL 24 16 to calculate the precise baud rate 15 Reserved Reserved 14 10 DSCNT Denominator for Sample Counter This bit field defines the divide ratio of the sample clock fSAMP_CLK The divided frequency fDS_CNT fPDS_CNT DSCNT 1 Note The maximum value of DSCNT is 0xF on UART mode and suggest ...

Page 406: ...LK fDIV_CLK 01 fSAMP_CLK fPROT_CLK 10 fSAMP_CLK fSCLK 11 fSAMP_CLK fREF_CLK 1 PTCLKSEL Protocol Clock Source Selection This bit selects the source signal of protocol clock fPROT_CLK 0 Reference clock fREF_CLK 1 fREF_CLK2 its frequency is half of fREF_CLK 0 RCLKSEL Reference Clock Source Selection This bit selects the source signal of reference clock fREF_CLK 0 Peripheral device clock fPCLK 1 HXT L...

Page 407: ...nsmission The data word is always right aligned in the data buffer USCI support word length from 4 to 16 bits 0x0 The data word contains 16 bits located at bit positions 15 0 0x1 Reserved 0x2 Reserved 0x3 Reserved 0x4 The data word contains 4 bits located at bit positions 3 0 0x5 The data word contains 5 bits located at bit positions 4 0 0xF The data word contains 15 bits located at bit positions ...

Page 408: ...cription Reset Value UI2C_TXDAT UI2Cx_BA 0x30 W USCI Transmit Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TXDAT 7 6 5 4 3 2 1 0 TXDAT Bits Description 31 16 Reserved Reserved 15 0 TXDAT Transmit Data Software can use this bit field to write 16 bit transmit data for transmission ...

Page 409: ...UI2C_RXDAT UI2Cx_BA 0x34 R USCI Receive Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXDAT 7 6 5 4 3 2 1 0 RXDAT Bits Description 31 16 Reserved Reserved 15 0 RXDAT Received Data This bit field monitors the received data which stored in receive data buffer Note 1 In I2 C protocol only use RXDAT 7 0 ...

Page 410: ...18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DEVADDR 7 6 5 4 3 2 1 0 DEVADDR Bits Description 31 10 Reserved Reserved 9 0 DEVADDR Device Address In I2 C protocol this bit field contains the programmed slave address If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR 9 8 to check for address match where the X is R W bit Then the second address byte is a...

Page 411: ... 6 5 4 3 2 1 0 ADDRMSK Bits Description 31 10 Reserved Reserved 9 0 ADDRMSK USCI Device Address Mask 0 Mask Disabled the received corresponding register bit should be exact the same as address register 1 Mask Enabled the received corresponding address bit is don t care USCI support multiple address recognition with two address mask register When the bit in the address mask register is set to one i...

Page 412: ... Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKADDREN WKEN Bits Description 31 2 Reserved Reserved 1 WKADDREN Wake up Address Match Enable Bit 0 The chip is woken up according to data toggle 1 The chip is woken up according to address match 0 WKEN Wake up Enable Bit 0 Wake up function Disabled 1 Wake...

Page 413: ... Value UI2C_WKSTS UI2Cx_BA 0x58 R W USCI Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WKF Bits Description 31 1 Reserved Reserved 0 WKF Wake up Flag When chip is woken up from Power down mode this bit is set to 1 Software can write 1 to clear this bit ...

Page 414: ...gger When a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2 C interrupt is requested It must write one by software to this bit after the related interrupt flags are set to 1 and the I2 C protocol function will go ahead until the STOP is active or the PROTEN is disabled 0 I2 C s stretch disabled and the I2 C protocol function will go ahead 1 I2 ...

Page 415: ...the acknowledge clock pulse on the SCL line when 1 A slave is acknowledging the address sent from master 2 The receiver devices are acknowledging the data sent by transmitter When AA 0 prior to address or data received a Not acknowledged high level to SDA will be returned during the acknowledge clock pulse on the SCL line 0 GCFUNC General Call Function 0 General Call Function Disabled 1 General Ca...

Page 416: ...ERRIEN Error Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an I2 C error condition is detected indicated by ERR UI2C_PROTSTS 16 0 The error interrupt Disabled 1 The error interrupt Enabled 4 ARBLOIEN Arbitration Lost Interrupt Enable Bit This bit enables the generation of a protocol interrupt if an arbitration lost event is detected 0 The arbitration lost interrup...

Page 417: ...enables the generation of a protocol interrupt if a start condition is detected 0 The start condition interrupt Disabled 1 The start condition interrupt Enabled 0 TOIEN Time out Interrupt Enable Bit In I2 C protocol this bit enables the interrupt generation in case of a time out event 0 The time out interrupt Disabled 1 The time out interrupt Enabled ...

Page 418: ...status for transmission Note This bit has no interrupt signal and it will be cleared automatically by hardware 17 WRSTSWK Read Write Status Bit in Address Wake up Frame 0 Write command be record on the address match wake up frame 1 Read command be record on the address match wake up frame 16 WKAKDONE Wake up Address Frame Acknowledge Bit Done 0 The ACK bit cycle of address match frame isn t done 1...

Page 419: ...s cleared by software writing one into this bit 10 NACKIF Non Acknowledge Received Interrupt Flag This bit indicates that a non acknowledge has been received in master mode This bit is not set in slave mode A protocol interrupt can be generated if UI2C_PROTCTL NACKIEN 1 0 A non acknowledge has not been received 1 A non acknowledge has been received It is cleared by software writing one into this b...

Page 420: ...ERENCE MANUAL 1 The bus is busy 5 TOIF Time out Interrupt Flag 0 A time out interrupt status has not occurred 1 A time out interrupt status has occurred Note It is cleared by software writing one into this bit 4 3 Reserved Reserved 2 0 Reserved Reserved 0 Reserved Reserved ...

Page 421: ...13 12 11 10 9 8 Reserved HTCTL 7 6 5 4 3 2 1 0 HTCTL STCTL Bits Description 31 8 Reserved Reserved 11 6 HTCTL Hold Time Configure Control Register This field is used to generate the delay timing between SCL falling edge SDA edge in transmission mode The delay hold time is numbers of peripheral clock HTCTL x fPCLK 5 0 STCTL Setup Time Configure Control Register This field is used to generate a dela...

Page 422: ...teger calculation 32 bit dividend with 16 bit divisor calculation capacity 32 bit quotient and 32 bit remainder outputs 16 bit remainder with sign extends to 32 bit Divided by zero warning flag 6 HCLK clocks taken for one cycle calculation Write divisor to trigger calculation Waiting for calculation ready automatically when reading quotient and remainder 6 15 3 Basic Configuration Before using the...

Page 423: ...signed integer and divisor is 16 bit signed integer The quotient is 32 bit signed integer and the remainder is 16 bit signed integer It is noted that the case of dividing the minimum dividend by 1 the quotient is set to be the minimum negative value since overflow and the remainder is set to 0 This is the only case the quotient is not represented in a positive number when a negative number by a ne...

Page 424: ...tion Reset Value HDIV Base Address HDIV_BA 0x5001_4000 HDIV_DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 HDIV_DIVISOR HDIV_BA 0x04 R W Divisor Source Resister 0x0000_FFFF HDIV_QUOTIENT HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 HDIV_REM HDIV_BA 0x0C R W Remainder Result Register 0x0000_0000 HDIV_STATUS HDIV_BA 0x10 R Divider Status Register 0x0000_0001 ...

Page 425: ...gister Offset R W Description Reset Value HDIV_DIVIDEND HDIV_BA 0x00 R W Dividend Source Register 0x0000_0000 31 30 29 28 27 26 25 24 DIVIDEND 23 22 21 20 19 18 17 16 DIVIDEND 15 14 13 12 11 10 9 8 DIVIDEND 7 6 5 4 3 2 1 0 DIVIDEND Bits Description 31 0 DIVIDEND Dividend Source This register is given the dividend of divider before calculation is started ...

Page 426: ..._BA 0x04 R W Divisor Source Resister 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DIVISOR 7 6 5 4 3 2 1 0 DIVISOR Bits Description 31 16 Reserved Reserved 15 0 DIVISOR Divisor Source This register is given the divisor of divider before calculation starts Note When this register is written hardware divider will start calculation ...

Page 427: ...W Description Reset Value HDIV_QUOTIENT HDIV_BA 0x08 R W Quotient Result Resister 0x0000_0000 31 30 29 28 27 26 25 24 QUOTIENT 23 22 21 20 19 18 17 16 QUOTIENT 15 14 13 12 11 10 9 8 QUOTIENT 7 6 5 4 3 2 1 0 QUOTIENT Bits Description 31 0 QUOTIENT Quotient Result This register holds the quotient result of divider after calculation is completed ...

Page 428: ...scription Reset Value HDIV_REM HDIV_BA 0x0C R W Remainder Result Register 0x0000_0000 31 30 29 28 27 26 25 24 REM 23 22 21 20 19 18 17 16 REM 15 14 13 12 11 10 9 8 REM 7 6 5 4 3 2 1 0 REM Bits Description 31 0 REM Remainder Result The remainder of hardware divider is 16 bit sign integer REM 15 0 with sign extension REM 31 16 to 32 bit integer ...

Page 429: ...001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DIVBYZERO Reserved Bits Description 31 2 Reserved Reserved 1 DIVBYZERO Divisor Zero Warning Read Only 0 The divisor is not 0 1 The divisor is 0 Note The DIVBYZERO flag is used to indicate divide by zero situation and updated whenever HDIV_DIVISOR is written This bit is read...

Page 430: ...ADC_PBRK WCMPIEN ADC_WCMPCTL 1 ADC1IEN ADC_CTL 9 ADC0IEN ADC_CTL 1 WCMPMCNT ADC_WCMPCTL 11 8 1 3 14 3 2 STADC trigger state rising falling rising falling PWMn rising falling Central period ADCMODE ADC_CTL 7 6 ADC1TRGSOR trigger source selection Event Flag register Sequencer Control FIFO2 only use by Sequencer LOW_Bund HIGH_Bund EQU_FLAG HIGH_FLAG LOW_FLAG Window Comparator Sequential mode 2S H 0 1...

Page 431: ...hen changing the analog input channel is enabled in order to prevent incorrect operation software must clear ADCnSWTRG bit to 0 in the ADC_CTL register The A D converter discards the current conversion immediately and enters idle state while ADCnSWTRG bit is cleared 6 16 2 1 ADC Peripheral Clock Generator The ADC engine has four clock sources selected by ADCSEL CLK_CLKSEL1 and selected between HXT...

Page 432: ...DAT 11 0 ADC_CLK Fixed Conversion time 1000ns Min S H time 200ns Figure 6 16 3 Single Mode Conversion Timing Diagram 6 16 2 3 Hardware Trigger Input Sampling and A D Conversion Time A D conversion can be triggered by hardware trigger request When the ADCnHWTRGEN bit of ADC_CTL register is set to 1 to enable ADC hardware trigger function setting the ADCnTRGSOR bits to 0000b is to select external tr...

Page 433: ...lue When the compare result meets the setting compare match counter will increase 1 otherwise the compare match counter will be clear to 0 When the match counter reaches the setting of WCMPMCNT 1 then WCMPIF bit will be set to 1 if WCMPIEN and WCMPEN bit is set then an ADCINT interrupt request is generated Software can use it to monitor the external analog input pin voltage transition 6 16 2 6 Int...

Page 434: ...generate ADC0IF interrupt when ADCMODE is set as 10b ADC_CTL 7 6 Figure 6 16 6 shows one time and simultaneous sample hold in S H0 and S H1 and then sequential conversion by the A D converter S H0 ADC0 ADC1 ADC0_TRG S H1 Ignore ADC0_TRG Figure 6 16 6 Simultaneous Simple Mode Conversion Timing Diagram 6 16 2 10Simultaneous Sequential 4R Mode In this mode the ADC in the Mini57 can be set to perform ...

Page 435: ...egister 1 0x0000_0000 ADC_CTL ADC_BA 0x20 R W ADC Control Register 0x0000_0000 ADC_TRGSOR ADC_BA 0x24 R W ADC Hardware Trigger Source Control Register 0x0000_0000 ADC_TRGDLY ADC_BA 0x28 R W ADC Trigger Delay Control Register 0x0000_0000 ADC_SMPCNT ADC_BA 0x2C R W ADC Sampling Time Counter Register 0x0000_0005 ADC_STATUS ADC_BA 0x30 R W ADC Status Register 0x0000_0000 ADC_WCMPCTL ADC_BA 0x34 R W AD...

Page 436: ...s set to 1 when A D conversion is completed and cleared by hardware after the ADC_DAT0 register is read 30 ADC1OV ADC1 over Run Flag 0 Data in ADC1DAT0 27 16 is recent conversion result 1 Data in ADC1DAT0 27 16 overwritten Note1 If converted data in ADC1DAT0 27 16 has not been read before the new conversion result is loaded to this register OV is set to 1 Note2 It is cleared by hardware after the ...

Page 437: ...nt conversion result 1 Data in ADC0DAT0 11 0 overwritten Note1 If converted data in ADC0DAT0 11 0 has not been read before the new conversion result is loaded to this register OV is set to 1 Note2 It is cleared by hardware after the ADC_DAT0 register is read 13 12 Reserved Reserved 11 0 ADC0DAT0 ADC0 Conversion Result This field contains conversion result of ADC ...

Page 438: ...ta in ADC1DAT1 27 16 overwritten Note1 If converted data in ADC1DAT1 27 16 has not been read before the new conversion result is loaded to this register OV is set to 1 Note2 It is cleared by hardware after the ADC_DAT1 register is read 29 28 Reserved Reserved 27 16 ADC1DAT1 ADC1 Conversion Result for FIFO1 This field contains conversion result of ADC 15 ADC0VALID ADC0 Valid Flag 0 Data in ADC0DAT1...

Page 439: ...Mini57 Apr 06 2017 Page 439 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 11 0 ADC0DAT1 ADC0 Conversion Result for FIFO1 This field contains conversion result of ADC ...

Page 440: ...HSEL 15 14 13 12 11 10 9 8 Reserved ADC1SWTRG ADC1HWTRG EN ADC1IEN Reserved 7 6 5 4 3 2 1 0 ADCMODE ADCSS3R Reserved ADC0SWTRG ADC0HWTRG EN ADC0IEN ADCEN Bits Description 31 Reserved Reserved 30 28 ADC1SEQSEL ADC1 Sequential Input Pin Selection Second Input 000 ADC1_CH0 001 ADC1_CH1 010 ADC1_CH2 011 ADC0_CH0 100 ADC0_CH4 101 PGA_ADC 110 Temp Sensor 111 VSS 27 Reserved Reserved 26 24 ADC1CHSEL ADC1...

Page 441: ...WM Timer ADC self 0 Hardware Trigger ADC Convertion Disabled 1 Hardware Trigger ADC Convertion Enabled 9 ADC1IEN ADC1 Interrupt Enable Bit 0 ADC1 interrupt function Disabled 1 ADC1 interrupt function Enabled Note A D conversion end interrupt request is generated if ADC1IEN bit is set to 1 7 6 ADCMODE A D Conversion Mode 00 Independent simple independent function and independent interrupt by themse...

Page 442: ...ally 2 ADC0HWTRGEN Hardware Trigger ADC Convertion Enable Enable or disable triggering of A D conversion by Hardware PWM Timer ADC self 0 Disabled 1 Enabled 1 ADC0IEN ADC0 Interrupt Enable 0 ADC0 interrupt function Disabled 1 ADC0 interrupt function Enabled Note A D conversion end interrupt request is generated if ADC0IEN bit is set to 1 0 ADCEN ADC Converter Enable 0 ADC Converter Disabled 1 ADC ...

Page 443: ...12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADC0STADCSEL ADC0PWMTRGSEL ADC0TRGSOR Bits Description 31 24 Reserved Reserved 23 22 ADC1STADCSEL ADC1 External Trigger Pin STADC Trigger Selection 00 Rising 01 Falling 10 Rising or Falling 11 Reserved 21 20 ADC1PWMTRGSE L PWM Trigger Selection for ADC1 00 EPWM Signal Falling 01 EPWM Counter Central 10 EPWM signal Rising 11 Period 19 16 ADC1TRGSOR ADC1 Trigger...

Page 444: ...tion 00 Rising 01 Falling 10 Rising or Falling 11 Reserved 5 4 ADC0PWMTRGSE L PWM Trigger Selection for ADC0 00 EPWM Signal Falling 01 EPWM Counter Central 10 EPWM signal Rising 11 Period 3 0 ADC0TRGSOR ADC0 Trigger Source 0000 STADC 0001 PWM0 0010 PWM1 0011 PWM2 0100 PWM3 0101 PWM4 0110 PWM5 0111 TMR0 1000 TMR1 1001 TMR2 1010 ADC0IF 1011 ADC1IF 1100 1111 Reserved ...

Page 445: ... 19 18 17 16 ADC1DELAY 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADC0DELAY Bits Description 31 24 Reserved Reserved 23 16 ADC1DELAY ADC1 Trigger Delay Timer Setting this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming x 0 1 Delay time is 4 ADC1DELAY system clock 15 8 Reserved Reserved 7 0 ADC0DELAY ADC0 Trigger Delay Timer Setting this field will delay ADC start ...

Page 446: ...served 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved ADCSMPCNT Bits Description 31 4 Reserved Reserved 3 0 ADCSMPCNT ADC Sampling Counter ADC sampling counters are 6 ADC clock is suggestion 0 1 ADC Clock 1 2 ADC Clock 2 3 ADC Clock 3 4 ADC Clock 4 5 ADC Clock 5 6 ADC Clock 6 7 ADC Clock 7 8 ADC Clock 8 16 ADC Clock 9 32 ADC Clock 10 64 ADC Clock 11 128 AD...

Page 447: ...ting 18 MIDFG Window Comparator Middle Bound Flag When A D conversion result is between High Bound WCMPHIGHDAT and Low Bound WCMPLOWDAT this bit is set to 1 Then it is cleared by writing 1 to ifself 0 Conversion result in ADC_DAT1 isn t between High Bound WCMPHIGHDAT and Low Bound WCMPLOWDAT 1 Conversion result in ADC_DAT1 is between High Bound WCMPHIGHDAT and Low Bound WCMPLOWDAT 17 LOWFG Window ...

Page 448: ...n End Flag A status flag that indicates the end of A D conversion ADF is set to 1 When A D conversion ends This flag can be cleared by writing 1 to itself 7 4 ADC0CH Current Conversion Channel This filed reflects the current conversion channel when ADC0BUSY 1 When ADC0BUSY 0 it shows the number of the next converted channel It is read only 3 ADC0BUSY BUSY IDLE 0 A D converter is in idle state 1 A ...

Page 449: ...ease 1 When the internal counter reaches the value to WCMPMCNT the CMPIF bit will be set NOTE If WCMPMCNT 0 the counter would do 16 times 7 WFLAGCTL Window Comparator Flag Control When the A D conversion result matches the compare condition 0 Auto update 1 none 6 WCMPHIGHEN Window Comparator High Flag Enable Bit Set A D conversion result higher than compare condition High bound range 0 Window Comp...

Page 450: ...CHNICAL REFERENCE MANUAL Bits Description 1 WCMPIEN Window Comparator Interrupt Enable Bit 0 Window Comparator Interrupt Disabled 1 Window Comparator Interrupt Enabled 0 WCMPEN Window Comparator Enable Bit 0 Window Comparator Disabled 1 Window Comparator Enabled ...

Page 451: ...PD AT ADC_BA 0x38 R W ADC Window Comparator Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved WCMPHIGHDAT 23 22 21 20 19 18 17 16 WCMPHIGHDAT 15 14 13 12 11 10 9 8 Reserved WCMPLOWDAT 7 6 5 4 3 2 1 0 WCMPLOWDAT Bits Description 31 28 Reserved Reserved 27 16 WCMPHIGHDAT Window Comparator High Bound Data 15 12 Reserved Reserved 11 0 WCMPLOWDAT Window Comparator Low Bound Data ...

Page 452: ... number of different configurations The comparator output is logic 1 when positive input greater than negative input otherwise the output is 0 Each comparator can be configured to generate interrupt when the comparator output value changes 6 17 2 Features Analog input voltage range 0 VDD Supports Hysteresis function Optional internal reference voltage source for each comparator negative input ...

Page 453: ...CMP_PHASE to PWM Phase Change PBRKSEL ACMPn_CTL 6 ACMPEN ACMPn_CTL 0 EDGESEL ACMPn_CTL 5 4 ACMP_STATUS 5 4 ACMP_STATUS 1 0 00 01 10 0 1 0 1 PGA_CMP Figure 6 17 1 Analog Comparator Block Diagram 6 17 4 Basic Configuration The ACMP pin functions are configured in SYS_GPB_MFP SYS_GPC_MFP and SYS_GPD_MFP registers It is recommended to disable the digital input path of the analog input pins to avoid th...

Page 454: ...CMPF1 ACMPIE ACMP1_CTL 1 DLYTRGF0 DLYTRGIE ACMP0_CTL 13 ACMP_INT DLYTRGF1 DLYTRGIE ACMP1_CTL 13 Figure 6 17 2 Analog Comparator Controller Interrupt Sources 6 17 5 2 Hysteresis Function The analog comparator provides hysteresis function to make the comparator output transition more stable If comparator output is 0 it will not change to 1 until the positive input voltage exceeds the negative input ...

Page 455: ...ference voltage to ACMP by setting CPNSEL ACMP_CTL 25 24 6 17 6 2 Features User selectable references voltage by setting CRVCTL ACMP_ VREF 3 0 Automatic disable resisters ladder for reducing power consumption when setting CPNSEL ACMP_CTL 25 24 01b selecting Band gap source voltage The block diagram of the CRV module is shown in Figure 6 17 4 AVSS 4R R R R R 4R CRVCTL ACMP_VREF 3 0 1111 1110 1101 0...

Page 456: ...A 0x400D_0000 ACMP_CTL0 ACMP_BA 0x00 R W Analog Comparator0 Control Register 0x0000_0000 ACMP_CTL1 ACMP_BA 0x04 R W Analog Comparator1 Control Register 0x0000_0000 ACMP_STATUS ACMP_BA 0x08 R W Analog Comparator Status Register 0x0000_0000 ACMP_VREF ACMP_BA 0x0C R W Analog Comparator Reference Voltage Control Register 0x0000_0000 ACMP_TRGDLY ACMP_BA 0x10 R W Analog Comparator Delay Trigger Mode Dle...

Page 457: ...ved 15 14 13 12 11 10 9 8 Reserved DLYTRGIE DLYTRGEN DLYTRGSOR DLYTRGSEL 7 6 5 4 3 2 1 0 Reserved PBRKSEL EDGESEL ACMPHYSEN ACMPIE ACMPEN Bits Description 31 PRESET Comparator Result Preset Value 0 0 for preset value 1 1 for preset value 30 28 CPPSEL Comparator Positive Input Select 000 ACMP0_P0 PB 0 001 ACMP0_P1 PB 1 010 ACMP0_P2 PB 2 011 ACMP0_P3 PC 1 100 PGA_CMP 27 26 Reserved Reserved 25 24 CP...

Page 458: ... Analog Comparator Delay Trigger Mode Enabled 11 10 DLYTRGSOR Analog Comparator Delay Trigger Mode Trigger Source Selection 00 PWM0 01 PWM2 10 PWM4 11 Reserved 9 8 DLYTRGSEL Analog Comparator Delay Trigger Mode Trigger Level Selection 00 Analog Comparator Delay Trigger Mode Trigger Disabled 01 Rising 10 Falling 11 Rising Falling 7 Reserved Reserved 6 PBRKSEL ACMP to EPWM Brake Selection 0 ACMP Res...

Page 459: ...terrupt function Disabled 1 ACMP interrupt function Enabled Note1 Interrupt is generated if ACMPIE bit is set to 1 after ACMP conversion is finished Note2 ACMP interrupt will wake CPU up in Power down mode 0 ACMPEN Comparator Enable Bit 0 Comparator Disabled 1 Comparator Enabled Note Comparator output needs to wait 2 us stable time after ACMPEN is set ...

Page 460: ... 1 0 Reserved PBRKSEL EDGESEL ACMPHYSEN ACMPIE ACMPEN Bits Description 31 PRESET Comparator Result Preset Value 0 0 for preset value 1 1 for preset value 30 28 CPPSEL Comparator Positive Input Selection 000 ACMP1_P0 PC 0 001 ACMP1_P1 PC 1 010 ACMP1_P2 PD 1 011 PGA_CMP 27 26 Reserved Reserved 25 24 CPNSEL Comparator Negative Input Selection 00 ACMP1_N PB 3 01 Band_Gap 10 CRV 11 Reserved 23 NFDIS Di...

Page 461: ...gger Level Selection 00 Analog Comparator Delay Trigger Mode Trigger Disabled 01 Rising 10 Falling 11 Rising Falling 7 Reserved Reserved 6 PBRKSEL ACMP to EPWM Brake Selection 0 ACMP Result direct output 1 ACMP Delay Trigger Result output 5 4 EDGESEL Interrupt Flag Trigger Edge Detection 00 Interrupt Flag Trigger Edge Detection Disable 01 Rising 10 Falling 11 Rising Falling 3 2 ACMPHYSEN Comparato...

Page 462: ...462 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 0 ACMPEN Comparator Enable Bit 0 Comparator Disabled 1 Comparator Enabled Note Comparator output needs to wait 2 us stable time after ACMPEN is set ...

Page 463: ...ized to the APB clock to allow reading by software Cleared when the comparator is disabled DLYTRGEN 0 5 DLYTRGF1 Comparator1 Flag This bit is set by hardware whenever the comparator1 output changes state This will cause an interrupt if DLYTRGIEN set Note Write 1 to clear this bit to 0 4 DLYTRGF0 Comparator0 Flag This bit is set by hardware whenever the comparator0 output changes state This will ca...

Page 464: ...1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL Bits Description 0 ACMPF0 Comparator0 Flag This bit is set by hardware whenever the comparator0 output changes state This will cause an interrupt if ACMPIE set Note Write 1 to clear this bit to 0 ...

Page 465: ... R W Description Reset Value ACMP_VREF ACMP_BA 0x0C R W Analog Comparator Reference Voltage Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CRVCTL Bits Description 31 4 Reserved Reserved 3 0 CRVCTL Comparator Reference Voltage Setting CRVS AVDD x 1 6 CRV 3 0 24 ...

Page 466: ...ter Offset R W Description Reset Value ACMP_TRGDLY ACMP_BA 0x10 R W Analog Comparator Delay Trigger Mode Dleay Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved DELAY 7 6 5 4 3 2 1 0 DELAY Bits Description 31 9 Reserved Reserved 8 0 DELAY Analog Comparator Delay Trigger Mode Dleay cycle ...

Page 467: ...in to 1 2 3 5 7 9 11 and 13 Note The analog input port pins must be configured as input type before the PGA function is enabled 1 1 4 Features Supports analog input voltage range 0 VDD Supports programmable gain 1 2 3 5 7 9 11 13 Supports PGA output as input of ADC and ACMP 1 1 5 Block Diagram PGA_I PGA_O pin PGA_ADC to ADC PGA_CMP to ACMP PGA SYS_PC 3_MFP 6 PGAOUTEN PGAEN GAIN 111 Figure 6 18 1 O...

Page 468: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved GAIN Reserved PGAEN Bits Description 31 7 Reserved Reserved 6 4 GAIN PGA Gain Selection 000 2 001 3 010 5 011 7 100 9 101 11 110 13 111 1 See Note 3 1 Reserved Reserved 0 PGAEN Programmable Gain Amplifier Enable Bit 0 Programmable Gain Amplifier Disabled 1 Programmable Gain Amplifier Enabled Note The PGA output needs to w...

Page 469: ...AT ICE_CLK SWD Interface 1uF VDD VSS I2 C Device CLK DIO I2Cx_SDA I2Cx_SCL 4 7K VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI LDO RS232 Transceiver ROUT TIN RIN TOUT PC COM Port XT_IN 0 1uF DVCC 4 7K DVCC DVCC Note 1 For the SPI device the Mini57 chip supply voltage must be equal to SPI device working voltage For example when the SPI Flash working voltage is 3 3 V the Mini57...

Page 470: ...6 2017 Page 470 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 8 ELECTRICAL CHARACTERISTICS For information on the Mini57 series electrical characteristics please refer to NuMicro Mini57 Series Datasheet ...

Page 471: ...Mini57 Apr 06 2017 Page 471 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 9 PACKAGE DIMENSIONS 1 2 28 Pin TSSOP 4 4x9 7x1 0 mm ...

Page 472: ...Mini57 Apr 06 2017 Page 472 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 1 3 20 Pin TSSOP 4 4x6 5x0 9 mm ...

Page 473: ...Mini57 Apr 06 2017 Page 473 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 9 1 33 pin QFN33 4x4x0 8 mm ...

Page 474: ...Mini57 Apr 06 2017 Page 474 of 475 Rev 1 00 MINI57 SERIES TECHNICAL REFERENCE MANUAL 10 REVISION HISTORY Date Revision Description 2017 04 06 1 00 Preliminary version ...

Page 475: ...es but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed for vehicular use traffic signal instruments all types of safety devices and other applications intended to support or sustain life All Insecure Usage shall be made at customer s risk and in the event...

Reviews:

No comments

Brands by name

Popular brands

Load more brands