NEC NEC PD78081(A) User Manual Download Page 32

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CHAPTER 1 OUTLINE

1.6 78K/0 Series Development

The following shows the 78K/0 Series products development. Subseries names are shown inside frames.

Note

Under planning

100-pin

80-pin

64-pin

42/44-pin

100-pin

80-pin

100-pin

µPD780308Y

µPD78064Y

80-pin

78K/0
series

Control

FIP® driving

IEBus

supported

Low EMI noise version of the µPD78078

Timer is added to the µPD78054 and its external interface is enhanced.

ROM-less versions of the µPD78078

Serial I/O of the µPD78078 is enhanced and only selected functions are provided.

Serial I/O-enhanced versions of the µPD78054; Low EMI noise version

Low EMI noise version of the µPD78054

UART and D/A converter are added to the µPD78014 and I/O is enhanced.

A/D-enhanced version of the µPD780024

Serial I/O-enhanced versions of the µPD78018F; Low EMI noise version

Low EMI noise version of the µPD78018F

Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities available.

A/D converter and 16-bit timer are added to the µPD78002.

A/D converter is added to the µPD78002.

Basic subseries for control applications

On-chip UART, and operable at low voltage (1.8 V).

I/O and FIP C/D of the µPD78044F are enhanced. Total display outputs : 53 pins

I/O and FIP C/D of the µPD78044H are enhanced. Total display outputs : 48 pins

N-ch open-drain I/O is added to the µPD78044F. Total display outputs : 34 pins

Basic subseries for FIP driving. Total display outputs: 34 pins

SIO of the µPD78064 is enhanced, and ROM and RAM are expanded.

Low EMI noise version of the µPD78064

Basic subseries for driving LCDs and with on-chip UART.

IEBus controller is added to the µPD78054.

Mass-produced products

Products under development

Y Subseries supports the I

C bus specifications.

µPD78098

64-pin

PWM output, LV digital code decoder and Hsync counter are incorporated.

µPD78P0914

µPD780308

64-pin

Inverter control

A/D-enhanced version of the µPD780924

On-chip inverter control circuit and UART incorporated; Low EMI noise version

µPD780964

µPD780924

LCD driving

µPD78064B

µPD78064

µPD780208

µPD780228

µPD78044H

µPD78044F

µPD78075B

µPD78078

µPD78070A

µPD780018

Note

µPD780058

µPD78058F

µPD78054

µPD780034

µPD780024

µPD78014H

µPD78018F

µPD78014

µPD780001

µPD78002

µPD78083

µPD78075BY

µPD78078Y

µPD78070AY

µPD780018Y

Note

µPD780058Y

Note

µPD78058FY

µPD78054Y

µPD780034Y

µPD780024Y

µPD78018FY

µPD78014Y

µPD78002Y

Summary of Contents for NEC PD78081(A)

Page 1: ...81 A PD78082 PD78082 A PD78P083 PD78P083 A PD78P081 A2 PD78083 SUBSERIES 8 BIT SINGLE CHIP MICROCONTROLLER Document No U12176EJ2V0UM00 2nd edition O D No IEU 886 Date Published May 1997 N Printed in J...

Page 2: ...CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CM...

Page 3: ...k of Open Software Foundation Inc TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by t...

Page 4: ...e containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed ba...

Page 5: ...445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860...

Page 6: ...er Mode Register in Figure10 1 A D Converter Block Diagram p 122 193 10 3 1 A D converter mode register ADM 13 1 1 Standby function and Cautions have been added p 137 Figure 11 1 Serial Interface Chan...

Page 7: ...d This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers For those who will be using this as a manual for the PD78081 A 78082 A 78...

Page 8: ...Caution Information requiring particular attention Remarks Additional explanatory material Numeral representations Binary or B Decimal Hexadecimal H Examples of use in this manual are prepared for St...

Page 9: ...5E PD78P083 Data Sheet U11006J U11006E PD78081 A 78082 A 78081 A2 Data Sheet In preparation To be prepared PD78P083 A Data Sheet U12175J U12175E PD78083 Subseries Special Function Register Table IEM 5...

Page 10: ...S DOS Base EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Base EEU 5008 U10540E IE 78000 R EEU 810 U11376E IE 78000 R A U10057J U10057E IE 78000 R BK EEU 867 EEU 1427 IE 78078 R EM U10775J U...

Page 11: ...y Inference Development Support System Fuzzy Inference Debugger EEU 921 EEU 1458 Other Documents Document name Document No Japanese English IC PACKAGE MANUAL C10943X Semiconductor Device Mounting Tech...

Page 12: ...3 Port 0 17 2 2 2 P10 to P17 Port 1 17 2 2 3 P30 to P37 Port 3 18 2 2 4 P50 to P57 Port 5 18 2 2 5 P70 to P72 Port 7 19 2 2 6 P100 to P101 Port 10 19 2 2 7 AVREF 20 2 2 8 AVDD 20 2 2 9 AVSS 20 2 2 10...

Page 13: ...ort 3 58 4 2 4 Port 5 59 4 2 5 Port 7 60 4 2 6 Port 10 62 4 3 Port Function Control Registers 63 4 4 Port Function Operations 67 4 4 1 Writing to input output port 67 4 4 2 Reading from input output p...

Page 14: ...ctions 115 9 2 Buzzer Output Control Circuit Configuration 115 9 3 Buzzer Output Function Control Registers 116 CHAPTER 10 A D CONVERTER 119 10 1 A D Converter Functions 119 10 2 A D Converter Configu...

Page 15: ...Register 206 15 2 PROM Programming 207 15 2 1 Operating modes 207 15 2 2 PROM write procedure 209 15 2 3 PROM reading procedure 213 15 3 Erasure Procedure PD78P083DU Only 214 15 4 Opaque Film Masking...

Page 16: ...rcuit Emulators to 78K 0 Series In Circuit Emulator 240 APPENDIX B EMBEDDED SOFTWARE 243 B 1 Real time OS 244 B 2 Fuzzy Inference Development Support System 245 APPENDIX C REGISTER INDEX 247 C 1 Regis...

Page 17: ...61 4 9 P100 to P101 Block Diagram 62 4 10 Port Mode Register Format 65 4 11 Pull Up Resistor Option Register Format 66 5 1 Block Diagram of Clock Generator 70 5 2 Processor Clock Control Register For...

Page 18: ...111 8 2 Clock Output Control Circuit Block Diagram 112 8 3 Timer Clock Select Register 0 Format 113 8 4 Port Mode Register 3 Format 114 9 1 Buzzer Output Control Circuit Block Diagram 115 9 2 Timer C...

Page 19: ...Word Configuration 180 12 8 Flowchart from Non Maskable Interrupt Request Generation to Acknowledgment 182 12 9 Non Maskable Interrupt Request Acknowledge Timing 182 12 10 Non Maskable Interrupt Reque...

Page 20: ...ix FIGURE 4 4 Fig No Title Page 15 6 PROM Read Timing 213 A 1 Development Tool Configuration 232 A 2 EV 9200G 44 Drawing For Reference Only 241 A 3 EV 9200G 44 Footprint For Reference Only 242...

Page 21: ...5 and 6 Configurations 82 6 5 8 Bit Timer Event Counters 5 and 6 Interval Times 92 6 6 8 Bit Timer Event Counters 5 and 6 Square Wave Output Ranges 95 7 1 Watchdog Timer Overrun Detection Times 103 7...

Page 22: ...ter HALT Mode Release 197 13 3 STOP Mode Operating Status 198 13 4 Operation after STOP Mode Release 200 14 1 Hardware Status after Reset 1 2 203 14 1 Hardware Status after Reset 2 2 204 15 1 Differen...

Page 23: ...xii MEMO...

Page 24: ...ation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions 33 I O ports 8 bit resolution A D converter 8 channels Serial interface...

Page 25: ...k ROM PD78082GB 3B4 44 pin plastic QFP 10 10 mm Mask ROM PD78082GB 3BS MTX 44 pin plastic QFP 10 10 mm Mask ROM PD78P083CU 42 pin plastic shrink DIP 600 mil One Time PROM PD78P083DU 42 pin ceramic shr...

Page 26: ...ot applicable PD78P083GB 3B4 44 pin plastic QFP 10 10 mm Standard PD78P083GB 3BS MTX 44 pin plastic QFP 10 10 mm Standard PD78081GB A 3B4 44 pin plastic QFP 10 10 mm Special PD78082GB A 3B4 44 pin pla...

Page 27: ...TI6 TO6 P70 RXD SI2 P71 TXD SO2 P72 ASCK SCK2 P17 ANI7 P16 ANI6 P15 ANI5 P14 ANI4 P13 ANI3 P12 ANI2 P11 ANI1 P10 ANI0 AVSS AVREF 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P55 P56...

Page 28: ...S pin to VSS 4 Connect NC pin to VSS for noise protection It can be left open Remark Pin connection in parenthesis is intended for the PD78P083 1 2 3 4 5 6 7 8 9 10 11 P03 INTP3 P02 INTP2 P01 INTP1 P0...

Page 29: ...Data AVSS Analog Ground SCK2 Serial Clock BUZ Buzzer Clock SI2 Serial Input IC Internally Connected SO2 Serial Output INTP1 to INTP3 Interrupt from Peripherals TI5 TI6 Timer Input NC Non connection TO...

Page 30: ...dually connect to VSS via a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open Do not connect anything 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VSS A4 A3 A...

Page 31: ...r Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 44 pin plastic QFP 10 10 mm PD78P083GB 3B4 78P083GB 3BS MTX PD78P083GB A 3B4 78P083GB A 3BS MTXNote 1 2...

Page 32: ...D converter is added to the PD78002 Basic subseries for control applications On chip UART and operable at low voltage 1 8 V I O and FIP C D of the PD78044F are enhanced Total display outputs 53 pins I...

Page 33: ...24 8 ch division 3 wire 1 ch PD78014H 2 ch 53 PD78018F 8K to 60K PD78014 8K to 32K 2 7 V PD780001 8K 1 ch 39 PD78002 8K to 16K 1 ch 53 Available PD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter PD780964...

Page 34: ...SO2 TXD P71 SCK2 ASCK P72 ANI0 P10 ANI7 P17 AVDD AVSS AVREF INTP1 P01 INTP3 P03 BUZ P36 PCL P35 PORT 0 PORT 1 PORT 3 PORT 5 PORT 7 PORT 10 SYSTEM CONTROL 8 bit TIMER EVENT COUNTER 5 BUZZER OUTPUT INT...

Page 35: ...8 bit resolution 8 channels Serial interface 3 wire serial I O UART mode selectable 1 channel Timer 8 bit timer event counter 2 channels Watchdog timer 1 channel Timer output 2 pins 8 bit PWM output...

Page 36: ...081 78082 and 78P083 the PD78081 A 78082 A and 78P083 A and the PD78081 A2 Part Number PD78081 PD78081 A PD78081 A2 PD78082 PD78082 A Item PD78P083 PD78P083 A Quality grade Standard Special Supply vol...

Page 37: ...14 CHAPTER 1 OUTLINE MEMO...

Page 38: ...ort it is possible to connect a pull up resistor by software Note P30 P34 Input output Port 3 Input P35 8 bit input output port PCL P36 Input output is specifiable bit wise BUZ P37 When used as the in...

Page 39: ...I0 ANI7 Input A D converter analog input Input P10 P17 AVREF Input A D converter reference voltage input AVDD A D converter analog power supply Connected to VDD AVSS A D converter ground potential Con...

Page 40: ...function as external interrupt request input pins which are capable of specifying the valid edges rising edge falling edge and both rising and falling edges 2 2 2 P10 to P17 Port 1 These are 8 bit in...

Page 41: ...3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as clock output and buzzer output...

Page 42: ...erface serial data input output pins d ASCK Asynchronous serial interface serial clock input pin Caution When this port is used as a serial interface the I O and output latches must be set according t...

Page 43: ...r Always use the same voltage as that of the VSS pin even when A D converter is not used 2 2 10 RESET This is a low level active system reset input pin 2 2 11 X1 and X2 Crystal resonator connect pins...

Page 44: ...le wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC...

Page 45: ...A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P100 TI5 TO5 8 A P101 TI6 TO6 RESET 2 Input AVREF Connect to VSS AVDD Connect to VDD AVSS Connect to VSS VPP PD78P083 Connect directly to VSS NC 44 pin plastic QFP...

Page 46: ...ble output disable data VDD P ch N ch Type 2 Type 5 A Schmitt Triggered Input with Hysteresis Characteristics Type 11 Type 8 A pull up enable VDD P ch IN OUT output disable data VDD P ch N ch pull up...

Page 47: ...24 CHAPTER 2 PIN FUNCTION MEMO...

Page 48: ...General Registers 32 8 bits Internal ROM 8192 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 256 8 bits Spe...

Page 49: ...16384 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 384 8 bits Special Function Registers SFRs 256 8 bits F...

Page 50: ...24576 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High speed RAM 512 8 bits Special Function Registers SFRs 256 8 bits...

Page 51: ...e RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses a...

Page 52: ...he instruction to be executed next or the address of a register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is a...

Page 53: ...ts Unusable Internal High speed RAM 256 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Base...

Page 54: ...its Unusable Internal High speed RAM 384 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Bas...

Page 55: ...bits Unusable Internal High speed RAM 512 8 bits Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Ba...

Page 56: ...cally incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector...

Page 57: ...of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result...

Page 58: ...k pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area FE00H FEFFH for the PD78081 FD80H FEFFH for the PD78082 and FD00H FEFFH...

Page 59: ...t 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms o...

Page 60: ...nipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describ...

Page 61: ...6 R FF56H Timer clock select register 6 TCL6 R W FF57H 8 bit timer mode control register 6 TMC6 FF70H Asynchronous serial interface mode register ASIM FF71H Asynchronous serial interface status regist...

Page 62: ...gister IMS Note FFF2H Oscillation mode selection register OSMS W 00H FFF3H Pull up resistor option register H PUOH R W FFF7H Pull up resistor option register L PUOL FFF9H Watchdog timer mode register...

Page 63: ...ormation is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 USER S MANUAL Instruction IEU 1372 3 3 1 Relative addressing Function The value obtained b...

Page 64: ...dr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory space The CALLF addr11 instruction branches to an area of addresses 0800H through...

Page 65: ...the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresse...

Page 66: ...0 PC 8 7 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when...

Page 67: ...be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numer...

Page 68: ...operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX B...

Page 69: ...by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1...

Page 70: ...FF00H through FF1FH to which short direct addressing is applied is a part of the entire SFR area To this area ports frequently accessed by the program and the compare registers and capture registers...

Page 71: ...addr offset Description example MOV 0FE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immedia...

Page 72: ...d This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier De...

Page 73: ...ister bank select flags RBS0 and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Des...

Page 74: ...HL register pair to be accessed is in the register bank specified by the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A...

Page 75: ...r to 16 bits as a positive number A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example...

Page 76: ...rts Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also se...

Page 77: ...cifiable bit wise BUZ P37 When used as the input port it is possible to connect a pull up resistor by software P50 P57 Input output Port 5 8 bit input output port A maximum of 7 out of 8 ports can dri...

Page 78: ...e output mode in 1 bit units with the port mode register 0 PM0 P00 pin is input only port When P01 to P03 pins are used as input ports an on chip pull up resistor can be used to them in 3 bit units wi...

Page 79: ...4 3 P01 to P03 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P00 RD Internal bus P ch WRPM WRPORT RD WRPUO VDD P01 INTP1 P03 INT...

Page 80: ...up resistor option register L PUOL Dual functions include an A D converter analog input RESET input sets port 1 to input mode Figure 4 4 shows a block diagram of port 1 Caution A pull up resistor can...

Page 81: ...to them in 8 bit units with a pull up resistor option register L PUOL Dual functions include clock output and buzzer output RESET input sets port 3 to input mode Figure 4 5 shows a block diagram of p...

Page 82: ...resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL A maximum of 7 out of 8 ports can drive LEDs directly RESET input sets port 5 to input mode Figure 4 6 shows...

Page 83: ...nterface channel 2 data input output and clock input output RESET input sets the input mode Port 7 block diagrams are shown in Figures 4 7 and 4 8 Caution When used as a serial interface set the input...

Page 84: ...ock Diagram PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO7 Output Latch P71 and P72 PM71 PM72 Inter...

Page 85: ...t by means of pull up resistor option register H PUOH These pins are dual function pins and serve as timer inputs outputs RESET input sets the input mode The port 10 block diagram is shown in Figure 4...

Page 86: ...10 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output...

Page 87: ...ut 1 TO6 Output 0 0 Dual functions Name P PM Input Output Pin Name Note If a read instruction is performed to these pins when they are used as an alternate function read data is to be undefined Cautio...

Page 88: ...6 PM15 PM14 PM13 PM12 PM11 PM10 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM7 FF27H FFH R W 1 1 1 1 1 PM72 PM71 PM70 1 1 PM10 PMmn Pmn Pin Input Output Mode Selec...

Page 89: ...L are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 P00 pin does not incorporate a pull up resistor 2 When port 1 is used as dual function...

Page 90: ...atch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction T...

Page 91: ...68 CHAPTER 4 PORT FUNCTIONS MEMO...

Page 92: ...le Main system clock oscillator This circuit oscillates at frequencies of 1 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction 5 2 Clock Generator Configuration The clock generato...

Page 93: ...Clock Oscillator X2 X1 STOP PCC2 PCC1 Internal Bus Standby Control Circuit 2 fXX 2 2 fXX 2 3 fXX 2 4 fXX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register fXX CPU Cl...

Page 94: ...r Format Caution Set 0 to the bits 3 to 7 Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillator frequency 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Fig...

Page 95: ...rmat Cautions 1 Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts As shown in Figure 5 4 below writing data including same...

Page 96: ...clock Cautions 1 Do not execute the STOP instruction if an external clock is used This is because the X2 pin is connected to VDD via a pull up register 2 When using a main system clock oscillator car...

Page 97: ...its b Signal conductors intersect is too long with each other c Changing high current is too near a d Current flows through the grounding line signal conductor of the ocsillator potential at points A...

Page 98: ...5 CLOCK GENERATOR Figure 5 6 Examples of Oscillator with Bad Connection 2 2 c Signals are fetched 5 4 2 Scaler The scaler divides the main system clock oscillator output fXX and generates various cloc...

Page 99: ...tion register OSMS a Upon generation of RESET signal the lowest speed mode of the main system clock 12 8 s when operated at 5 0 MHz is selected PCC 04H OSMS 00H Main system clock oscillation stops whi...

Page 100: ...or CPU Clock Switchover 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 PCC0 PCC2 PCC1 0 0 0 0 1 1 0 0 0 1 1 1 8 instructions 2 instructions 4 instructions 4 instructions 2 instructions 8 instructions 4 instructions 4...

Page 101: ...ation stabilization time 217 fX is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 12 8 s when operated at 5 0 MHz 2 After the l...

Page 102: ...kable interrupt requests and RESET at the preset time intervals See CHAPTER 7 WATCHDOG TIMER 3 Clock output control circuit This circuit supplies a clock obtained by dividing the main system clock to...

Page 103: ...6 s 204 8 s 409 6 s 800 ns 1 6 s 23 1 fX 24 1 fX 211 1 fX 212 1 fX 23 1 fX 24 1 fX 1 6 s 3 2 s 409 6 s 819 2 s 1 6 s 3 2 s 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 s 6 4 s 819 2 s 1 64 m...

Page 104: ...6 s 3 2 s 409 6 s 819 2 s 1 6 s 3 2 s 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 s 6 4 s 819 2 s 1 64 ms 3 2 s 6 4 s 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 s 12 8 s 1 64 ms 3...

Page 105: ...t timer mode control register 5 and 6 TMC5 TMC6 Port mode register 10 PM10 Figure 6 1 8 Bit Timer Event Counters 5 and 6 Block Diagram Note Refer to Figures 6 2 for details of configurations of 8 bit...

Page 106: ...Bit 0 of port mode register 10 PM10 PM101 Bit 1 of PM10 Remarks 1 The section in the broken line is an output control circuit 2 n 5 6 RESET LVRn LVSn TMCn1 TMCn6 OVFn INTTMn TCEn INTTMn R S Q PWM Out...

Page 107: ...ution When using the PWM mode please set the CRn0 value before setting TMCn n 5 6 to the PWM mode 2 8 bit timer registers 5 and 6 TM5 TM6 These are 8 bit registers to count count pulses TM5 and TM6 ar...

Page 108: ...0 Symbol TCL5 FF52H 00H R W Address After Reset R W TCL53 TCL52 TCL51 TCL50 0 0 0 0 TI5 falling edgeNote 0 0 0 1 TI5 rising edgeNote 0 1 1 0 0 1 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 0 fXX 2 2...

Page 109: ...heses when operated at fX 5 0 MHz 0 0 0 0 TCL63 TCL62 TCL61 TCL60 7 6 5 4 3 2 1 0 Symbol TCL6 TCL63 TCL62 TCL61 TCL60 0 0 0 0 TI6 falling edge Note 0 0 0 1 TI6 rising edge Note 0 1 0 0 0 1 0 1 0 1 1 0...

Page 110: ...ust be stopped before setting TMC5 2 If LVS5 and LVR5 are read after data are set they will be 0 3 Set 0 to the bits 4 and 5 TCE5 TMC56 0 0 LVS5 LVR5 TMC51 TOE5 7 6 5 4 3 2 1 0 Symbol TMC5 FF53H 00H R...

Page 111: ...t be stopped before setting TMC6 2 If LVS6 and LVR6 are read after data are set they will be 0 3 Set 0 to the bits 4 and 5 TCE6 TMC66 0 0 LVS6 LVR6 TMC61 TOE6 7 6 5 4 3 2 1 0 Symbol TMC6 FF57H 00H R W...

Page 112: ...01 and output latches of P100 and P101 to 0 PM10 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM10 to FFH Figure 6 7 Port Mode Register 10 Format Caution Set 1 to the...

Page 113: ...timer registers 5 and 6 TM5 and TM6 match the values set to CR50 and CR60 counting continues with the TM5 and TM6 values cleared to 0 and the interrupt request signals INTTM5 and INTTM6 are generated...

Page 114: ...INTTMn TCEn CRn0 TOn Interval Time Interval Time Interval Time Interrupt Request Acknowledge Interrupt Request Acknowledge N N N N Clear Count start Clear t 00 01 N 00 01 N 00 01 N Figure 6 9 Interval...

Page 115: ...X 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 s 6 4 s 819 2 s 1 64 ms 3 2 s 6 4 s 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 s 12 8 s 1 64 ms 3 28 ms 6 4 s 12 8 s 26 1 fX 27 1 fX 214 1 fX...

Page 116: ...the TM5 and TM6 counted values match the values of 8 bit compare registers 50 and 60 CR50 and CR60 TM5 and TM6 are cleared to 0 and the interrupt request signals INTTM5 and INTTM6 are generated Figure...

Page 117: ...5 TMC5 or bit 1 TMC61 and bit 0 TOE6 of 8 bit timer mode control register 6 TMC6 to 1 This enables a square wave of any selected frequency to be output Figure 6 12 8 Bit Timer Mode Control Register S...

Page 118: ...fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 s 6 4 s 819 2 s 1 64 ms 3 2 s 6 4 s 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 s 12 8 s 1 64 ms 3 28 ms 6 4 s 12 8 s 26 1 fX 27 1 fX 214 1 fX 215 1...

Page 119: ...r mode control register 6 TMC6 This PWM pulse has an 8 bit resolution The pulse can be converted into an analog voltage by integrating it with an external low pass filter LPF Count clock of 8 bit time...

Page 120: ...CRn0 00H active high setting Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 N N 1 N 2 N 3 00 OVFn M N N 00 Inactive Level CRn0 Changing M N Active Level Inactive Level...

Page 121: ...gure 6 16 PWM Output Operation Timings CRn0 FFH active high setting Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn FF FF FF 00 Inactive Level Inact...

Page 122: ...h setting Caution If CRn0 is changed during TMn operation the value changed is not reflected until TMn overflows Remark n 5 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn OVFn Active Level Inactiv...

Page 123: ...nchronously with the count pulse Figure 6 18 8 Bit Timer Registers 5 and 6 Start Timing Count Pulse TM5 TM6 Count Value 00H 01H 02H 03H 04H Timer Start TI5 TI6 Input CR50 CR60 TM5 TM6 Count Value TO5...

Page 124: ...isters 50 and 60 CR50 and CR60 are changed are smaller than those of 8 bit timer registers 5 and 6 TM5 and TM6 TM5 and TM6 continue counting overflow and then restart counting from 0 Thus if the value...

Page 125: ...102 CHAPTER 6 8 BIT TIMER EVENT COUNTERS 5 AND 6 MEMO...

Page 126: ...t request or RESET can be generated Table 7 1 Watchdog Timer Overrun Detection Times Runaway Detection Time MCS 1 MCS 0 211 1 fXX 211 1 fX 410 s 212 1 fX 819 s 212 1 fXX 212 1 fX 819 s 213 1 fX 1 64 m...

Page 127: ...3 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX...

Page 128: ...WDTM4 WDTM3 8 Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request INTWDT Non Maskable Interrupt Request RESET Control Circuit 7 2 Watchdog Timer Configuration The watchdog timer consists of...

Page 129: ...imer Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulat...

Page 130: ...1 TCL27 TCL26 TCL25 Buzzer output disable fXX 29 fXX 210 fXX 211 Setting prohibited MCS 1 fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz MCS 0 fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzzer Output...

Page 131: ...counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 7 3 Watchdog Timer Mode Register Format Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be...

Page 132: ...o 1 the watchdog timer can be cleared The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and t...

Page 133: ...RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the in...

Page 134: ...rocedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM3...

Page 135: ...trol Circuit Configuration Item Configuration Timer clock select register 0 TCL0 Port mode register 3 PM3 Figure 8 2 Clock Output Control Circuit Block Diagram Control register Internal Bus fXX fXX 2...

Page 136: ...XX fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 Setting prohibited MCS 1 fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz MCS 0 fX 2 2...

Page 137: ...e Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock outp...

Page 138: ...put from the BUZ P36 pin Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bi...

Page 139: ...e buzzer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memor...

Page 140: ...1 1 0 1 0 1 TCL27 TCL26 TCL25 Buzzer output disable fXX 29 fXX 210 fXX 211 Setting prohibited MCS 1 fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz MCS 0 fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzze...

Page 141: ...Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for buzzer out...

Page 142: ...log input from ANI0 to ANI7 and perform A D conversion As for A D conversion operations when the hardware is started up the A D conversion operation stops when A D conversion is completed and an inter...

Page 143: ...12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 Selector A D Converter Mode Register 3 Trigger Enable ES40 ES41Note 3 Sample Hold Circuit CS ADIS3 4 Internal Bus Internal Bus Edge Detector Control Cir...

Page 144: ...resistor string is connected within AVREF to AVSS and generates a voltage for comparison with the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to und...

Page 145: ...ter mode register ADM A D converter input select register ADIS External interrupt mode register 1 INTM1 1 A D converter mode register ADM This register sets the analog input channel for A D conversion...

Page 146: ...4 ADM3 3 2 1 0 FF80H Address ADM Symbol ADM2 ADM1 HSC 5 01H After Reset R W R W ADM3 0 0 0 0 1 1 1 1 ADM2 0 0 1 1 0 0 1 1 ADM1 0 1 0 1 0 1 0 1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 A...

Page 147: ...s set for analog input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option regist...

Page 148: ...pulation instruction RESET input sets INTM1 to 00H Figure 10 4 External Interrupt Mode Register 1 Format 0 7 0 6 0 0 4 0 3 2 1 0 FFEDH Address INTM1 Symbol 0 ES41 ES40 5 00H After Reset R W R W ES41 0...

Page 149: ...voltage tap and the analog input is compared by the voltage comparater If the analog input is larger than 1 2 AVREF the MSB of the SAR remains set If it is smaller than 1 2 AVREF the MSB is reset 7 N...

Page 150: ...10 5 A D Converter Basic Operation A D conversion operations are performed continuously until bit 7 CS of A D converter mode register ADM is reset 0 by software If a write to the ADM is performed duri...

Page 151: ...R 0 5 Where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of A D conversion result register ADCR Figure 10 6 shows the re...

Page 152: ...er mode register ADM are set to 1 the A D conversion standby state is set When the external trigger signal INTP3 is input the A D conversion starts on the voltage applied to the analog input pins spec...

Page 153: ...of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and t...

Page 154: ...ever there is no precision to the actual AVREF voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 10 9 Example of Method of Reduc...

Page 155: ...reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to couplin...

Page 156: ...ore the ADM rewrite and when ADIF is read immediately after the ADM rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D convers...

Page 157: ...134 CHAPTER 10 A D CONVERTER MEMO...

Page 158: ...the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 3 3 wire serial I O mode...

Page 159: ...11 1 Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode reg...

Page 160: ...2 CSCK INTSER SCK Output Control Circuit Baud Rate GeneratorNote fxx fxx 210 Internal Bus CSCK SCK INTST Baud Rate Generator Control Register Serial Operating Mode Register 2 PE FE OVE Transmission Co...

Page 161: ...Control Register 4 TXE CSIE2 5 Bit Counter Selector Selector Decoder 1 2 Selector Transmit Clock 1 2 Selector Receive Clock Match Match MDL0 MDL3 5 Bit Counter RXE Start Bit Detection Selector fxx fx...

Page 162: ...ve data Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 t...

Page 163: ...is used in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Figure 11 3 Serial Operating Mode Register 2 Format Cautions 1 Se...

Page 164: ...E 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No Parity Even parity PS0 0 1 0 parity always added in transm...

Page 165: ...s P70 SI2 RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM71 P71 PM72 P72 ASIM CSIM2 0 0 0 1 1 0 1 0 1 0 1 1 Note2 x Note2 0 1 1 0 1 0 x 1 x 1 MSB LSB External clock I...

Page 166: ...1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits b...

Page 167: ...fSCK 30 fSCKNote 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k 4 Baud rate generator control register B...

Page 168: ...1 1 fXX 26 fX 26 78 1 kHz fX 27 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above...

Page 169: ...0 to MDL3 0 k 14 Table 11 3 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Valu...

Page 170: ...m the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 11 4 Relation between ASCK Pin Input Fre...

Page 171: ...71 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Operation stop mode settings are performed using serial operating mode register 2 CSIM2 and the asynchrono...

Page 172: ...eset R W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled b Asynchronous s...

Page 173: ...UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard ba...

Page 174: ...ock from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM 0 1 Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt request generated i...

Page 175: ...detected PE 0 1 Parity Error Flag Parity error not generated Parity error generated When transmit data parity does not match c Asynchronous serial interface status register ASIS ASIS is set with a 1 b...

Page 176: ...K 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73...

Page 177: ...39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When...

Page 178: ...DL0 to MDL3 0 k 14 Table 11 5 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Va...

Page 179: ...m the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 11 6 Relation between ASCK Pin Input Fre...

Page 180: ...length for each data frame is carried out with asynchronous serial interface mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in...

Page 181: ...is counted If it is odd a parity error occurs ii Odd parity Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit dat...

Page 182: ...smission completion interrupt request INTST is generated Figure 11 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing a Stop bit length 1 b Stop bit length 2 Caution Rewr...

Page 183: ...s performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shif...

Page 184: ...he receive buffer register RXB or receiving the next data if there is an error in the next data the corresponding error flag is set Table 11 7 Receive Error Causes Receive Errors Cause Parity error Tr...

Page 185: ...during reception enable disable will differ depending on the timing the condition of the receive buffer register RXB and generation of the reception completed interrupt request INTSR The timing is di...

Page 186: ...rial operating mode register 2 CSIM2 the asynchro nous serial interface mode register ASIM and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with...

Page 187: ...0 1 Control of Reception Completion Interrupt in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not genera...

Page 188: ...SCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MD...

Page 189: ...39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When...

Page 190: ...DL0 to MDL3 to 1 1 1 1 The serial clock frequency becomes the same as the source clock frequency for the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with TPS0...

Page 191: ...transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit...

Page 192: ...transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or S...

Page 193: ...170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 MEMO...

Page 194: ...sk control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H PR1L Multiple high priorit...

Page 195: ...0018H B error generation 5 INTSR End of serial interface channel 2 001AH UART reception INTCSI2 End of serial interface channel 2 3 wire transfer 6 INTST End of serial interface channel 2 001CH UART...

Page 196: ...l Circuit Vector Table Address Generator Standby Release Signal Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Figure 12 1 Basic Configur...

Page 197: ...ector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 12 1 Basic Configuration of Interrupt Function 2 2 C External...

Page 198: ...listing of interrupt request flags interrupt mask flags and priority specify flags corresponding to interrupt request sources Table 12 2 Various Flags Corresponding to Interrupt Request Sources Inter...

Page 199: ...pon acknowledgment of an interrupt request or upon application of RESET input IF0L IF0H and IF1L are set with a 1 bit or 8 bit memory manipulation instruction If IF0L and IF0H are used as a 16 bit reg...

Page 200: ...MK0H MK1L The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MK0L MK0H and MK1L are set with a 1 bit or 8 bit memor...

Page 201: ...1L are set with a 1 bit or 8 bit memory manipulation instruction If PR0L and PR0H are used as a 16 bit register PR0 use a 16 bit memory manipulation instruction for the setting RESET input sets these...

Page 202: ...FFECH 00H After Reset R W R W 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 0 2 0 1 0 0 0 0 0 1 1 INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES21...

Page 203: ...the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The contents of PSW ar...

Page 204: ...quest generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI...

Page 205: ...Interval timer Start No Yes Yes No Yes No Yes No Yes No Figure 12 8 Flowchart from Non Maskable Interrupt Request Generation to Acknowledgment WDTM Watchdog timer mode register WDT Watchdog timer Figu...

Page 206: ...on maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction Execution NMI Request NMI Request Execute NMI Request Reserve Reserved NMI Request Processing Main Routine NMI...

Page 207: ...nterrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the requ...

Page 208: ...rve Interrupt request reserve Vectored interrupt servicing IE 1 Yes High priority Yes No Yes No No No Yes Interrupt Request Generation No Yes No Low Priority Yes Yes No Yes Yes No No Do any of the sim...

Page 209: ...imum Time Remark 1 clock fCPU CPU clock fCPU 1 fCPU 1 Instruction Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 8 Clocks 7 Clocks CPU Processing IF PR 1...

Page 210: ...ry during interrupt processing to set the IE flag 1 using the IE instruction and enable interrupts There are cases where multiple requests are not enabled even though interrupts are enabled However th...

Page 211: ...pt enable 2 D Multiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted or an interrup...

Page 212: ...t INTxx and a multiple interrupt is generated Before each interrupt request is acknowledged the EI instruction is always executed and interrupt request acknowledgment enabled Example 2 Example of when...

Page 213: ...interrupt is not generated because interrupts are not enabled Because interrupts are not enabled the EI instruction is not executed during processing of interrupt INTxx interrupt request INTyy is not...

Page 214: ...1 CY PSW bit SET1 PSW bit CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 EI DI Manipulate instructions for IF0L IF0H IF1L MK0L MK0H MK1L PR0L PR0H PR1...

Page 215: ...t Hold Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than instruction N 3 The operation of IF interrupt request is not affected by PR priority l...

Page 216: ...D 1 8 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent oper...

Page 217: ...OP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instr...

Page 218: ...The operating status in the HALT mode is described below Table 13 1 HALT Mode Operating Status Item HALT Mode Operating Status Clock generator Can be oscillated Supply to the CPU clock is stopped CPU...

Page 219: ...pt service is carried out If disabled the next address instruction is executed Figure 13 2 HALT Mode Clear upon Interrupt Generation Remarks 1 The broken line indicates the case when the interrupt req...

Page 220: ...de Release Release Source MK PR IE ISP Operation Maskable interrupt 0 0 0 Next address instruction execution request 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0...

Page 221: ...standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time...

Page 222: ...of sources a Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode If interrupt acknowledge is enabled after the lapse of oscillation stabilization time...

Page 223: ...time reset operation is carried out Figure 13 5 Release by STOP Mode RESET Input Remarks 1 fX main system clock oscillation frequency 2 Values in parentheses when operated at fX 5 0 MHz Table 13 4 Ope...

Page 224: ...to the status as shown in Table 14 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the r...

Page 225: ...Pin Delay Delay Hi Z X1 Normal Operation Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing X1 Normal Operation Watchdog Timer Overflow Internal Reset...

Page 226: ...y size switching register IMS Note3 Oscillation stabilization time select register OSTS 04H Timer clock selection register 0 TCL0 00H 8 bit timer event counter Timer register TM5 TM6 00H 5 and 6 Compa...

Page 227: ...flag register PR0L PR0H PR1L FFH External interrupt mode register INTM0 INTM1 00H Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware statuses bec...

Page 228: ...RAM capacity 512 bytes PD78081 256 bytes PD78082 384 bytes Internal ROM and internal high speed Enable Note Disable RAM capacity change by internal memory size switching register IMS IC pin Not avail...

Page 229: ...g register IMS By setting the IMS memory mapping can be made to match the memory mapping of the PD78081 and 78082 which have different internal memory IMS is set with an 8 bit memory manipulation inst...

Page 230: ...nd a low level signal is applied to the RESET pin the PD78P083 are set to the PROM programming mode This is one of the operating modes shown in Table 15 3 below according to the setting of the CE OE a...

Page 231: ...write and verify operations are executed X times X 10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program ver...

Page 232: ...V X 0 Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Latch X X 1 0 1 ms program pulse Verify 4 Bytes Pass Address N No Pass VDD 4 5 to 5 5 V VPP VDD All bytes verified End of...

Page 233: ...CHAPTER 15 PD78P083 Figure 15 3 Page Program Mode Timing Page Data Latch Page Program Program Verify Data Input Data Output A2 A14 A0 A1 D0 D7 VPP VDD VPP VDD 1 5 VDD VDD VIH CE PGM OE VIL VIH VIL VIH...

Page 234: ...Address G VDD 6 5 V VPP 12 5 V X 0 X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X...

Page 235: ...VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the VPP pin may have an adverse affect o...

Page 236: ...handled as shown in paragraph 2 PROM programming mode in section 1 5 Pin Configuration Top View 2 Supply 5 V to the VDD and VPP pins 3 Input the address of data to be read to pins A0 through A14 4 Rea...

Page 237: ...tents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window mask the window with opaque film after writing the EPROM 15 5 Screening of One Time P...

Page 238: ...PTER 16 INSTRUCTION SET This chapter describes each instruction set of the PD78083 subseries as list table For details of its operation and operation code refer to the separate document 78K 0 series U...

Page 239: ...nction names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 16 1 Operand Identifiers and Description Methods Identifier Description...

Page 240: ...rry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses...

Page 241: ...HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 XCH...

Page 242: ...2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A...

Page 243: ...Y A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r...

Page 244: ...4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A...

Page 245: ...after Addition Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit C...

Page 246: ...bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 SET1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr...

Page 247: ...SP 2 SP word 4 10 SP word MOVW SP AX 2 8 SP AX AX SP 2 8 AX SP addr16 3 6 PC addr16 BR addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8...

Page 248: ...it BTCLR PC PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdis...

Page 249: ...226 CHAPTER 16 INSTRUCTION SET 16 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ...

Page 250: ...D ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC A...

Page 251: ...L 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1...

Page 252: ...ions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ...

Page 253: ...230 CHAPTER 16 INSTRUCTION SET MEMO...

Page 254: ...VELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the PD78083 subseries Figure A 1 shows the configuration of the d...

Page 255: ...Assembler package C compiler package C library source file System simulator Screen debugger or integrated debugger Device file Host machine PC or EWS Interface adapter only when integrated debugger i...

Page 256: ...S DF78083 CC78K 0 L This is a function source program configurating object library included in CC78K 0 C compiler C Library Source File Necessary for changing object library included in CC78K 0 in ac...

Page 257: ...8P083CU 42 pin plastic shrink DIP 600 mil PROM programmer 42 pin ceramic shrink DIP with window 600 mil adapter PA 78P083GB 44 pin plastic QFP 10 10 mm A 2 2 Software PG 1500 controller This program c...

Page 258: ...r mode commercially available conversion adapter is necessary IE 78000 R This is in circuit emulator that debugs hardware and software when application system using In circuit emulator 78K 0 series is...

Page 259: ...ftware quality can be improved This simulator is used with optional device file DF78083 Part Number S SM78K0 Remark of the part number differs depending on the host machine and OS used Refer to the ta...

Page 260: ...tem performance analyzer This program is used in combination with optional device file DF78083 Part Number S ID78K0 Remark of the part number differs depending on the host machine and OS used Refer to...

Page 261: ...K0 or SD78K 0 Part Number S DF78083 Note This device file can be used for any of the RA78K 0 CC78K 0 SM78K0 ID78K0 SD78K 0 devices Remark of the part number differs depending on the host machine and O...

Page 262: ...Development Support System Windows Ver 3 0 to Ver 3 1 is necessary OS Version PC DOS Ver 5 02 to 6 3 J6 1 VNote to J6 3 VNote IBM DOS J5 02 VNote MS DOS Ver 5 0 to 6 22 5 0 VNote to 6 2 VNote Note Onl...

Page 263: ...R BK 78K I series IE 78130 R IE 78140 R 78K II series IE 78230 RNote IE 78230 R A IE 78240 RNote IE 78240 R A 78K III seires IE 78320 RNote IE 78327 R IE 78330 R IE 78350 R Note Maintenance product Ta...

Page 264: ...O L K R Q I H P J G EV 9200G 44 G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R 15 0 10 3 10 3 15 0 4 C 3 0 0 8 5 0 12 0 14 7 5 0 12 0 14 7 8 0 7 8 2 0 1 35 0 35 0 1 1 5 0 591 0 406 0...

Page 265: ...3 0 618 0 433 0 433 0 618 0 197 0 197 0 02 0 062 0 087 0 062 0 8 0 02 10 8 0 0 05 0 8 0 02 10 8 0 0 05 0 002 0 001 0 002 0 002 0 002 0 001 0 002 0 002 0 003 0 004 0 003 0 004 0 001 0 002 0 001 0 002 0...

Page 266: ...BEDDED SOFTWARE APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the PD78083 subseries to allow users to develop and maintain the application program fo...

Page 267: ...erimental production Mass production object Use for mass production S01 Source program Can be purchased only when object for mass production has been purchased Host Machine OS Medium 5A13 PC 9800 Seri...

Page 268: ...edge data converted by translator Fuzzy Inference Module Part Number S FI78K0 PC 9800 series IBM PC AT and their compatible machines FD78K0 This software supports evaluating and adjusting fuzzy knowle...

Page 269: ...246 APPENDIX B EMBEDDED SOFTWARE MEMO...

Page 270: ...3 E External interrupt mode register INTM0 179 External interrupt mode register INTM1 125 179 I IF0H Interrupt request flag register 0H 175 176 IF0L Interrupt request flag register 0L 175 176 IF1L Int...

Page 271: ...78 PSW Program status word 33 175 180 PUOH Pull up resistor option register H 66 PUOL Pull up resistor option register L 66 R RXB Receive buffer register 139 S SAR Successive approximation register 12...

Page 272: ...changed Figure 7 3 Watchdog Timer Mode Register Format notes and CHAPTER 7 WATCHDOG TIMER cautions have been added Description of 7 4 2 Interval timer operation has been changed Cautions with regard...

Page 273: ...EVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following Development Tools have been added IE 78000 R A IE 70000 98 IF B IE 70000 98 N IF IE 70000 PC IF B IE 78000 R SV3 SM78K0 ID78K0 A 4 OS for IB...

Page 274: ...erica NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasi...

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