107
CHAPTER 7 WATCHDOG TIMER
Figure 7-2. Timer Clock Select Register 2 Format
TCL27
7
TCL26
6
TCL25
0
4
0
3
2
1
0
FF42H
Address
TCL2
Symbol
TCL22 TCL21 TCL20
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TCL22 TCL21 TCL20
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
f
XX
/2
8
f
XX
/2
9
f
XX
/2
11
MCS=1
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
11
MCS=0
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
9
f
X
/2
10
f
X
/2
12
Watchdog Timer Count Clock Selection
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
TCL27 TCL26 TCL25
Buzzer output disable
f
XX
/2
9
f
XX
/2
10
f
XX
/2
11
Setting prohibited
MCS=1
f
X
/2
9
(9.8 kHz)
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
MCS=0
f
X
/2
10
(4.9 kHz)
f
X
/2
11
(2.4 kHz)
f
X
/2
12
(1.2 kHz)
Buzzer Output Frequency Selection
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(2.4 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
Caution
1. When rewriting TCL2 to other data, stop the timer operation beforehand.
2. Set 0 to the bits 3 and 4.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3.
×
: Don’t care
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X
= 5.0 MHz.
Summary of Contents for NEC PD78081(A)
Page 23: ...xii MEMO...
Page 37: ...14 CHAPTER 1 OUTLINE MEMO...
Page 47: ...24 CHAPTER 2 PIN FUNCTION MEMO...
Page 91: ...68 CHAPTER 4 PORT FUNCTIONS MEMO...
Page 125: ...102 CHAPTER 6 8 BIT TIMER EVENT COUNTERS 5 AND 6 MEMO...
Page 157: ...134 CHAPTER 10 A D CONVERTER MEMO...
Page 193: ...170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 MEMO...
Page 253: ...230 CHAPTER 16 INSTRUCTION SET MEMO...