221
CHAPTER 16 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
A, #byte
2
4
–
A
←
A
byte
×
saddr, #byte
3
6
8
(saddr)
←
(saddr) byte
×
A, r
Note 3
2
4
–
A
←
A
r
×
r, A
2
4
–
r
←
r A
×
A, saddr
2
4
5
A
←
A
(saddr)
×
A, !addr16
3
8
9
A
←
A
(addr16)
×
A, [HL]
1
4
5
A
←
A
(HL)
×
A, [HL + byte]
2
8
9
A
←
A
(HL + byte)
×
A, [HL + B]
2
8
9
A
←
A
(HL + B)
×
A, [HL + C]
2
8
9
A
←
A
(HL + C)
×
A, #byte
2
4
–
A
←
A
byte
×
saddr, #byte
3
6
8
(saddr)
←
(saddr)
byte
×
A, r
Note 3
2
4
–
A
←
A
r
×
r, A
2
4
–
r
←
r
A
×
A, saddr
2
4
5
A
←
A
(saddr)
×
A, !addr16
3
8
9
A
←
A
(addr16)
×
A, [HL]
1
4
5
A
←
A
(HL)
×
A, [HL + byte]
2
8
9
A
←
A
(HL + byte)
×
A, [HL + B]
2
8
9
A
←
A
(HL + B)
×
A, [HL + C]
2
8
9
A
←
A
(HL + C)
×
A, #byte
2
4
–
A – byte
× × ×
saddr, #byte
3
6
8
(saddr) – byte
× × ×
A, r
Note 3
2
4
–
A – r
× × ×
r, A
2
4
–
r – A
× × ×
A, saddr
2
4
5
A – (saddr)
× × ×
A, !addr16
3
8
9
A – (addr16)
× × ×
A, [HL]
1
4
5
A – (HL)
× × ×
A, [HL + byte]
2
8
9
A – (HL + byte)
× × ×
A, [HL + B]
2
8
9
A – (HL + B)
× × ×
A, [HL + C]
2
8
9
A – (HL + C)
× × ×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remark
One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
Mnemonic
Operands
Byte
Operation
Instruction
Group
OR
XOR
CMP
8-bit
operation
Summary of Contents for NEC PD78081(A)
Page 23: ...xii MEMO...
Page 37: ...14 CHAPTER 1 OUTLINE MEMO...
Page 47: ...24 CHAPTER 2 PIN FUNCTION MEMO...
Page 91: ...68 CHAPTER 4 PORT FUNCTIONS MEMO...
Page 125: ...102 CHAPTER 6 8 BIT TIMER EVENT COUNTERS 5 AND 6 MEMO...
Page 157: ...134 CHAPTER 10 A D CONVERTER MEMO...
Page 193: ...170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 MEMO...
Page 253: ...230 CHAPTER 16 INSTRUCTION SET MEMO...
