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CHAPTER 12 INTERRUPT FUNCTION
Main Processing
INTxx
Servicing
INTyy
Servicing
INTxx
(PR=0)
1 Instruction
Execution
IE=0
INTyy
(PR=1)
EI
IE=0
EI
RETI
RETI
Main Processing
EI
INTxx
(PR=1)
INTyy
(PR=0)
IE=0
EI
RETI
INTxx
Servicing
INTzz
(PR=0)
IE=0
EI
RETI
INTyy
Servicing
IE=0
RETI
INTzz
Servicing
Figure 12-14. Multiple Interrupt Example (1/2)
Example 1.
Example of when a multiple interrupt is generated twice.
Two interrupt requests, INTyy and INTzz, are acknowledged during processing of interrupt INTxx,
and a multiple interrupt is generated. Before each interrupt request is acknowledged, the EI
instruction is always executed and interrupt request acknowledgment enabled.
Example 2.
Example of when a multiple interrupt is not generated because of priority control.
Interrupt request INTyy, which has been generated during processing of interrupt INTxx, and which
has an interrupt priority that is lower than that of INTxx, is not acknowledged, and a multiple interrupt
is not generated. Interrupt request INTyy is reserved and is acknowledged after execution of one
main processing instructions.
PR = 0 : High priority level
PR = 1 : Low priority level
IE = 0
: Interrupt request acknowledge disabled
Summary of Contents for NEC PD78081(A)
Page 23: ...xii MEMO...
Page 37: ...14 CHAPTER 1 OUTLINE MEMO...
Page 47: ...24 CHAPTER 2 PIN FUNCTION MEMO...
Page 91: ...68 CHAPTER 4 PORT FUNCTIONS MEMO...
Page 125: ...102 CHAPTER 6 8 BIT TIMER EVENT COUNTERS 5 AND 6 MEMO...
Page 157: ...134 CHAPTER 10 A D CONVERTER MEMO...
Page 193: ...170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 MEMO...
Page 253: ...230 CHAPTER 16 INSTRUCTION SET MEMO...