NEC mPD789026 Subseries, User Manual

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CHAPTER 5 CLOCK GENERATION CIRCUIT
User's Manual U11919EJ3V0UM00
91
5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 5-2).
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value before Switching Set Value after Switching
PCC1 PCC1 PCC1
0 1
0 4 clocks
1 2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
5.6.2 Switching CPU clock
The following figure illustrates how the CPU clock switches.
Figure 5-5. Switching CPU Clock
V
DD
RESET
CPU Clock
Slow
Operation High-Speed
Operation
Wait (6.55 ms: at 5.0-MHz operation)
Internal Reset Operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is
released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the
time during which oscillation settles (2
15
/f
X
) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the system clock (1.6
µ
s: at 5.0-MHz
operation).
<2> After the time during which the V
DD
voltage rises to the level at which the CPU can operate at the high
speed has elapsed, the processor clock control register (PCC) is rewritten so that the high speed can be
selected.