NEC mPD789026 Subseries, User Manual

Page: 137 / 213

CHAPTER 9 SERIAL INTERFACE 00
User's Manual U11919EJ3V0UM00
137
(d) Baud rate generator control register 00 (BRGC00)
BRGC00 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC00 to 00H.
TPS003
0
0
0
0
0
0
0
0
1
TPS003 TPS002 TPS001 TPS000 0 0 0 0 BRGC00
R/W
FF73H 00H R/W
7 6 5 4 3 2 1 0
TPS002
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
TPS001
0
0
1
1
0
0
1
1
0
TPS000
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
-
Setting prohibited
Symbol
Address After Reset
3-Bit Counter Source Clock Selection
Input clock from external to ASCK pin
Other than above
Cautions 1. When writing to BRGC00 is performed during a communication operation, the
output of baud rate generator is disrupted and communications cannot be
performed normally. Be sure not to write to BRGC00 during communication
operation.
2. Be sure not to select n = 1 during an operation at f
X
= 5.0 MHz because n = 1
exceeds the baud rate limit.
3. When selecting an input clock from an external source, set port mode register 2
(PM2) to the input mode.
Remarks 1. f
X
: System clock oscillation frequency
2. n : Value determined by setting TPS000 through TPS003 (1
≤
n
≤
8)
3. The parenthesized values apply to operation at f
X
= 5.0 MHz.
The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or
a signal scaled from the clock input from the ASCK pin.
(i) Generation of baud rate transmit/receive clock by means of system clock
The transmit/receive clock is generated by scaling the system clock. The baud rate generated from
the system clock is estimated by using the following expression.
[Baud rate] = [Hz]
f
X
: System clock oscillation frequency
n : Value determined by setting TPS000 through TPS003 as shown in the above table (2
≤
n
≤
8)
f
X
2
n + 1
×
8