NEC mPD789026 Subseries, User Manual

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User's Manual U11919EJ3V0UM00
13
TABLE OF CONTENTS
CHAPTER 1 GENERAL.............................................................................................................................23
1.1 Features ......................................................................................................................................23
1.2 Applications................................................................................................................................23
1.3 Ordering Information .................................................................................................................24
1.4 Pin Configuration (Top View)....................................................................................................25
1.5 Development of 78K/0S Series..................................................................................................28
1.6 Block Diagram ............................................................................................................................30
1.7 Outline of Functions ..................................................................................................................31
CHAPTER 2 PIN FUNCTIONS ..................................................................................................................33
2.1 List of Pin Functions..................................................................................................................33
2.2 Description of Pin Functions ....................................................................................................35
2.2.1 P00 to P07 (Port 0)......................................................................................................................35
2.2.2 P10 to P17 (Port 1)......................................................................................................................35
2.2.3 P20 to P22 (Port 2)......................................................................................................................35
2.2.4 P30 to P32 (Port 3)......................................................................................................................36
2.2.5 P40 to P47 (Port 4)......................................................................................................................36
2.2.6 P50 to P53 (Port 5)......................................................................................................................37
2.2.7 RESET.........................................................................................................................................37
2.2.8 X1, X2..........................................................................................................................................37
2.2.9 NC ...............................................................................................................................................37
2.2.10 V
DD
...............................................................................................................................................37
2.2.11 V
SS
...............................................................................................................................................37
2.2.12 V
PP
(
µ
PD78F9026A only) ............................................................................................................37
2.2.13 IC (mask ROM model only) .........................................................................................................38
2.3 Pin Input/Output Circuits and Connection of Unused Pins ...................................................39
CHAPTER 3 CPU ARCHITECTURE .........................................................................................................41
3.1 Memory Space ............................................................................................................................41
3.1.1 Internal program memory space..................................................................................................46
3.1.2 Internal data memory (internal high-speed RAM) space .............................................................47
3.1.3 Special function register (SFR) area ...........................................................................................47
3.1.4 Data memory addressing ............................................................................................................48
3.2 Processor Registers ..................................................................................................................53
3.2.1 Control registers ..........................................................................................................................53
3.2.2 General-purpose registers...........................................................................................................56
3.2.3 Special function register (SFR)....................................................................................................57
3.3 Instruction Address Addressing ..............................................................................................60
3.3.1 Relative addressing .....................................................................................................................60