NEC mPD789026 Subseries, User Manual

Page: 163 / 213

CHAPTER 10 INTERRUPT FUNCTIONS
User's Manual U11919EJ3V0UM00
163
Figure 10-12. Interrupt Request Acceptance Timing (Example of MOV A,r)
Clock
CPU
Interrupt
MOV A,r
Saving PSW and PC, jump
to interrupt processing
8 Clocks
Interrupt Processing Program
If an interrupt request flag (
××
IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n
−
1,
the interrupt is accepted after the instruction under execution completes. Figure 10-12 shows an example of the
interrupt request acceptance timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed
for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is
performed after the MOV A,r instruction is completed.
Figure 10-13. Interrupt Request Acceptance Timing (When Interrupt Request Flag Generates at the Last
Clock during Instruction Execution)
Saving PSW and PC, jump
to interrupt processing
8 Clocks
Interrupt
Processing
Program
Clock
CPU
Interrupt
NOP MOV A,r
If an interrupt request flag (
××
IF) is set at the last clock of the instruction, the interrupt acceptance processing
starts after the next instruction is executed. Figure 10-13 shows an example of the interrupt acceptance timing for
an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r
instruction after the NOP instruction is executed, and then the interrupt acceptance processing is performed.
Caution Interrupt requests are reserved while the interrupt request flag register (IF0 or IF1) or the
interrupt mask flag register (MK0 or MK1) is being accessed.
10.4.3 Nesting processing
Nesting processing in which another interrupt is accepted while an interrupt is processed can be processed by
priority. When two or more interrupts are generated at once, interrupt processing is performed according to the
priority assigned to each interrupt request in advance (see Table 10-1).