CHAPTER 14 SERIAL INTERFACE CHANNEL 1
261
User’s Manual U11302EJ4V0UM
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 1.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Remark
Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial
interface channel 0.
Figure 14-2. Format of Timer Clock Select Register 3
Caution
If TCL3 is to be rewritten with data that is not identical, stop the serial transfer first.
Remarks 1.
f
X
: Main system clock oscillation frequency
2.
Figures in parentheses apply to operation with f
X
= 5.0 MHz.
TCL30
TCL3
7
6
5
4
3
2
Symbol
1
0
TCL33
Serial interface channel 0
serial clock selection
FF43H
TCL31
TCL33 TCL32
TCL34
TCL35
TCL36
TCL37
Address
After reset
R/W
88H
R/W
0
f
X
/2
2
(1.25 MHz)
0
f
X
/2
3
(625 kHz)
1
f
X
/2
4
(313 kHz)
1
f
X
/2
5
(156 kHz)
1
f
X
/2
6
(78.1 kHz)
1
f
X
/2
7
(39.1 kHz)
1
f
X
/2
8
(19.5 kHz)
1
f
X
/2
9
(9.8 kHz)
Setting prohibited
TCL32
1
1
0
0
0
0
1
1
TCL31
1
1
0
0
1
1
0
0
Other than above
TCL30
0
1
0
1
0
1
0
1
TCL37
Serial interface channel 1
serial clock selection
0
f
X
/2
2
(1.25 MHz)
0
f
X
/2
3
(625 kHz)
1
f
X
/2
4
(313 kHz)
1
f
X
/2
5
(156 kHz)
1
f
X
/2
6
(78.1 kHz)
1
f
X
/2
7
(39.1 kHz)
1
f
X
/2
8
(19.5 kHz)
1
f
X
/2
9
(9.8 kHz)
Setting prohibited
TCL36
1
1
0
0
0
0
1
1
TCL35
1
1
0
0
1
1
0
0
Other than above
TCL34
0
1
0
1
0
1
0
1