CHAPTER 13 SERIAL INTERFACE CHANNEL 0
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User’s Manual U11302EJ4V0UM
Figure 13-4. Format of Serial Bus Interface Control Register (2/2)
R/W
ACKE
Acknowledge signal output control
0
Acknowledge signal automatic output disabled (output with ACKT enabled)
Before completion
The acknowledge signal is output in synchronization with the 9th clock
of transfer
falling edge of SCK0 (automatically output when ACKE = 1).
1
After completion
The acknowledge signal is output in synchronization with the falling edge of
of transfer
SCK0 just after execution of the instruction to be set to 1 (automatically
output when ACKE = 1). However, ACKE is not automatically cleared to 0
after acknowledge signal output.
R
ACKD
Acknowledge detection
Clear conditions (ACKD = 0)
Set conditions (ACKD = 1)
• At the falling edge of SCK0 immediately after the
• When acknowledge signal (ACK) is detected at the
busy mode has been released when a transfer
rising edge of SCK0 clock after completion of
start instruction is executed
transfer
• When CSIE0 = 0
• When RESET input is applied
R/W BSYE
Note
Synchronizing busy signal output control
Busy signal which is output in synchronization with the falling edge of SCK0 clock just after
0
execution of the instruction to be cleared to 0 is disabled.
1
Busy signal is output at the falling edge of SCK0 clock following the acknowledge signal.
Note
Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not
cleared to 0.
Remarks
1.
Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
