CHAPTER 6 16-BIT TIMER/EVENT COUNTER
134
User’s Manual U11302EJ4V0UM
(6) Sampling clock select register (SCS)
This register sets the clock to be used for sampling the valid edge input to INTP0. When remote controlled
reception is carried out using INTP0, digital noise is eliminated using the sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input sets SCS to 00H.
Figure 6-9. Format of Sampling Clock Select Register
Caution f
X
/2
N+1
is the clock supplied to the CPU, and f
X
/2
6
and f
X
/2
7
are clocks supplied to peripheral
hardware. f
X
/2
N+1
is stopped in HALT mode.
Remarks 1.
N: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0
to 4)
2.
f
X
: Main system clock oscillation frequency
3.
Figures in parentheses apply to operation with f
X
= 5.0 MHz.
SCS0
SCS
7
6
5
4
3
2
Symbol
1
0
0
SCS1
INTP0 sampling clock selection
0
0
f
X
/2
N+1
Setting prohibited
FF47H
0
0
0
0
0
1
1
0
1
0
1
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
SCS1
SCS0
Address
After reset
R/W
00H
R/W
