Theory of Operation
Section Six
GPIB-1014P User Manual
6-2
© National Instruments Corporation
Two onboard signals, LDTACK* and IDTACK*, determine the control of DTACK*. The
Read/Write State Machine drives LDTACK* which is used during read and write cycles, while the
interrupter circuitry controls IDTACK* which is used during Status/ID cycles. DTACK* is
asserted when either of these signals is true; DTACK* is released when both LDTACK* and
IDTACK* are false and DSO* and DS1* are both high.
Since the GPIB-1014P does not request control of the bus, the VMEbus daisy chain bus grant
signals BG0IN* through BG3IN* are connected directly to the corresponding BG0OUT* through
BG3OUT* lines.
Address Lines
Two LS2521 comparators receive VMEbus address lines A04 through A15, and the address
modifier lines AM4, AM3, AM1, and AM0 for decoding. An FTTL gate receives AM5, AM2 ,
and LWORD* which are also used in decoding.
An ALS244 buffer receives address lines A01 through A03. These addresses are latched when AS
goes high, provided the GPIB-1014P is not active in a data transfer cycle by holding MDTACK*
low. The GPIB-1014P holds MDTACK* true while it is driving the VMEbus signal DTACK*.
Latching these addresses assures that the proper address will be present at the TLC for internal
decoding when addresses are pipelined.
Address Decoding
The GPIB-1014P occupies a 16-byte space; you determine the base address by setting the switches
on U28 and U29 (see Section Three, Configuration and Installation). The GPIB-1014P only
responds if the address modifier codes indicate 16-bit addressing. This code is either 29 or 2D
depending on whether you choose supervisory or non-privileged access. An onboard jumper
selects the access mode (see Access Mode.in Section Three).
An F20 NAND gate, an S02 NOR gate, and two LS2521 8-bit comparators decode the GPIB-
1014P base address and address modifier codes. When the base address is matched, the address
modifier codes indicate 16-bit addressing (AM0 through AM5 = 29 or 2D), and LWORD* and
IACK* are both high; then both LS2521 outputs become true, and the D input of flip-flop U24
becomes high. If one of these conditions is not met, then the D input is low.
The signal AS-25 clocks the result of the decoding circuitry. AS-25 is the address strobe signal
delayed 25 nsec. The delay assures that the decoding has been completed and the result is valid.
The clocked output signal is labeled MCYC. If MCYC is false, the GPIB-1014P is prevented from
taking any action until a new address cycle begins. If MCYC is true, the GPIB-1014P is able to
respond if DS0* goes low. DS1* is not monitored for the purpose of distinguishing 16-bit
transfers from 8-bit transfers, so the GPIB-1014P responds to BYTE (0-1) or BYTE (2-3)
accesses. The upper byte is not used during a write cycle and returns a hex value of FF during a
read cycle. When the master releases AS*, MCYC is cleared and the GPIB-1014P is ready for a
new data transfer cycle.
