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Section Four

Register Bit Descriptions

© National Instruments Corporation

4-21

GPIB-1014P User Manual

Address Status Register (ADSR)

VMEbus Address:

Base A 9 (hex)

Attributes:

Read Only

7

5

6

4

3

2

1

0

R

CIC

ATN*

SPMS

LPAS

TPAS

LA

TA

MJMN

The ADSR contains information that can be used to monitor the TLC GPIB address status.

Bit

Mnemonic

Description

7r

CIC

Controller-In-Charge Bit

CIC = -(CIDS + CADS)

CIC indicates that the TLC GPIB Controller function is in an active or
standby state, with ATN* on or off, respectively. The Controller
function is in an idle state, with ATN* off, if CIC=0.

6r

ATN*

Attention* Bit

ATN* is a status bit which indicates the current level of the GPIB ATN*
signal. If ATN* is 0, the GPIB ATN* signal is asserted.

5r

SPMS

Serial Poll Mode State Bit

If SPMS=1, the TLC GPIB Talker (T) or Talker Extended (TE) function
is enabled to participate in a serial poll. SPMS is set when the TLC has
been addressed as a GPIB Talker and the GPIB Active Controller has
issued the GPIB Serial Poll Enable (SPE) command message. SPMS is
cleared when the GPIB Serial Poll Disable (SPD) command is received,
by power on reset, or by issuing the Chip Reset auxiliary command.

4r

LPAS

Listener Primary Addressed State Bit

The LPAS bit is used when the TLC is configured for extended GPIB
addressing and, when set, indicates that the TLC has received its primary
listen address. In Mode 3, addressing (see Address Mode Register
Description), LPAS=1 indicates that the secondary address being
received on the next GPIB command may represent the TLC Extended
(Secondary) GPIB Listen address. LPAS is cleared by pon or by issuing
the Chip Reset auxiliary command.

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Summary of Contents for GPIB-1014P

Page 1: ... Copyright 1984 1994 National Instruments Corporation All Rights Reserved GPIB 1014P User Manual June 1994 Edition Part Number 370944A 01 ...

Page 2: ...tria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Québec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 ...

Page 3: ...n against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenan...

Page 4: ...erference from the equipment to radio reception in commercial areas Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense There is no guarantee that interference will not occur in a particular installation However the chances of interference are much less if the equipment is i...

Page 5: ...nd to verify that it is functioning properly Section Four Register Bit Descriptions contains detailed descriptions of the GPIB Interface registers of the NEC µPD7210 LSI GPIB Talker Listener Controller as well as summary tables for easy reference Section Five Programming Considerations explains important considerations for programming the GPIB 1014P Section Six Theory of Operation contains a funct...

Page 6: ... Appendix G Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals The Index contains an alphabetical list of key terms and topics in this manual including the page where you can find each one Abbreviations Used in This Manual The following abbreviations are used in the text of this manual A ampere C Celsius degree hex ...

Page 7: ... Manual µPD7210 Intelligent GPIB Interface Controller Engineering Data Sheet How to Interface a Microcomputer System to a GPIB The NEC µPD7210 TLC Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to cont...

Page 8: ...ription 2 5 Section Three Configuration and Installation 3 1 Configuration 3 1 Access Mode 3 3 VMEbus Base Address 3 3 VMEbus Interrupt Configuration 3 5 Interrupt Request Line Selection 3 5 Interrupt Priority Code 3 5 Interrupt Status ID Vector Selection 3 7 GPIB Cable Shield Grounding 3 8 Installation 3 9 Verification of System Compatibility 3 9 Verification Testing 3 10 Cabling 3 10 Section Fou...

Page 9: ...mming Considerations 5 1 Initialization 5 1 The GPIB 1014P as GPIB Controller 5 2 Becoming Controller In Charge CIC and Active Controller 5 2 Sending Remote Multiline Messages Commands 5 3 Going from Active to Standby Controller 5 3 Going from Standby to Active Controller 5 4 Going from Active to Idle Controller 5 4 The GPIB 1014P as GPIB Talker and Listener 5 5 Programmed Implementation of Talker...

Page 10: ...ms B 1 Appendix C Sample Programs C 1 Appendix D Multiline Interface Command Messages D 1 Appendix E Operation of the GPIB E 1 Types of Messages E 1 Talkers Listeners and Controllers E 1 The Controller In Charge and System Controller E 2 GPIB Signals and Lines E 2 Data Lines E 2 Handshake Lines E 2 NRFD not ready for data E 2 NDAC not data accepted E 2 DAV data valid E 3 Interface Management Lines...

Page 11: ...gure 3 7 GPIB Cable Shield Grounding 3 8 Figure 3 8 GPIB Cable Connector 3 11 Figure 4 1 µPD7210 Interface Registers 4 4 Figure 4 2 Writing to the Hidden Registers 4 5 Figure E 1 GPIB Connector and the Signal Assignment E 4 Figure E 2 Linear Configuration E 5 Figure E 3 Star Configuration E 6 Tables Table 2 1 GPIB 1014P Signals 2 1 Table 2 2 µPD7210 Internal GPIB Interface Registers 2 3 Table 2 3 ...

Page 12: ...ng the NECµPD7210 GPIB TLC chip Polled or interrupt driven transfers Transfer rates up to 80 kbytes sec User configurable parameters Base Address Interrupt Request Line Interrupt Status ID byte Supervisor or User Access IEEE 1014 VMEbus standard compliance Comprehensive software support The GPIB 1014P conforms to all requirements and conventions specified in the ANSI IEEE Std 1014 1987 Hereafter t...

Page 13: ......

Page 14: ...n shielded cable may cause interference to radio and television reception in commercial areas GPIB Monitor Analyzer GPIB 400 GPIB 410 Unpacking Follow these steps when unpacking your GPIB 1014P 1 Your GPIB 1014P board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such ...

Page 15: ...with both single and double height metal front panels 8 in width A DIN 41612 96 pin connector connects the GPIB 1014P to the VMEbus backplane Electrical Characteristics All integrated circuit drivers and receivers used on the GPIB 1014P meet the requirements of the VMEbus Specification and the IEEE 1014 standard Table 2 1 contains a list of the VMEbus signals used by the GPIB 1014P and the device ...

Page 16: ...ave Addressing The GPIB 1014P occupies 16 bytes of consecutive memory addresses located in the A16 short Input Output I O space These addresses are used to access the GPIB Talker Listener Controller TLC As a VMEbus slave it only responds when the address modifier AM lines specify a short supervisory access AM code 2D or short non privileged access AM code 29 An onboard jumper allows selection of p...

Page 17: ...dress Mode ADMR 8 bits B R Command Pass Through CPTR 8 bits B W Auxiliary Mode AUXMR 8 bits D R Address 0 ADR0 8 bits D W Address ADR 8 bits F R Address 1 ADR1 8 bits F W End of String EOSR 8 bits VMEbus Slave Data As discussed previously the GPIB 1014P can function as a VMEbus slave decoding memory addresses and commands from a VMEbus master It is designed to accommodate address pipelining as wel...

Page 18: ...ded value of the priority must match the level of the interrupt request line See Interrupt Request Line Selection in Section Three for more information on setting the interrupt level The onboard hardware implements the VMEbus interrupt acknowledge protocol The interrupter drives the VMEbus with an 8 bit Status ID byte vector during an interrupt acknowledge cycle This Status ID byte is set by an on...

Page 19: ...kbytes sec Data transfer rates approaching 1 Mbyte sec can be obtained with very high performance microprocessors and driver software The actual transfer rate for any particular GPIB system is a function of several factors including the following Response time of the GPIB devices involved Microprocessor speed and operating system and application program overhead Interrupt service response time GPI...

Page 20: ... National Instruments interface boards to connect a VMEbus computer to other processors in order to transfer information or to perform other communication functions 3 Lines Digital Voltmeter Able to Talk and Listen Device C Printer Able to Listen Device B Device A VMEbus Computer with GPIB 1014P Able to Talk Listen and Control 8 Lines 5 Lines DIO1 DIO8 DAV Data Valid NRFD Not Ready for Data NDAC N...

Page 21: ...2 R D Lab Microprocessor Work Station Production Testing VMEbus Computer with GPIB 1014P IEEE 488 Interface IBM PC with GPIB PC IEEE 488 Interface S 100 Computer GPIB 696P IEEE 488 Interface PDP 11 44 with GPIB11 2 IEEE 488 Interface GPIB 100 Bus Extender GPIB 100 Bus Extender Figure 2 2 GPIB 1014P in a Multiprocessor Application ...

Page 22: ...Timing and Data Direction Control Interrupt Logic Data Bus Transceivers 75162A Transceiver 75160A Transceiver System Controller Select SRQ ATN EOI DAV NRFD NDAC IFC REN DI08 DI01 µPD7210 TLC SAC DO7 DO0 AM5 AM0 A15 A01 A03 A01 WR RD INT D7 D0 GPIB LWORD DSO AS IACK CS DTACK IACKIN IACKOUT IRQ1 IRQ7 LOCAL BUS VMEbus WRITE DS1 Figure 2 3 GPIB 1014P Block Diagram ...

Page 23: ...appropriate strobe to effect the data transfer Clock and Reset Circuitry Monitors the VMEbus utility signals to generate the 8 MHz clock used by the TLC and to detect System Reset Timing State Machine Controls the timing of accesses to the GPIB 1014P from the VMEbus Interrupter Implements the correct VMEbus priority interrupt protocol allowing the GPIB 1014P to request and respond to an interrupt ...

Page 24: ...plete Talker capability Basic Talker Serial Poll Talk Only mode Unaddressed on MLA Send END or EOS Dual primary addressing TE5 Complete Extended Talker capability Basic Extended Talker Serial Poll Talk Only mode Unaddressed on MSA LPAS Send END or EOS Dual primary addressing L3 Complete Listener capability Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual extended addressin...

Page 25: ...arallel Poll Take control synchronously E1 E2 Tri state bus drivers with automatic switch to open Collector drivers during Parallel Poll The GPIB 1014P has complete Source and Acceptor Handshake capability The GPIB 1014P can operate as a basic Talker or Extended Talker and can respond to a Serial Poll It can be placed in a Talk Only mode and it is unaddressed to talk when it receives its listen ad...

Page 26: ...ke control synchronously or asynchronously Table 2 4 indicates the GPIB 1014P IEEE 1014 compliance levels Table 2 4 GPIB 1014P IEEE 1014 Compliance Levels Compliance Notation Description Bus Slave Compliance Levels D08 O 8 bit data path to TLC A16 Responds to 16 bit short I O addresses when specified on the address modifier lines ADO Accommodates Address Only cycles Interrupter Compliance Levels D...

Page 27: ...lation of the GPIB 1014P Configuration Before installing the GPIB 1014P in the VMEbus backplane the following options must be configured with hardware jumpers or switches that are located on the GPIB 1014P interface board Access Mode W2 VMEbus Base Address U28 U29 VMEbus Interrupt Configuration W3 Interrupt Status ID Vector U7 GPIB Cable Shield Grounding W1 ...

Page 28: ......

Page 29: ...dress Modifier AM code 2D In the Supervisor and User non privileged mode the board responds to AM codes 2D or 29 Refer to the ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus for more information on Supervisor and Non privileged modes a Supervisor only NP S W2 I O Privileged NP S b Supervisor and User W2 I O Non privileged Figure 3 2 Access Selection VMEbus Base Address T...

Page 30: ... address bit Press the side labeled 1 to select a logical one Figure 3 3 shows the configuration for the base address default setting 1000 hex 1 2 3 4 5 6 O F F O N This side down for logic 0 This side down for logic 1 U28 7 I1 I2 I3 A4 A5 A6 A7 0 Key the side you press down for Base Address 1000 hex not involved in Base Address selection 1 2 3 4 5 6 O F F O N This side down for logic 0 This side ...

Page 31: ... The interrupt priority code must be set to correspond to the interrupt request line Figure 3 4a shows the jumper configured to select interrupt request line IRQ2 while Figure 3 4b shows the configuration for selecting IRQ4 The default setting for the GPIB 1014P is IRQ2 1 7 IRQ W3 b Select Interrupt Request Line Configured to IRQ4 1 7 IRQ W3 a Select Interrupt Request Line Configured to IRQ2 Defau...

Page 32: ...d in Interrupt Priority Code selection 1 2 3 4 5 6 O F F O N This side down for logic 0 This side down for logic 1 U28 7 I1 I2 I3 A4 A5 A6 A7 4 b Switch configuration using IRQ4 1 2 3 4 5 6 O F F O N This side down for logic 0 This side down for logic 1 U28 7 I1 I2 I3 A4 A5 A6 A7 2 a Switch configuration using IRQ2 Default setting Figure 3 5 VMEbus Interrupt Priority Code Selection ...

Page 33: ...ed V0 through V7 as shown in Figure 3 6 Bit V7 corresponds to the most significant bit while V0 corresponds to the least significant Press the side labeled 0 to select a logical zero for the corresponding address bit Press the side labeled 1 to select a logical one Figure 3 6 shows the configuration for a status ID byte value 1A hex Key the side you press down for Status ID Byte 1A hex 1 2 3 4 5 6...

Page 34: ...1 to the side labeled CON to short or connect the GPIB cable shield to VMEbus digital logic ground Place the jumper on the side labeled ISO to leave the GPIB cable shield isolated Select one configuration depending on whether or not the GPIB 1014P is the GPIB System Controller and whether or not the GPIB cable shield is grounded elsewhere Figure 3 7 shows the two possible configurations The GPIB 1...

Page 35: ...h the GPIB 1014P will be installed to ensure that the GPIB 1014P provides all the necessary signals needed by the VMEbus system and vice versa Table 3 1 GPIB 1014P Pin Assignment on VMEbus Connector P1 Pin No Signal Used Signal Not Used Pin No Signal Used Signal Not Used A1 D00 A17 GND A2 D01 A18 AS A3 D02 A19 GND A4 D03 A20 IACK A5 D04 A21 IACKIN A6 D05 A22 IACKOUT A7 D06 A23 AM4 A8 D07 A24 A07 A...

Page 36: ... in Section Seven of this manual consist of a series of steps written in a pseudo processor independent language with instructions The steps generally involve writing data to specific GPIB 1014P device registers followed by reading other GPIB 1014P registers to verify that the programming is correct These tests exercise virtually all of the major functions of the GPIB 1014P including I O communica...

Page 37: ... present on the GPIB cable connector DIO1 DIO2 DIO3 DIO4 EOI DAV NRFD NDAC IFC SRQ ATN SHIELD DIO5 DIO6 DIO7 DIO8 REN GND TW PAIR W DAV GND TW PAIR W NRFD GND TW PAIR W NDAC GND TW PAIR W IFC GND TW PAIR W SRQ GND TW PAIR W ATN SIGNAL GROUND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 3 8 GPIB Cable Connector ...

Page 38: ... Write only 8 bit Interrupt Status Register 1 Base address 3 Read only 8 bit Interrupt Mask Register 1 Base address 3 Write only 8 bit Interrupt Status Register 2 Base address 5 Read only 8 bit Interrupt Mask Register 2 Base address 5 Write only 8 bit Serial Poll Status Register Base address 7 Read only 8 bit Serial Poll Mode Register Base address 7 Write only 8 bit Address Status Register Base ad...

Page 39: ...significant bit bit 7 for an 8 bit register shown on the left and the least significant bit bit 0 shown on the right A rectangle is used to represent each bit Each bit is labeled with a name inside its rectangle An asterisk after the bit name indicates that the signal is active low An asterisk is equivalent to an overbar In many of the registers several bits are labeled with an X indicating don t ...

Page 40: ...sters register contents and interface functions as well as GPIB remote messages commands and logic states as defined in the IEEE 488 standard After a mnemonic of a name has been defined the mnemonic is used thereafter Appendix F contains a list of all mnemonics used in this manual along with their type and name Mnemonics are assigned to messages states registers bits functions and integrated circu...

Page 41: ...ach of the 16 interface registers is addressed relative to the GPIB 1014P VMEbus base address which is set with DIP switches refer to Base Address in Section Three Figure 4 1 shows the µPD7210 Interface registers the bit mnemonics of each its read write accessibility and its relative address Figure 4 2 shows the hidden GPIB interface registers and illustrates the method of writing to those registe...

Page 42: ... DET END RX DEC ERR DO DI CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE INT SRQI LOK REM CO LOKC REMC ADSC 0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IEADSC IE S8 PEND S6 S5 S4 S3 S2 S1 S8 rsv S6 S5 S4 S3 S2 S1 CIC ATN SPMS LPAS TPAS LA TA MJMN ton lon TRM1 TRM0 0 0 ADM1 ADM0 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 X DT0 DL0 AD5 0 AD4 0 AD3 0 AD2 0 AD1 0...

Page 43: ...COM0 0 CLK3 CLK2 CLK1 CLK0 U S P3 P2 P1 BIN XEOS REOS HLDE HLDA ISS INV TRI SPEOI CPT ENABLE 0 0 0 DHDT DHDC 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 When CNT2 CNT0 is ICR is loaded with PPR is loaded with AUXRA is loaded with AUXRB is loaded with AUXRE is loaded with Control Code Command Code W AUXMR B Figure 4 2 Writing to the Hidden Registers ...

Page 44: ...il the byte is removed from the DIR by an I O read from a VMEbus master The Acceptor Handshake AH completes automatically after the byte has been read In RFD Holdoff mode refer to Auxiliary Register A later in this section the GPIB Handshake is not finished until the Finish Handshake FH auxiliary command is issued telling the TLC to release the Holdoff By using the RFD Holdoff mode the same byte c...

Page 45: ...ta Out Register CDOR is used to move data from the VMEbus to the GPIB when the TLC is the GPIB Talker or the Active Controller Outgoing data is separately latched by this register and is not destroyed by a read of the DIR which is located at the same address When a byte is written to the CDOR the TLC GPIB Source Handshake SH function is initiated and the byte is transferred to the GPIB Bit Mnemoni...

Page 46: ...bit and an interrupt enable bit associated with it If the Interrupt Enable bit is true when the corresponding status condition or event occurs a hardware interrupt request is generated Bits in ISR1 are set and cleared by the TLC regardless of the status of the interrupt enable bits in IMR1 If an interrupt condition occurs at the same time ISR1 is being read the TLC holds off setting the correspond...

Page 47: ...ized by the TLC and all following GPIB secondary commands when the Command pass through feature is enabled by the CPT ENAB bit AUXRB 0 w Any GPIB command message not decoded by the TLC is treated as an undefined command for example the Go To Local command GTL However any addressed command is automatically ignored when the TLC is not addressed Undefined commands are read using the CPTR The TLC hold...

Page 48: ...e 3 When APT is set the DAC message is held and the GPIB handshake stops until either the Valid or Non Valid auxiliary command is issued The secondary address can be read from the CPTR 5r DET Device Execute Trigger Bit 5w DET IE Device Execute Trigger Interrupt Enable Bit DET is set by DTAS DET is cleared by pon Read ISR1 Notes DTAS GPIB Device Trigger Active State pon power on reset Read ISR1 Bit...

Page 49: ... from the GPIB Talker or the data byte in the DIR matches the contents of the End Of String Register EOSR 3r DEC Device Clear Bit 3w DEC IE Device Clear Interrupt Enable Bit DEC is set by DCAS DEC is cleared by pon Read ISR1 Notes DCAS GPIB Device Clear Active State pon power on reset Read ISR1 Bit is cleared immediately after it is read The DEC bit indicates that the GPIB Device Clear DCL command...

Page 50: ...ost ERR is set when data is sent over the GPIB without a specified Listener or when a byte is written to the CDOR during SIDS or during the SDYS to SIDS transition 1r DO Data Out Bit 1w DO IE Data Out Interrupt Enable Bit DO is set as TACS SGNS becomes true DO is cleared by Read ISR1 TACS SGNS Notes TACS GPIB Talker Active State SGNS GPIB Source Generate State Read ISR1 Bit is cleared immediately ...

Page 51: ...Listener Active State ACDS GPIB Accept Data State Continuous Mode Listen In Continuous Mode auxiliary command in effect pon power on reset Read ISR1 Bit is cleared immediately after it is read Finish Handshake Finish Handshake auxiliary command issued Holdoff Mode RFD holdoff state Read DIR Read Data In Register The DI bit indicates that the TLC as a GPIB Listener has accepted a data byte from the...

Page 52: ...e interrupt request is generated Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2 If a condition occurs which requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read the TLC holds off setting or clearing the bit or bits until the read is finished Bit Mnemonic Description 7r INT Interrupt Bit This bit is the logical OR of all the enabl...

Page 53: ...Interrupt on Data Out Bit DI Data In Bit DI IE Enable Interrupt on Data In Bit SRQI Service Request Input Bit SRQI IE Enable Interrupt on Service Request Input Bit REMC Remote Change Bit REMC IE Enable Interrupt on Remote Change Bit CO Command Output Bit CO IE Enable Interrupt on Command Output Bit LOKC Lockout Change Bit LOKC IE Enable Interrupt on Lockout Change Bit ADSC Address Status Change Bi...

Page 54: ...lemented Do not set this bit 4r REM Remote Bit This bit is true whenever the TLC GPIB RL function is in one of two states Remote State REMS or Remote With Lockout State RWLS The TLC RL function enters one of these states when the System Controller has asserted the Remote Enable line REN and the Controller In Charge addresses the TLC as a Listener 4w DMAI DMA Input Enable Bit The DMA feature is not...

Page 55: ...er there is a change in the LOK bit ISR2 5 r REMS RELS 1w REMC Remote Change Bit 1r REMC IE Remote Change Interrupt Enable Bit REMC is set by any change in REM REMC is cleared by pon Read ISR2 Notes REM ISR2 4 r pon power on reset Read ISR2 Bit is cleared immediately after it is read REMC is set whenever there is a change in the REM bit ISR2 4 r REMS RELS 0r ADSC Addressed Status Change Bit 0w ADS...

Page 56: ... ADSR 1 r LA Listener Active bit ADSR 2 r CIC Controller In Charge bit ADSR 7 r MJMN Major Minor bit ADSR 0 r lon Listen Only bit ADMR 6 w ton Talk Only bit ADMR 7 w pon power on reset Read ISR2 Bit is cleared immediately after it is read ADSC is set whenever there is a change in one of the four bits TA LA CIC MJMN of the Address Status Register ADSR ...

Page 57: ...al Poll Enable SPE command message it transmits a byte of status information SPMR 7 0 to the Controller In Charge after the Controller goes to Standby and becomes an active Listener 6r PEND Pending Bit PEND is set when rsv 1 and cleared when Negative Poll Response States NPRS Request Service rsv 1 Reading the PEND status bit can confirm that a request was accepted and that the Status Byte STB was ...

Page 58: ...asserted 5r SPMS Serial Poll Mode State Bit If SPMS 1 the TLC GPIB Talker T or Talker Extended TE function is enabled to participate in a serial poll SPMS is set when the TLC has been addressed as a GPIB Talker and the GPIB Active Controller has issued the GPIB Serial Poll Enable SPE command message SPMS is cleared when the GPIB Serial Poll Disable SPD command is received by power on reset or by i...

Page 59: ...issuing the Chip Reset auxiliary command 1r TA Talker Active Bit TA is set whenever the TLC has been addressed or programmed as the GPIB Talker that is the TLC is in the Talker Active State TACS the Talker Addressed State TADS or the Serial Poll Active State SPAS The TLC can be addressed to talk either by sending its own talk or extended talk address while it is CIC or by receiving its talk addres...

Page 60: ...aring ton does not by itself take the TLC out of GPIB Talker Active state TACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command 6w lon Listen Only Bit Setting lon programs the TLC to be a GPIB Listener If lon is set ton ADM1 and ADM0 should be cleared Note Clearing lon does not by itself take the TLC out of Listener Active state LACS It is also necessary to...

Page 61: ...tle 0 0 0 ton lon 1 0 1 Normal dual addressing 2 1 0 Extended single addressing 3 1 1 Extended dual addressing In mode 1 ADR0 and ADR1 contain the major and minor addresses respectively for dual primary GPIB address applications that is the TLC responds to two GPIB addresses a major address and a minor address The MJMN bit in the ADSR indicates which address was received In applications where the ...

Page 62: ...ram when mode 3 is used When the TLC is in Talker Primary Addressed State TPAS or Listener Primary Addressed State LPAS and a secondary address byte is on the GPIB DIO lines the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR The TLC Acceptor Handshake is held up in the Accept Data State ACDS until the Valid or Non Valid auxiliary command is written to the AUXMR ...

Page 63: ...ne GPIB commands recognized by the µPD7210 are listed in Table 4 3 All GPIB Secondary Command Group SCG messages following an undefined GPIB PCG message are also treated as undefined In such a case when an undefined GPIB message is encountered it is held in the CPTR and the TLC Acceptor Handshake function is held off in ACDS until the Valid auxiliary command is written to the AUXMR The CPTR is als...

Page 64: ...configure 18 SPE Serial Poll Enable 19 SPD Serial Poll Disable 20 3E MLA My Listen Address 3F UNL Unlisten 40 5E MTA My Talk Address 5F UNT Untalk 60 6F MSA PPE My Secondary Address or Parallel Poll Enable 70 7E MSA PPD My Secondary Address or Parallel Poll Disable The CPTR is read during a TLC initiated Parallel Poll operation to fetch the Parallel Poll response The PPR message is latched into th...

Page 65: ... five hidden registers Auxiliary Register A AUXRA Auxiliary Register B AUXRB Parallel Poll Register PPR Auxiliary Register E AUXRE Internal Counter Register ICR Table 4 2 shows the control and command codes used Bit Mnemonic Description 7 5w CNT 2 0 Control Code Bits 2 through 0 These bits specify the control code that is the manner in which the information in bits COM 4 0 is to be used If CNT 2 0...

Page 66: ...the hidden registers indicated by the control code in CNT 2 0 Table 4 4 Auxiliary Command Summary Function Code COM4 COM0 Hex 4 3 2 1 0 Code Auxiliary Command 0 0 0 0 0 00 Immediate Execute pon 0 0 0 1 0 02 Chip Reset 0 0 0 1 1 03 Finish Handshake 0 0 1 0 0 04 Trigger 0 0 1 0 1 05 Retur n to Local 0 0 1 1 0 06 Send EOI 0 0 1 1 1 07 Non Valid Secondary Command or Address 0 1 1 1 1 0F Valid Secondar...

Page 67: ...0 Code Auxiliary Command 1 0 0 0 0 10 Go To Standby 1 0 0 1 1 13 Listen 1 1 0 1 1 1B Listen in Continuous Mode 1 1 1 0 0 1C Local Unlisten 1 1 1 0 1 1D Execute Parallel Poll 1 1 1 1 0 1E Set IFC 1 0 1 1 0 16 Clear IFC 1 1 1 1 1 1F Set REN 1 0 1 1 1 17 Clear REN 1 0 1 0 0 14 Disable System Control CNT 2 0 set to 000 binary Represents all eight bits of the Auxiliary Mode Register ...

Page 68: ...e SIDS Source Idle State SIIS System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State If the command is sent while a pon message is already active by either an external reset pulse or the Chip Reset auxiliary command the local pon message becomes false 0 0 0 1 0 Chip Reset The Chip Rese...

Page 69: ...mand generates a high pulse on the TRIG pin T R3 pin when TRM1 0 of the TLC The Trigger command performs the same function as if the DET Device Trigger bit ISR1 5 r were set The DET bit is not set by issuing the Trigger command 0 0 1 0 1 Return to Local rtl 0 1 1 0 1 Return to Local rtl The two Return to Local commands implement the rtl message as defined by IEEE 488 When COM3 is zero the message ...

Page 70: ...as if a My Secondary Address MSA message had been received The DAC message is released at the time of Command Pass Through CPT DAC is also released if DCAS or DTAS is in Holdoff state 0 0 0 0 1 Clear Parallel Poll Flag 0 1 0 0 1 Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3 The value of the Parallel Poll Flag is used as the local message ist when bit four of...

Page 71: ...sage is cleared when the TLC enters CACS 1 0 0 1 1 Listen The listen command generates the local message ltn in the form of a pulse 1 1 0 1 1 Listen in Continuous Mode The Listen in Continuous Mode command generates the local message ltn in the form of a pulse and places the TLC in continuous mode In continuous mode the local message rdy is issued when the Acceptor Not Ready State ANRS is initiate...

Page 72: ...r State STRS or Source Delay State SDYS 1 1 1 1 0 Set IFC 1 0 1 1 0 Clear IFC These commands generate the local message request system control rsc and set Interface Clear IFC to the value of COM3 These commands should only be issued if the GPIB 1014P is the System Controller SC In order to meet the IEEE 488 requirements you must not issue the Clear IFC command until IFC has been held true for at l...

Page 73: ...strates how they are loaded with data from the AUXMR Internal Counter Register ICR VMEbus Address Base Address B hex AUXMR Control Code 001 Binary Bits 7 5 Attributes Write Only Accessed through AUXMR 4 3 2 1 0 W 0 CLK3 CLK2 CLK1 CLK0 Bit Mnemonic Description 4w 0 Reserved Bit Write zero to this bit 3 0w CLK 3 0 Clock Bits 3 though 0 The contents of the ICR are used to divide internal counters tha...

Page 74: ...arallel Poll Configure PPC Parallel Poll Enable PPE Parallel Poll Disable PPD and Identify IDY messages The user need only set or clear the individual status ist message using Set Clear Parallel Poll Flag auxiliary commands according to pre established system protocol convention Writing to the PPR after it is remotely configured will corrupt the configuration When using the local PPC capability co...

Page 75: ... Parallel Poll Response Bits 3 through 1 PPR bits 3 through 1 designated P 3 1 contain an encoded version of the Parallel Poll Response P 3 1 indicate which of the eight DIO lines is asserted during a Parallel Poll equal to N 1 The GPIB 1014P normally drives the GPIB DIO lines using three state drivers During Parallel Poll responses however the drivers automatically convert to Open Collector mode ...

Page 76: ...Description 4w BIN Binary Bit The BIN bit selects the length of the EOS message Setting BIN causes the End of String Register EOSR to be treated as a full 8 bit byte When BIN 0 the EOSR is treated as a 7 bit register for ASCII characters and only a 7 bit comparison is done with the data on the GPIB 3w XEOS Transmit END with EOS Bit The XEOS bit permits or prohibits automatic transmission of the GP...

Page 77: ...he Finish Handshake FH auxiliary command is issued Unlike Normal Handshake mode the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR that is the GPIB RFD message is not generated In RFD Holdoff on End mode operation is the same as the RFD HLDA but only when the end of the data block EOS or END message is detected that is the END message is received ...

Page 78: ...me value as the TLC Service Request State SRQS The TLC is asserting the GPIB SRQ message when it is in SRQS When ISS 0 ist takes on the value of the TLC Parallel Poll Flag The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands 3w INV Invert Bit The INV bit affects the polarity of the TLC INT pin Setting INV causes the polarity of ...

Page 79: ...D message in Serial Poll Active State SPAS If SPEOI is set EOI is sent true when the TLC is in SPAS otherwise EOI is sent false in SPAS 0w CPT ENABLE Command Pass Through Enable Bit The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or prohibits the setting of the CPT bit ISR1 7 r on receipt of an undefined command When CPT ENAB is set and an undefined com...

Page 80: ... causes the two lowest order bits to be written to AUXRE The 2 bit code DHDC and DHDT determines how the TLC uses DAC Holdoff Bit Mnemonic Description 4 2w 0 Reserved Bits Write zeros to these bits 1w DHDC DAC Holdoff on DCAS Bit Setting DHDC enables DAC holdoff when the TLC enters Device Clear Active State DCAS Clearing DHDC disables DAC Holdoff on DCAS Issuing the Finish Handshake auxiliary comm...

Page 81: ...o or one 6r DT0 Disable Talker 0 If DT0 is set it indicates that the mode 2 primary or mode 1 and 3 major Talker is not enabled that is the TLC does not respond to a GPIB talk address matching AD 5 0 1 0 If DT0 0 the TLC responds to a GPIB talk address matching bits AD 5 0 1 0 5r DL0 Disable Listener 0 Bit If DL0 is set it indicates that the mode 2 primary or mode 1 and 3 major Listener is not ena...

Page 82: ...gisters ADR0 or ADR1 respectively 6w DT Disable Talker Bit DT must be set if recognition of the GPIB talk address formed from AD5 through AD1 ADR 4 0 w is not to be enabled 5w DL Disable Listener Bit DL must be set if recognition of the GPIB Listen address formed from AD 5 1 is not to be enabled 4 0w AD5 1 Address Bit These bits specify the five low order bits of the GPIB address that is to be rec...

Page 83: ...ine was asserted with the received byte EOI is cleared by pon or by using the Chip Reset auxiliary command 6r DT1 Disable Talker 1 Bit If DT1 is set the mode 2 secondary or mode 1 and 3 minor Talker is not enabled that is the TLC does not respond to a secondary address or minor primary talk address formed from bits AD5 1 to AD1 1 If DT1 is cleared DT1 0 and the TLC received its primary talk addres...

Page 84: ...n be placed in the EOSR to be used in detecting the end of a block of data The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA AUXRA 4 w If the TLC is a Listener and bit REOS of AUXRA is set the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR If the TLC is a Talker and the data is being transmitted and XEOS bit of AUXRA is set the END me...

Page 85: ...de Register SPMR are cleared End Or Identify EOI bit is cleared All bits of the Auxiliary Registers A B and E AUXRA AUXRB and AUXRE are cleared The Parallel Poll Flag and Request System Control RSC local message are cleared The Internal Clock Register ICR is set to a count of eight The Transmit Receive Mode 0 TRM0 and Transmit Receive Mode 1 TRM1 bits in the Address Mode Register ADMR are cleared ...

Page 86: ...andby not asserting ATN The following paragraphs discuss the various transitions between these two modes Becoming Controller In Charge CIC and Active Controller The TLC can become CIC either by being the System Controller and taking control by issuing the Set IFC auxiliary command or by being passed control of the GPIB from the current Active Controller To take control issue the Set IFC auxiliary ...

Page 87: ...the TLC automatically becomes CIC and asserts ATN As soon as the TLC becomes CIC the CIC bit in the ADSR and the Command Output CO bit in Interrupt Status Register 2 ISR2 are set Using these two bits the program can unambiguously determine that the TLC is the GPIB Active Controller and can send remote messages Sending Remote Multiline Messages Commands The GPIB 1014P sends commands as Active Contr...

Page 88: ...ynchronously auxiliary command Do not issue the Take Control Asynchronously auxiliary command until there are no more bytes to send and the DO bit is set Case 2 The TLC as a Listener takes control upon receipt of the Take Control Synchronously auxiliary command If programmed I O is used the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the...

Page 89: ...LA 0 1 0 Addressed Talker cannot send data 1 1 0 Active Talker can send data 0 0 1 Addressed Listener cannot receive data 1 0 1 Active Listener can receive data The status bits Address Status Change ADSC Command Output CO Address Pass Through APT Data Out DO and Data In DI are used to prompt the program possibly with an interrupt request when a change of state occurs The following paragraphs discu...

Page 90: ...ts primary GPIB listen address the Listener Primary Addressed State LPAS bit in the ADSR is set If the TLC receives its secondary GPIB listen address before receiving another GPIB Primary Command Group PCG message that is not its MLA the LA bit in the ADSR is set the ADSC bit in ISR2 is set and the DI bit in ISR1 is set when the first GPIB data byte is received The Major Minor MJMN bit in the ADSR...

Page 91: ...the GPIB CIC can address several devices having the same primary address without repeating the primary address each time If a PCG message is received before a secondary address is received the TPAS and LPAS bits are cleared Sending Receiving Messages When the GPIB 1014P is a GPIB Talker or Listener data device dependent messages can be sent or received To send data wait until the GPIB 1014P has be...

Page 92: ...ified by the ISR1 and ISR2 bits For one of these conditions to drive the selected IRQ line the following criteria must be satisfied The interrupt condition must be true The interrupt condition must be enabled bits in IMR1 and IMR2 The µPD7210 interrupt signal must be programmed to be active high see Auxiliary Register B in Section Four After an interrupt is generated the operating system will ask ...

Page 93: ... is set the TLC waits until any current Serial Poll is complete and then asserts the GPIB SRQ signal In response to that signal the CIC starts the poll addressing the TLC to talk When the CIC unasserts ATN the TLC unasserts SRQ and transfers the STB message onto the GPIB data bus with DIO7 the RQS signal asserted While the Serial Poll is in progress SPAS 1 the CIC normally reads the STB only once ...

Page 94: ...l operation is complete based on the condition of CO CO 1 when the poll is complete The response can be obtained by reading the contents of the CPTR The response is held in the CPTR until a GPIB command is transmitted or the TLC Controller function becomes inactive In response to IDY each device participating in the Parallel Poll drives one and only one GPIB DIO line its Parallel Poll response or ...

Page 95: ...llowing Enabling the TLC to participate in polls Selecting the sense or polarity of the response Selecting the GPIB data line on which the response will be asserted when the CIC issues the IDY message With remote configuration PP1 the TLC interprets the configuration commands received from the CIC without any software assistance or interpretation from your program With local configuration PP2 the ...

Page 96: ...atus signals to or from the VMEbus All drivers drive the proper amount of current as required by the VMEbus specification and all receivers meet the bus loading limits as called out by the VMEbus specification Data Lines An F245 octal bus transceiver connects VMEbus data lines D00 through D07 to the GPIB 1014P During interrupter Status ID cycles or read cycles to the GPIB 1014P the F245 is directe...

Page 97: ...determine the base address by setting the switches on U28 and U29 see Section Three Configuration and Installation The GPIB 1014P only responds if the address modifier codes indicate 16 bit addressing This code is either 29 or 2D depending on whether you choose supervisory or non privileged access An onboard jumper selects the access mode see Access Mode in Section Three An F20 NAND gate an S02 NO...

Page 98: ...s driven true and the data bus drivers are enabled immediately The state machine then uses the VMEbus utility SYSCLK to count a minimum delay of 250 nsec which corresponds to the read access time of the TLC At this time the local signal LDTACK becomes true signaling the DTACK assert release circuitry to drive the VMEbus signal DTACK low This indicates that valid data is present on the data bus The...

Page 99: ...ng onboard switches as described in Interrupt Status ID Byte in Section Three Two inverters delay EV to allow for data set up on the VMEbus EV then signals the DTACK Asset Release circuitry via IDTACK to drive DTACK true EV and EV are held true until the interrupt handler releases DS0 The rise of EV releases the IRQ line Therefore the GPIB 1014P is a Release On AcKnowledge ROAK interrupter Note Ev...

Page 100: ...g mask bits that is they are set and cleared regardless of whether an interrupt request is enabled for the condition An important fact to remember is that ISR1 and ISR2 are always cleared when read even if the condition which caused the bit to be initially set remains true Data to and from the GPIB is pipelined through the CDOR and DIR respectively An 8 MHz clock is used as the CLOCK input to the ...

Page 101: ...ctioning properly Since most failures including problems with short or open circuits on the PWB prevent the TLC from working at all this test gives limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly NDAC is the GPIB Not Data Accepted signal By programming the TLC to Listen or not Listen via the ADMR NDAC can be asserted o...

Page 102: ...Equations not followed by a question mark are instructions to the user to load the value shown into the designated register Equations followed by a question mark are instructions to the user to read the register and verify that the value in the register is the one indicated The column to the left of each test step contains the relative register address Comments written to the right of each test st...

Page 103: ... ISR2 0 7 SPSR 0 9 ADSR 40 B CPTR 0 3 Test ton DO ERR CPTR TA B AUXMR 2 Chip Reset 9 ADMR 80 ton B AUXMR 0 Immediate execute pon 9 ADSR 42 TA 3 ISR1 2 DO 1 CDOR 51 write data byte B CPTR 51 verify 3 ISR1 6 DO ERR 3 ISR1 0 bits cleared when read B AUXMR 2 Chip Reset 9 ADMR 0 disable ton B AUXMR 0 Immediate execute pon 9 ADSR 40 not TA 4 Check lon LA B AUXMR 2 Chip Reset 3 IMR1 0 no interrupts 5 IMR...

Page 104: ...struments Corporation 7 3 GPIB 1014P User Manual 5 Test ATN CIC CO B AUXMR 2 Chip Reset 9 ADMR 31 Address Mode 1 B AUXMR 0 Immediate execute pon B AUXMR 1E set IFC B AUXMR 16 clear IFC 9 ADSR 80 CIC 5 ISR2 9 CO ADSC B AUXMR 10 go to standby 9 ADSR C0 CIC ATN ...

Page 105: ...ytes sec Power Requirement 5 VDC 0 5 A typical 1 0 A maximum Physical Board dimensions 6 3 x 3 9 in Input output connector IEEE 488 standard 24 pin Operating Environment Component temperature 0 to 70 C Relative humidity 10 to 90 noncondensing Storage Environment Temperature 62 to 71 C Relative humidity 0 to 100 noncondensing ...

Page 106: ... National Instruments Corporation B 1 GPIB 1014P User Manual Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB 1014P ...

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Page 117: ... interface messages CMD Pass GPIB control to another device PASSC Assumptions regarding the state of the GPIB 1014P appear at the beginning of each routine and must be adhered to for proper error free operation The following characteristics of the code must be considered The GPIB 1014P base address is FF1000 hex Normal non extended GPIB addressing is used Time out on subroutine calls is not implem...

Page 118: ...ontrol Data Out Register write ISR1 BASE 0x3 Interrupt Status Register 1 read IMR1 BASE 0x3 Interrupt Mask Register 1 write ISR2 BASE 0x5 Interrupt Status Register 2 read IMR2 BASE 0x5 Interrupt Mask Register 2 write SPSR BASE 0x7 Serial Poll Status Register read SPMR BASE 0x7 Serial Poll Mask Register write ADSR BASE 0x9 Address Status Register read ADMR BASE 0x9 Address Mode Register write CPTR ...

Page 119: ...ter A AUXRB 0240 Auxiliary Register B AUXRE 0300 Auxiliary Register E AUXMR Commands IEPON 000 Immediate execute power on FH 003 Finish release handshake SEOI 006 Send END GTS 020 Go to standby TCA 021 Take control asynchronously TCS 022 Take control synchronously TCSE 032 Take control synchronously on END LTN 023 Listen LTNC 033 Listen continuously LUN 034 Unlisten SIFC 036 Set IFC CIFC 026 Clear...

Page 120: ...uffer for device dependent messages count word 0 Current number of commands transferred datct word 0 Number of data bytes to be sent cic byte 0 Controller In Charge flag non zero if CIC ola byte 0 Listen address passed to WRITE sre byte 0 REN flag zero to not set REN non zero to set REN tctadr byte 0 TCT address of new Active Controller vseoi byte 0 SEOI flag zero to not send non zero to send END ...

Page 121: ...peed timing is used Interrupts are not used Status byte will be set elsewhere Remote Parallel Poll configuration will be used Actions Pulse IEPON to put hardware in known reset state Disable interrupts and clear status Set hardware registers to desired values Status on return The following registers are cleared ISR1 2 IMR1 2 SPMR SPSR PPR AUXRA AUXRE Other registers are configured as described The...

Page 122: ...TLC interrupts movb 0 IMR2 L tstb ISR1 L Clear status bits by reading registers tstb ISR2 L movb MODE1 TRM ADMR L Set address mode Talker Listener inactive and proper T R signal mode movb MA SEL0 ADR L Set GPIB address mode 1 primary only with Talker Listener enabled movb DT1 DL1 SEL1 ADR L Disable secondary address recognition movb ICR 8 AUXMR L Set clock divider for 8MHz low speed rts ...

Page 123: ...ctions Assert GPIB IFC Wait at least 100 microseconds Unassert IFC Status on return GPIB 1014P is Active Controller Interface functions of other GPIB devices are reset to their idle states 68000 Code Comments IFC link a6 4 Link movl d1 a6 4 Save d1 movb SIFC AUXMR Set the IFC signal movb 50 d1 Wait at least 100 microseconds 18 clock cycles IFC1 subb 1 d1 bne IFC1 movb CIFC AUXMR Clear IFC movl a6 ...

Page 124: ...REN is to be asserted and is zero if REN is to be unasserted GPIB 1014P is System Controller and Active Controller Actions Check sre flag if non zero true send REN else send clear REN Status on return REN is asserted or unasserted 68000 Code Comments REN tstb sre L Turn on the REN signal if sre is non zero beq REN1 movb SREN AUXMR L bra REN2 REN1 movb CREN AUXMR L Else turn off REN if sre is zero ...

Page 125: ...er has been or will be addressed The Talker will send END with last byte if the number of bytes sent is less than the byte count The d0 register contains the byte count The a0 register contains the address of the data buffer The user specified variable cic is set properly Actions Release any holdoff in progress Set up handshake holdoffs as r ired by Controller status cic Wait for GPIB END message ...

Page 126: ...HLDE and BIN in AUXRA bra RCV2 RCV1 movb AUXRA AUXMR L No Clear any HLDE or HLDA in effect RCV2 clr d1 Clear byte counter RCV3 movb ISR1 L d2 Read status btst END DI d2 Wait for GPIB END or DI beq RCV3 btst END d2 Look for END bne RCV5 movb DIR a0 Read byte addw 1 d1 cmpw d0 d1 More bytes to read bne RCV3 Yes continue bra RCV6 No exit RCV5 movb DIR a0 END read last byte movw d1 d0 Record bytes rea...

Page 127: ...t to 1 The buffer datbuf is free to place incoming data The number of bytes to read is placed in datct Actions Set up cmdbuf and cmdct and call CMD to address the Talker and unaddress all other devices Program the GPIB 1014P to listen Go to standby and unassert ATN Transfer the contents of datct to the d0 register Load the a0 register with the address of datbuf Call RCV to receive the data Call CM...

Page 128: ...lker movb LTN AUXMR L Program GPIB 1014P to be a Listener movb GTS AUXMR L so it can take control synchronously later then go to standby and drop ATN movw datct d0 Take control Preset d0 register with byte count movl datbuf a0 Preset a0 register with buffer address bsr RCV Receive routine will read data movb TCS AUXMR L READ1 btst NATN ADSR Wait for ATN indefinitely bne READ1 subw 1 cmdct Prepare ...

Page 129: ...l be addressed to talk If the GPIB 1014P is Idle Controller the current CIC will go to standby The d0 register contains the byte count The a0 register contains the address of the data buffer The user specified variable veoi has been set properly Actions Copy byte count to d1 Wait until the CDOR is empty Decrement d1 If last byte assert EOI if in use Write a byte Check for a GPIB error Loop until a...

Page 130: ...CDOR or ERR beq DSEND1 btst ERR d2 Look for error bne DSEND3 subl 1 d1 dec byte counter bmi DSEND4 Have all bytes been sent bne DSEND2 No Is this last byte cmpb 0 vseoi L Yes EOI in use beq DSEND2 No movb SEOI AUXMR L Send EOI with last byte DSEND2 movb a0 CDOR L Next byte bra DSEND1 movb DMAO IMR2 Enable DMA to the CDOR DSEND3 movl 1 d0 Return 1 indicating error DSEND4 movl a6 8 d2 Restore d2 mov...

Page 131: ...a The data to be sent is placed in datbuf The variable datct contains the number of bytes to send Actions Set up cmdbuf and cmdct and call CMD to address the GPIB 1014P as Talker to address the Listener and to unaddress all other devices Go to standby and unassert ATN Transfer the contents of datct to the d0 register Load a0 register with the address of datbuf Call DSEND to write the data When the...

Page 132: ...f L 2 movb ola cmdbuf L 3 bsr CMD Call CMD to address GPIB devices movb GTS AUXMR L Go to standby and drop ATN movw datct d0 Preset d0 register with byte count movl datbuf a0 Preset a0 register with address of buffer bsr DSEND Source Handshake Data will write data WRITE1 btst DO ISR1 L Wait until last byte has been sent beq WRITE1 movb TCA AUXMR L Then take control subw 2 cmdct L Prepare to unaddr...

Page 133: ...Write a byte and increment the counter Check for a GPIB error Loop until all bytes are transferred On an error set d0 to 1 Status on return d0 register contains number of bytes sent or 1 if an error occurred 68000 Code Comments CSEND clrw count L Initialize count variable CSEND1 btst CO ISR2 L Wait till CDOR is empty beq CSEND1 cmpw count d0 Have all commands been sent beq CSEND3 Yes addw 1 count ...

Page 134: ...e less than 256 Interruption of any data transfer in progress is acceptable Actions Issue TCA command to assert ATN in case the GPIB 1014P is at standby Load the d0 register with the address of cmdbuf Load a0 with the number of commands Call CSEND to transmit the bytes Status on return GPIB 1014P is Active Controller GPIB devices are programmed as implied by command bytes 68000 Code Comments CMD m...

Page 135: ...d in tctadr Actions Send TCA command to take control in case the GPIB 1014P is at standby Set up the command buffer and command count Call CMD to send the command bytes Status on return The GPIB 1014P is Idle Controller 68000 Code Comments PASSC movb TCA AUXMR L Take control in case at standby movb UNT cmdbuf L Set up the command buffer movb UNL cmdbuf L 1 movb tctadr cmdbuf L 2 movb TCT cmdbuf L ...

Page 136: ... National Instruments Corporation D 1 GPIB 1014P User Manual Appendix D Multiline Interface Messages The following tables are multiline interface messages sent and received with ATN TRUE ...

Page 137: ...0F 017 15 SI 2F 057 47 MLA15 10 020 16 DLE 30 060 48 0 MLA16 11 021 17 DC1 LLO 31 061 49 1 MLA17 12 022 18 DC2 32 062 50 2 MLA18 13 023 19 DC3 33 063 51 3 MLA19 14 024 20 DC4 DCL 34 064 52 4 MLA20 15 025 21 NAK PPU 35 065 53 5 MLA21 16 026 22 SYN 36 066 54 6 MLA22 17 027 23 ETB 37 067 55 7 MLA23 18 030 24 CAN SPE 38 070 56 8 MLA24 19 031 25 EM SPD 39 071 57 9 MLA25 1A 032 26 SUB 3A 072 58 MLA26 1B...

Page 138: ... MTA13 6D 155 109 m MSA13 PPE 4E 116 78 N MTA14 6E 156 110 n MSA14 PPE 4F 117 79 O MTA15 6F 157 111 o MSA15 PPE 50 120 80 P MTA16 70 160 112 p MSA16 PPD 51 121 81 Q MTA17 71 161 113 q MSA17 PPD 52 122 82 R MTA18 72 162 114 r MSA18 PPD 53 123 83 S MTA19 73 163 115 s MSA19 PPD 54 124 84 T MTA20 74 164 116 t MSA20 PPD 55 125 85 U MTA21 75 165 117 u MSA21 PPD 56 126 86 V MTA22 76 166 118 v MSA22 PPD 5...

Page 139: ... messages Talkers Listeners and Controllers A Talker sends data messages to one or more Listeners The Controller manages the flow of information on the GPIB by sending commands to all devices Devices can be Listeners Talkers and or Controllers A digital voltmeter for example is a Talker and may be a Listener as well The GPIB is a bus like an ordinary computer bus except that the computer has its c...

Page 140: ...ce on the bus the System Controller can make itself the CIC The GPIB interface board is usually the System Controller GPIB Signals and Lines The interface system consists of 16 signal lines and eight ground return or shield drain lines The 16 signal lines are divided into the following three groups Eight data lines Three handshake lines Five interface management lines Data Lines The eight data lin...

Page 141: ...IFC line to initialize the bus and become CIC REN remote enable The System Controller drives the REN line which is used to place devices in remote or local program mode SRQ service request Any device can drive the SRQ line to asynchronously request service from the Controller EOI end or identify The EOI line has two purposes The Talker uses the EOI line to mark the end of a message string The Cont...

Page 142: ...is a TTL low level 0 8V and when DAV is false it is a TTL high level 2 0V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DIO5 DIO6 DIO7 DIO8 REN GND TW PAIR W DAV GND TW PAIR W NRFD GND TW PAIR W NDAC GND TW PAIR W IFC GND TW PAIR W SRQ GND TW PAIR W ATN SIGNAL GROUND DIO1 DIO2 DIO3 DIO4 EOI DAV NRFD NDAC IFC SRQ ATN SHIELD Figure E 1 GPIB Connector and the Signal Assignment ...

Page 143: ...Appendix E Multiline Interface Messages National Instruments Corporation E 5 GPIB 1014P User Manual Figure E 2 Linear Configuration ...

Page 144: ... that the GPIB was designed for the physical distance between devices and the number of devices on the bus are limited The following restrictions are typical A maximum separation of four meters between any two devices and an average separation of two meters over the entire bus A maximum total cable length of 20 m No more than 15 devices connected to each bus with at least two thirds powered on ...

Page 145: ...vailable from National Instruments and other manufacturers for use when these limits must be exceeded Related Document For more information on topics covered in this section consult IEEE Standard Digital Interface for Programmable Instrumentation IEEE 488 Std 488 1978 IEEE 488 1 Std 488 1987 and IEEE 488 2 Std 488 1987 ...

Page 146: ...nual for functions remote messages local messages states bits registers integrated circuits system functions and VMEbus operations and signals The mnemonic types in the key that follows are abbreviated to mean the following B Bit F Function IC Integrated Circuit LM Local Message LS Local Signal R Register RM Remote Message SF System Function ST State VBO VMEbus Operation VBS VMEbus Signal ...

Page 147: ...BO Address Only Cycle ADR R Address Register ADR0 R Address Register 0 ADR1 R Address Register 1 ADSC B Address Status Change ADSR R Address Status Register AH ST Acceptor Handshake AIDS ST Acceptor Idle State AM VBS Address Modifier ANRS ST Acceptor Not Ready State APRS ST Affirmative Poll Response State APT B Address Pass Through Bit APT IE B Enable Interrupt on Address Pass Through Bit ARS B Ad...

Page 148: ...h 0 CPWS ST Controller Parallel Poll Wait State CSBS ST Controller Standby State CSHS ST Controller Standby Hold State CSNS ST Controller Service Not Requested State CSRS ST Controller Service Requested State CSWS ST Controller Synchronous Wait State CTRS ST Controller Transfer State C function D DAB RM Data Byte DAC RM Data Accepted dacr DAC holdoff release DAV RM Data Valid DC F Device Clear DCA...

Page 149: ...tate DTIS ST Device Trigger Idle State E END RM End END IE B Enable Interrupt on End Received Bit END RX B End Received Bit EOI B End or Identify Bit EOI RM End or Identify EOS RM End of String EOS 7 0 B End of String Bits 7 through 0 EOSR R End of String Register ERR B Error Bit ERR RM Error ERR IE B Enable Interrupt on Error Bit EV LS Enable Vector G GET RM Group Execute Trigger GND VBS Ground G...

Page 150: ...dressed State L function LAG RM Listener Address Group LDTACK LS Local DTACK LE F Listener Extended LIDS ST Listener Idle State LLO RM Local Lockout LMR B Local Master Reset Bit LOCS ST Local State LOK B Lockout Bit LOKC B Lockout Change Bit LOKC IE B Enable Interrupt on Lockout Change Bit lon B Listen Only Bit lon LM Listen Only LPAS B Listener Primary Addressed State Bit LPAS ST Listener Primary...

Page 151: ...all status flags PPAS ST Parallel Poll Active State PPC RM Parallel Poll Configure PPD RM Parallel Poll Disable PPE RM Parallel Poll Enable PPIS ST Parallel Poll Idle State PPR RM Parallel Poll Response PPSS ST Parallel Poll Standby Active PPU RM Parallel Poll Unconfigure PUCS ST Parallel Poll Unaddressed to Configure State R rdy LM Ready for next message REM B Remote Bit REMC B Remote Change Bit ...

Page 152: ... Source Idle Wait State SNAS ST System Control Not Active State SP F Serial Poll scanning flags SPAS ST Serial Poll Active State T function SPD RM Serial Poll Disable SPE RM Serial Poll Enable SPEOI B Send Serial Poll End Or Indentify Bit SPIS ST Serial Poll Idle State SPMR R Serial Poll Mode Register SPMS B Serial Poll Mode State Bit SPMS ST Serial Poll Mode State SPSR R Serial Poll Status Regist...

Page 153: ...TE F Extended Talk TIDS ST Talker Idle State TLC IC Talker Listener Controller GPIB Adapter TLC CS LS TLC Chip Reset TLC WR LS TLC Write ton B Talker Only Bit ton LM Talker Only TPAS B Talker Primary Addressed State Bit TPAS ST Talker Primary Addressed State TPIS ST Talker Primary Idle State TRI B Three State Timing Bit TRM 1 0 B Transmit Receive Mode Bits 1 through 0 U U B Unconfigure Bit UAT VBO...

Page 154: ... p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Fax Number Australia 03 879 9422 03 879 9179 Austria 0662 435986 0662 437010 19 Belgium 02 757 00 20 02 757 03 11 Denmark 45 76 26 00 45 76 71 11 Finland 90 527 2321 90 502 2930...

Page 155: ...ficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used Natio...

Page 156: ...8M Software Version Number on Distribution Medium National Instruments board installed GPIB 1014 GPIB 1014D GPIB 1014P or GPIB 1014DP _________________________________________________________ GPIB 1014 Revision Hardware Settings Base I O Address Interrupt Request Line DMA Channel 1st GPIB 1014 2nd GPIB 1014 Software Settings Base I O Address Interrupt Vector Number DMA Channel gpib0 gpib1 Other Pr...

Page 157: ... Type of other boards installed and their respective hardware settings Board Type Base I O Address Interrupt Level DMA Channel ...

Page 158: ...Part Number 370944A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53...

Page 159: ... 1 0 Address Mode Bits 1 through 0 4 23 to 4 24 ADMR See Address Mode Register ADMR ADR See Address Register 0 ADR ADR0 See Auxiliary Register 0 ADR0 ADR1 See Address Register 1 ADR1 ADSC Addressed Status Change Bit 4 17 to 4 18 ADSC IE Addressed Status Change Interrupt Enable Bit 4 17 to 4 18 ADSR See Address Status Register ADSR AH Acceptor Handshake 4 6 APT Address Pass Through Bit 4 9 to 4 10 ...

Page 160: ... codes for 4 29 description 4 34 CLK 3 0 Clock Bits 3 through 0 4 35 clock and reset circuitry definition 2 9 operation 6 2 CNT 2 0 Control Code Bits 2 through 0 4 27 to 4 34 CO Command Out Bit 4 16 CO IE Command Out Interrupt Enable Bit 4 16 Command Data Out Register CDOR 4 7 Command Pass Through Register CPTR 4 25 to 4 26 COMMAND SEND CSEND sample program C 17 commands auxiliary command summary ...

Page 161: ...mple program C 13 to C 14 data transfer features 2 5 DAV data valid signal E 3 DCL Device Clear command 4 26 DEC Device Clear Bit 4 11 DEC IE Device Clear Interrupt Enable Bit 4 11 DET Device Execute Trigger Bit 4 10 DET IE Device Execute Trigger Interrupt Enable Bit 4 10 DHDC DAC Holdoff on DCAS Bit 4 42 DHDT DAC Holdoff on DTAS Bit 4 42 DI Data In Bit 4 12 to 4 13 DI IE Data In Interrupt Enable ...

Page 162: ...cute Parallel Poll command codes for 4 29 description 4 34 F features of GPIB 1014P 1 1 Finish Handshake FH command codes for 4 28 description 4 31 G GET Group Execute Trigger command 4 25 Go To Standby command codes for 4 29 description 4 32 GPIB cable shield grounding 3 8 GPIB Controller See Controller function GPIB 1014P block diagram 2 8 capabilities 2 10 to 2 12 contents of kit 1 3 definition...

Page 163: ... interface clear line E 3 Immediate Execute Pon command codes for 4 28 description 4 30 IMR1 See Interrupt Mask Register 1 IMR1 initialization of GPIB 1014P 5 1 to 5 2 INITIALIZE INIT sample program C 5 to C 6 installation cabling 3 10 to 3 11 hardware installation tests 7 2 to 7 3 prerequisites for 3 1 unpacking the GPIB 1014P 1 3 to 1 4 verification of system compatibility 3 9 verification testi...

Page 164: ...uration VMEbus interrupt priority code 3 5 to 3 6 interrupt request line selection 3 5 overview 3 5 Interrupt Mask Register 1 IMR1 4 8 to 4 13 interrupt status ID vector selection configuring 3 7 Interrupt Status Register 1 ISR1 4 8 to 4 13 Interrupt Status Register 2 ISR2 4 14 to 4 18 interrupter definition 2 9 description of 2 4 interrupter logic 6 3 to 6 4 programming considerations 5 7 to 5 8 ...

Page 165: ...ressed State Bit 4 20 M messages types of E 1 µPD7210 interface registers chart 4 4 MJMN Major Minor Bit 4 21 MLA My Listen Address command 4 26 mnemonics for registers alphabetical list with definitions F 1 to F 8 clues to understanding 4 3 MSA PPD My Secondary Address or Parallel Poll Disable command 4 26 MSA PPE My Secondary Address or Parallel Poll Enable command 4 26 MTA My Talk Address comma...

Page 166: ...ommand 4 25 PPR See Parallel Poll Register PPR PPU Parallel Poll Unconfigure command 4 26 programming Controller function becoming controller in charge CIC and active controller 5 2 to 5 3 going from active to idle 5 4 going from active to standby 5 3 going from standby to active 5 4 sending remote multiline messages commands 5 3 initialization 5 1 to 5 2 interrupts 5 7 to 5 8 parallel polls 5 9 t...

Page 167: ...ister 2 ISR2 4 14 µPD7210 interface registers chart 4 4 overview 4 3 to 4 4 Serial Poll Mode Register SPMR 4 19 Serial Poll Status Register SPSR 4 19 writing to hidden registers 4 5 mnemonics for 4 3 register map 4 1 to 4 2 size of 4 2 terminology related to 4 2 to 4 3 REM Remote Bit 4 16 REMC Remote Change Bit 4 17 REMC IE Remote Change Interrupt Enable Bit 4 17 REMOTE ENABLE REN sample program C...

Page 168: ...description 4 34 Set Parallel Poll Flag command codes for 4 28 description 4 32 Set REN command codes for 4 29 description 4 34 SH Source Handshake 4 7 signals and lines data lines E 2 GPIB connector and signal assignment illustration E 4 GPIB 1014P pin assignment on VMEbus connector P1 3 9 to 3 10 handshake lines E 2 DAV data valid E 3 NDAC not data accepted E 2 NRFD not ready for data E 2 interf...

Page 169: ...3 switches See jumpers and switches system reset clock and reset circuitry 6 2 during initialization 5 1 to 5 2 T TA Talker Active Bit 4 21 Take Control Asynchronously Pulsed command codes for 4 28 description 4 32 Take Control Synchronously command codes for 4 28 description 4 33 Take Control Synchronously on End command codes for 4 28 description 4 33 Talker Listener Controller TLC See also Cont...

Page 170: ...40 to 4 41 Trigger command codes for 4 28 description 4 31 TRM 1 0 Transmit Receive Mode Bits 1 through 0 4 22 to 4 23 troubleshooting test procedures hardware installation tests 7 2 to 7 3 interpreting test procedures 7 1 overview 6 5 7 1 verification of GPIB 1014P before installation 3 10 U U Parallel Poll Unconfigure Bit 4 36 UNL Unlisten command 4 26 unpacking the GPIB 1014P 1 3 to 1 4 UNT Unt...

Page 171: ...nstruments Corporation Index 13 GPIB 1014P User Manual signals chart 2 1 to 2 2 slave addressing 2 2 to 2 3 slave data 2 3 W WRITE sample program C 15 to C 16 X X Don t Care Bit 4 43 XEOS Transmit END with EOS Bit 4 38 ...

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