Theory of Operation
Section Six
GPIB-1014P User Manual
6-4
© National Instruments Corporation
When the TLC drives its INT line, the interrupter immediately pulls one of the interrupt request
lines low (see VMEbus Interrupt Request Line in Section Three). The F85 comparator compares
the address lines A01 through A03 with the priority you select on U28 and sets the A=B output
high if there is a match during an interrupt acknowledge cycle.
Note:
The priority you select must match the interrupt request line (see Interrupt Request Priority
in Section Three).
The VME signal AS is delayed 25 nsec to allow the comparator output to stabilize. This delayed
signal then clocks the result of the comparison. AS is delayed an additional 25 nsec before asserting
IACKOUT* or responding with a STATUS/ID byte. This additional delay assures that the output
of the flip-flop will be stable before the logic selects to either pass the interrupt of the comparison or
respond with a status byte.
If the output of the flip-flop is latched true, the interrupter is set to respond with a STATUS/ID byte.
The interrupter waits for IACKIN and DS0 to become true, as well as for the signal AS that has
been delayed 50 nsec, and makes certain that the VME signal DTACK* has been released. At this
time, an enable vector signal, EV, is latched in order to enable the data bus transceiver for the entire
transfer cycle. The complement, EV*, enables an F244 to drive the VME data bus with a
STATUS/ID byte (which you determine by setting onboard switches as described in Interrupt
Status/ID Byte in Section Three). Two inverters delay EV* to allow for data set-up on the
VMEbus; EV* then signals the DTACK* Asset/Release circuitry, via IDTACK*, to drive
DTACK* true.
EV and EV* are held true until the interrupt handler releases DS0*. The rise of EV* releases the
IRQ* line. Therefore, the GPIB-1014P is a Release On AcKnowledge (ROAK) interrupter.
Note: Even though the VMEbus interrupt request line is no longer driven, the TLC INT line
remains asserted until it is cleared in the interrupt service routine by reading the appropriate
interrupt status register (ISR1 or ISR2). The appropriate interrupt status register must be
read to enable further interrupts from the GPIB-1014P.
The DTACK* assert/release circuitry releases DTACK* after the F245 ceases driving the data bus
(DEN*=1), IDTACK* is high, and DS1* is released.
If the address lines A01 through A03 do not match the indicated priority of the GPIB-1014P, the
Q* output of the flip-flop is latched high, indicating that IACKOUT* is to be asserted. After
IACKIN and the delayed AS are received high, the VMEbus signal IACKOUT* is driven low.
IACKOUT* is released within 30 nsec of AS* being released.
GPIB Interface
The GPIB-1014P is interfaced to the GPIB using an NEC
µ
PD7210 Talker/Listener/Controller
(TLC) large scale integrated circuit. The TLC contains most of the logic circuitry needed to
program, control, and monitor the GPIB interface functions that are implemented by the GPIB-
1014P. Access to these functions is through eight read-only registers and 13 write-only registers,
five of which are indirectly addressed. These registers occupy a block of 16 memory addresses
(eight consecutive odd addresses).
