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Section Four
Register Bit Descriptions
© National Instruments Corporation
4-23
GPIB-1014P User Manual
Address Mode Register (ADMR)
VMEbus Address:
Base A 9 (hex)
Attributes:
Write Only
W
7
6
5
4
3
2
1
ton
1on
TRM1
TRM0
0
0
ADM1
ADM0
0
Bit
Mnemonic
Description
7w
ton
Talk Only Bit
Setting ton programs the TLC to be a GPIB Talker. If ton is set, the lon,
ADM1, and ADM0 bits must be cleared. This method must be used in
place of the addressing method when the TLC will be only a Talker.
Note: Clearing ton does not by itself take the TLC out of GPIB Talker
Active state (TACS). It is also necessary to execute the Chip
Reset or Immediate Execute pon auxiliary command.
6w
lon
Listen Only Bit
Setting lon programs the TLC to be a GPIB Listener. If lon is set, ton,
ADM1, and ADM0 should be cleared.
Note: Clearing lon does not by itself take the TLC out of Listener Active
state (LACS). It is also necessary to execute the Chip Reset or
Immediate Execute pon auxiliary command.
5-4w
TRM[1-0]
Transmit/Receive Mode Bits 1 through 0
TRM1 and TRM0 control the function of the TLC T/R2 and T/R3 output
pins in the following manner:
TRM1
TRM0
T/R2
T/R3
0
0
EOI OE
TRIG
0
1
CIC
TRIG
1
0
CIC
EOI OE
1
1
CIC
PE