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Register Bit Descriptions
Section Four
GPIB-1014P User Manual
4-18
© National Instruments Corporation
Bit
Mnemonic
Description
2w
LOKC
Lockout Change Bit
2r
LOKC IE
Lockout Change Interrupt Enable Bit
LOKC is set by:
any change in LOK
LOKC is cleared by:
pon + (Read ISR2)
Notes:
LOK:
ISR2[5]r
pon:
power on reset
Read ISR2: Bit is cleared immediately after it is read.
LOKC is set whenever there is a change in the LOK bit, ISR2[5]r,
(REMS + RELS).
1w
REMC
Remote Change Bit
1r
REMC IE
Remote Change Interrupt Enable Bit
REMC is set by:
any change in REM
REMC is cleared by:
pon + (Read ISR2)
Notes:
REM:
ISR2[4]r
pon:
power on reset
Read ISR2: Bit is cleared immediately after it is read.
REMC is set whenever there is a change in the REM bit, ISR2[4]r,
(REMS + RELS).
0r
ADSC
Addressed Status Change Bit
0w
ADSC IE
Addressed Status Change Interrupt Enable Bit
ADSC is set by:
[(any change in TA) + (any change in LA)
+ (any change in CIC) + (any change in MJMN)] & -(lon + ton)
ADSC is cleared by:
pon + (Read ISR2)