Section Four
Register Bit Descriptions
© National Instruments Corporation
4-9
GPIB-1014P User Manual
Interrupt Status Register 1 (ISR1)
VMEbus Address:
Base A 3 (hex)
Attributes:
Read Only,
Bits are cleared when read
Interrupt Mask Register 1 (IMR1)
VMEbus Address:
Base A 3 (hex)
Attributes:
Write Only
CPT
CPT IE
APT
APT IE
DET
DET IE
END RX
END IE
DEC
DEC IE
ERR
ERR IE
DO
DO IE
DI
DI IE
R
W
7
6
5
4
3
2
1
0
ISR1 is composed of eight interrupt status bits. IMR1 is composed of eight interrupt enable bits
which directly correspond to the interrupt status bits in ISR1. As a result, ISR1 and IMR1 service
eight possible interrupt conditions, where each condition has an interrupt status bit and an interrupt
enable bit associated with it. If the Interrupt Enable bit is true when the corresponding status
condition or event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared
by the TLC regardless of the status of the interrupt enable bits in IMR1. If an interrupt condition
occurs at the same time ISR1 is being read, the TLC holds off setting the corresponding status bit
until the read has finished.
Bit
Mnemonic
Description
7r
CPT
Command Pass-Through Bit
7w
CPT IE
Command Pass-Through Interrupt Enable Bit
CPT is set on:
[UCG + ACG & (TADS + LADS)]
& undefined & ACDS & (CPTENAB)
+ UDPCF & SCG & ACDS & CPT ENAB
CPT is cleared by:
pon + (Read ISR1)
Notes:
UCG:
GPIB Universal Command Group message
ACG:
GPIB Addressed Command Group message
TADS:
GPIB Talker Addressed State
LADS:
GPIB Listener Addressed State
defined:
GPIB command automatically recognized and executed
by TLC
