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Register Descriptions
Section Four
GPIB-1014P User Manual
4-36
© National Instruments Corporation
Hidden Registers
The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is
loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred
to the hidden register. The hidden registers cannot be read, and in some cases the contents can only
be set; that is, they can be cleared or reset to initialized conditions only by issuing the Chip Reset
auxiliary command, or by a pon. Figure 4-2, earlier in this section, shows the five hidden registers
and illustrates how they are loaded with data from the AUXMR.
Internal Counter Register (ICR)
VMEbus Address:
Base A B (hex)
AUXMR Control Code: 001 (Binary, Bits 7 - 5)
Attributes:
Write Only,
Accessed through AUXMR
4
3
2
1
0
W
0
CLK3
CLK2
CLK1
CLK0
Bit
Mnemonic
Description
4w
0
Reserved Bit
Write zero to this bit.
3-0w
CLK[3-0]
Clock Bits 3 though 0
The contents of the ICR are used to divide internal counters that generate
TLC state change delay times used by the IEEE-488 specification. The
most familiar of these times, T1, is the minimum delay between placing
the data or command bytes on the GPIB DIO lines and asserting DAV.
These delay times vary depending on the type of transfer in progress and
the value of the AUXRB bit TRI.
For proper operation, ICR should be set to eight because the TLC is
clocked at 8 MHz.