Section Four
Register Bit Descriptions
© National Instruments Corporation
4-13
GPIB-1014P User Manual
Bit
Mnemonic
Description
Notes:
TACS:
GPIB Talker Active State
SDYS:
GPIB Source Delay State
DAC:
GPIB Data Accepted message
RFD:
GPIB Ready For Data message
SIDS:
GPIB Source Idle State
(Write CDOR):
Bit is set immediately after writing to the
Command/Data Out Register
SDYS->SIDS:
Transition from GPIB Source Delay State to Source
Idle State
pon:
power on reset
Read ISR1:
Bit is cleared immediately after it is read.
The ERR bit indicates that the contents of the CDOR have been lost.
ERR is set when data is sent over the GPIB without a specified Listener
or when a byte is written to the CDOR during SIDS or during the SDYS
to SIDS transition.
1r
DO
Data Out Bit
1w
DO IE
Data Out Interrupt Enable Bit
DO is set as:
(TACS & SGNS) becomes true
DO is cleared by:
(Read ISR1) + -(TACS) + -(SGNS)
Notes:
TACS: GPIB Talker Active State
SGNS:GPIB Source Generate State
Read ISR1:
Bit is cleared immediately after it is read.
The DO bit indicates that the TLC is ready to accept another data byte
from the VMEbus for transmission onto the GPIB when the TLC is the
GPIB Talker. The DO bit is cleared when a byte is written to the CDOR
and also when the TLC ceases to be the Active Talker.
0r
DI
Data In Bit
0w
DI IE
Data In Interrupt Enable Bit
DI is set by:
LACS & ACDS & -(Continuous Mode)
