Section Four
Register Bit Descriptions
© National Instruments Corporation
4-15
GPIB-1014P User Manual
Interrupt Status Register 2 (ISR2)
VMEbus Address:
Base A 5 (hex)
Attributes:
Read Only,
Bits are cleared when read
Interrupt Mask Register 2 (IMR2)
VMEbus Address:
Base A 5 (hex)
Attributes:
Write Only
R
7
6
5
4
3
2
1
0
INT
0
SRQI
SRQI IE
LOK
DMAO
REM
DMAI
CO
CO IE
LOKC
LOKC IE
REMC
REMC IE
ADSC
ADSC IE
W
ISR2 consists of six interrupt status bits and two TLC internal status bits. IMR2 consists of five
interrupt enable bits and two TLC internal control bits. If the Interrupt Enable bit is true when the
corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in
ISR2 are set and cleared regardless of the status of the bits in IMR2. If a condition occurs which
requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read, the TLC
holds off setting or clearing the bit or bits until the read is finished.
Bit
Mnemonic
Description
7r
INT
Interrupt Bit
This bit is the logical OR of all the enabled interrupt status bits in both
ISR1 and ISR2, each one ANDed with its interrupt enable bit (refer
below). There is no corresponding mask bit for INT. If the INT=1, the
INT output pin of the TLC, signal GPIB IR, is asserted.
Note: Program the INT output pin of the TLC to be active high; see
description of AUXRB.
INT is set by:
(CPT & CPT IE) + (APT & APT IE) +
(DET & DET IE) + (ERR & ERR IE) +
(END RX & END IE) + (DEC & DEC IE) +
(DO & DO IE) + (DI & DI IE) +
(SRQI & SRQI IE) + (REMC & REMC IE) +
(CO & CO IE) + (LOKC & LOKC IE) +
(ADSC & ADSC IE)
