283
FX
3U
/FX
3UC
Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
11 Rotation and Shift Operation – FNC 30 to FNC 39
11.7 FNC 36 – WSFR / Word Shift Right
11
FN
C30-
FN
C39
R
o
ta
tion and
Sh
ift
12
FNC
4
0
-FNC49
D
a
ta
Op
e
ra
tio
n
13
FNC5
0
-FNC5
9
H
igh Speed
Pr
ocessi
ng
14
FM
C6
0
-F
NC6
9
H
and
y
In
st
ru
cti
o
n
15
FNC7
0
-FNC7
9
Ex
te
rn
a
l F
X
I
/O
D
evi
ce
16
FNC8
0
-FNC8
9
Ext
e
rnal
FX
D
evi
ce
17
F
N
C1
00
-F
NC
10
9
Da
ta
Tr
ansf
e
r 2
18
FN
C
110-FN
C
13
9
Fl
oat
ing P
o
in
t
19
FN
C
140-FN
C
149
Da
ta
O
per
at
io
n
2
20
FN
C
15
0-F
N
C
159
P
o
si
tioni
ng
C
ont
ro
l
11.7
FNC 36 – WSFR / Word Shift Right
Outline
This instruction shifts word devices with "n1" data length rightward by "n2" words.
1. Instruction format
2. Set data
3. Applicable devices
Explanation of function and operation
1. 16-bit operation (WSFR and WSFRP)
For "n1" word devices starting from
, "n2" words are shifted rightward ([1] and [2] shown below).
After shift, "n2" words starting from
are shifted to "n2" words starting from [
+n1-n2] ([3] shown
below).
Operand Type
Description
Data Type
Head device number to be stored to the shift data after rightward shift
16-bit binary
Head word device number storing data to be shifted rightward
16-bit binary
n1
Word data length of the shift data n2
≤
n1
≤
512
16-bit binary
n2
Number of words to be shifted rightward n2
≤
n1
≤
512
16-bit binary
Oper-
and
Type
Bit Devices
Word Devices
Others
System User
Digit Specification
System User
Special
Unit
Index
Con-
stant
Real
Number
Charac-
ter String
Pointer
X Y M T C S D
.b KnX KnY KnM KnS
T
C
D
R U
\G
V
Z Modify K
H
E
"
"
P
3
3
3
3
3 3 3 3
3
3
3
3
3
3 3 3 3
3
3
n1
3 3
n2
3 3
3 3
P
FNC 36
WSFR
16-bit Instruction
9 steps
Mnemonic
Operation Condition
Continuous
Operation
Pulse (Single)
Operation
WSFR
WSFRP
−
−
Mnemonic
Operation Condition
32-bit Instruction
S
D
S
D
D
S
D
Command
input
FNC 36
WSFRP
n1
n2
D
S
+2
+8
+2
n2 (in the case of "n2=3")
n1 (in the case of "n1=9")
[1]
Overflow (data to
be deleted)
+1
D
+7 +6 +5 +4 +3
D
+1
+8
D
+7 +6 +5
D
+4 +3 +2 +1
+8 to +3 before shift (n2=3)
D
[3] Copy
[2]
"n2" bits are
shifted rightward
(n2=3).
+2 to before shift (n2=3)
S
Before
execution
After
execution
S
S
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
S
D