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Rev.1.0
The SIO Transmit/Receive Mode Registers consist of the bits to select serial I/O operation mode,
data format, and the function to be used during communication.
The SIO Transmit/Receive Mode Registers must always be set before serial I/O starts operation.
To modify the register contents after the SIO started sending or receiving, check to see that the
transmit or receive operation is completed and disable transmit/receive operations (by clearing the
SIO Transmit Control Register transmit enable bit and the SIO Receive Control Register receive
enable bit to 0) before setting the register.
(1) SMOD (serial I/O mode select) bits (D8-D10)
These bits select serial I/O operation mode.
(2) CKS (internal/external clock select) bit (D11)
This bit is effective when CSIO mode is selected. When UART mode is selected, this bit has no
effect and the SIO operates with an internal clock.
(3) STB (stop bit length select) bit (D12)
This bit is effective when in UART mode. Use this bit to select the length of the stop bit that
indicates the end of the transmit data. Setting this bit to 0 selects one stop bit; setting this bit to 1
selects two stop bits.
During clock synchronized mode, the content of this bit has no effect.
(4) PSEL (odd/even parity select) bit (D13)
This bit is effective when in UART mode. When parity is enabled (D14 = 1), use this bit to select
the parity attribute (odd or even). Setting this bit to 0 selects odd parity; setting this bit to 1 selects
even parity.
When parity is disabled (D14 = 0) and when in clock synchronized mode, the content of this bit
has no effect.
(5) PEN (parity enable) bit (D14)
This bit is effective when in UART mode. Setting this bit to 1 enables parity, so that a parity bit is
added immediately after the data bits of transmit data. When receiving data, the received data is
checked for parity.
The parity bit added to the transmit data is automatically determined to be to 0 or 1 so that the
attribute of the result derived by adding the number of 1's in the data bits and the content of the
parity bit matches the attribute selected with the odd/even parity select bit (D13).
Figure 12.2.4 shows an example of a data format where parity is enabled.
(6) SEN (sleep select) bit (D15)
This bit is effective when in UART mode. When the sleep function is enabled by setting this bit to
1, data is latched into the UART Receive Buffer Register only when the most significant bit (MSB)
of the received data = 1.
SERIAL I/O
12.2 Serial I/O Related Registers
Summary of Contents for 32172
Page 20: ... This is a blank page 16 ...
Page 21: ...1 1 Overview 1 2 Block Diagram 1 3 Pin Functions 1 4 Pin Layout CHAPTER 1 CHAPTER 1 OVERVIEW ...
Page 44: ...1 1 24 Rev 1 0 This is a blank page Overview 1 4 Pin Layout ...
Page 58: ...2 2 14 Rev 1 0 This is a blank page CPU 2 6 Data Formats ...
Page 122: ...4 4 26 Rev 1 0 This is a blank page EIT 4 13 Precautions on EIT ...
Page 200: ...7 7 6 Rev 1 0 This is a blank page RESET 7 4 Precautions to Be Taken Immediately after Reset ...
Page 298: ...9 9 58 Rev 1 0 This is a blank page DMAC 9 4 Precautions on Using DMAC ...
Page 776: ...19 19 10 Rev 1 0 RAM BACKUP MODE 19 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 782: ...20 20 6 Rev 1 0 OSCILLATION CIRCUIT 20 2 Clock Generator Circuit This is a blank page ...
Page 856: ...23 23 26 Rev 1 0 This is a blank page ELECTRICAL CHARACTERISTICS 23 6 AC Characteristics ...
Page 857: ...24 1 A D Conversion Characteristics CHAPTER 24 CHAPTER 24 STANDARD CHARACTERISTICS ...
Page 859: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 865: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...