Mitsubishi 32172, User Manual

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9
9-51
Rev.1.0
9.3.5 Gaining and Releasing Control of the Internal Bus
Gaining and releasing control of the internal bus is arbitrated by a single-transfer method DMA on
all channels. With the single-transfer method DMA, the DMA controller gains control of the internal
bus when a DMA transfer request is accepted and returns bus control to the CPU after executing
one session of DMA transfer (one read cycle + one write cycle of the internal peripheral clock). The
diagram below shows the behavior of the single-transfer method DMA.
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
9.3.6 Transfer Unit
The number of data bits transferred in one DMA transfer (8 or 16 bits), referred to as the transfer
unit, is selected for each channel with the TSZSL (DMA transfer size select) bit.
9.3.7 Transfer Count
The transfer count, or the number of times a DMA transfer is performed, is set for each channel by
using the DMA Transfer Count Register.
DMA transfer can be performed up to 256 times. The value of the transfer count register is
decremented by one for each transfer unit transferred.
In ring buffer mode, the DMA Transfer Count Register operates in free-running mode, with its set
value ignored.
DMAC
9.3 Functional Description of DMAC
One session of
DMA transfer
DMAC
CPU
Internal bus
arbitration
(Request from
the DMAC)
Internal
bus
R: Read
W: Write
R W R W R W
Request Granted Request Granted Request Granted
One session of
DMA transfer
One session of
DMA transfer
Relinquished Relinquished Relinquished