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15-6

Rev.1.0

+0 address

+1 address

D7 D8

D15

H'0080 1888

H'0080 188A

H'0080 188C

H'0080 188E

H'0080 18A0

H'0080 18A4

H'0080 18A6

H'0080 18A8

H'0080 18AA

H'0080 18AC

H'0080 18B0

H'0080 18B2

H'0080 18B4

H'0080 18B6

Address

ABDLT1 Register (ABDLT1)

H'0080 1880

H'0080 1886

H'0080 1882

H'0080 1884

Blank areas are reserved for future use.

H'0080 18A2

Prescaler Register 1C(PRS1C)

SMSB Control Register 1(SMSBCR1)

TEP1P Control Register (TEP1PCR)

TEP1M Control Register (TEP1MCR)

SNEWLT1 Register (SNEWLT1)

FDLT1 Register (FDLT1)

PRLT1 Register (PRLT1)

PITCHL1 Register (PITCHLT1)

MRLT1 Register (MRTL1)

PNEWLT1 Register (PNEWLT1)

POLDT1 Register (POLDLT1)

MNEWLT1 Register (MNEWLT1)

MOLDLT1 Register (MOLDLT1)

PSUBLT1 Register (PSUBLT1)

MSUBLT1 Register (MSUBLT1)

RSUMLT1 Register (RSUMLT1)

H'0080 18AE

H'0080 18BA

TEP1P Counter (TEP1PCT)

TEP1M Counter (TEP1MCT)

PD1 Data Updating Disable Event Select Register (PDNSEL1R)

PD1 Data Updating Control Register (PDNCNT1R)

ABD1 Mask Register (ABD1MK)

S Error 1 Detection Range Select Register (SNEW1MK)

ABD1 Compare Register (ABD1CM)

PITCH1 Compare Register (PITCH1CMR)

SSLT1 Register (SSLT1)

H'0080 18B8

Note: The registers enclosed in are an intermediate register used for calculations.
Do not access these registers for read or write.

Figure 15.2.2 PD Module Register Map (2/2)

PD MODULE

15.2 PD Module Related Registers

Summary of Contents for 32172

Page 1: ...website to confirm that this is the most current document available http www infomicom maec co jp indexe htm Rev 1 0 Revision date Oct 5 2001 Mitsubishi 32 bit RISC Single chip Microcomputers M32R Family M32R ECU Series Group User s Manual 32172 32173 ...

Page 2: ...naccuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Mitsubishi Electric Corporation by various means including the Mitsubishi Semiconductor home page http www mitsubishichips com When using any or all of the information cont...

Page 3: ...Rev Date Description Page Summary REVISION HISTORY 32172 32173 GROUP USER S MANUAL 1 0 10 5 2001 First edition issued ...

Page 4: ... bits after reset are indicated each in column At read read enabled read disabled read value invalid 0 Read always as 0 1 Read always as 1 At write Write enabled Write enable conditionally include some conditions at write Write disabled Written value invalid Abit 1 2 3 4 D0 D Bit name Function W R at reset H 04 0 Not assigned 0 1 Abit 0 1 3 2 Not implemented in the shaded portion Example of repres...

Page 5: ...t in D A Converters 1 5 1 1 8 Built in Timer Arithmetic Circuits for PD Phase Digital Sensors 1 6 1 1 9 Built in Debug Function 1 6 1 2 Block Diagram 1 7 1 3 Pin Functions 1 10 1 4 Pin Layout 1 18 CHAPTER 2 CPU 2 1 CPU Registers 2 2 2 2 General purpose Registers 2 2 2 3 Control Registers 2 3 2 3 1 Processor Status Word Register PSW CR0 2 4 2 3 2 Condition Bit Register CBR CR1 2 5 2 3 3 Interrupt S...

Page 6: ...3 9 3 4 2 SFR Special Function Register Area 3 9 3 5 EIT Vector Entry 3 35 3 6 ICU Vector Table 3 36 3 7 Precautions on Address Space 3 38 CHAPTER 4 EIT 4 1 Outline of EIT 4 2 4 2 EIT Events 4 3 4 2 1 Exceptions 4 3 4 2 2 Interrupts 4 3 4 2 3 Trap 4 3 4 3 EIT Processing Procedure 4 4 4 4 EIT Processing Mechanism 4 6 4 5 Accepting EIT Events 4 7 4 6 Saving and Restoring PC and PSW 4 8 4 7 EIT Vecto...

Page 7: ...Vector Register 5 7 5 3 2 Interrupt Mask Register 5 8 5 3 3 SBI System Break Interrupt Control Register 5 9 5 3 4 Interrupt Control Registers 5 10 5 4 ICU Vector Table 5 14 5 5 Description of Interrupt Operation 5 17 5 5 1 Accepting Interrupts from Internal Peripheral I O 5 17 5 5 2 Processing of Internal Peripheral I O Interrupts by Handler 5 20 5 6 Description of System Break Interrupt SBI Opera...

Page 8: ...tual flash Emulation Function 6 38 6 7 1 Virtual Flash Emulation Areas 6 40 6 7 2 Transition to Virtual Flash Emulation Mode 6 45 6 7 3 Application Example for Virtual Flash Emulation Mode 6 46 6 8 Connecting a Serial Programmer 6 48 6 9 Precautions on Rewriting Flash Memory 6 50 CHAPTER 7 RESET 7 1 Outline of Reset 7 2 7 2 Reset Operation 7 2 7 2 1 Power on Reset 7 2 7 2 2 Reset during Operation ...

Page 9: ... Registers 9 30 9 2 5 DMA Destination Address Registers 9 31 9 2 6 DMA Transfer Count Registers 9 32 9 2 7 DMA Interrupt Request Status Registers 9 33 9 2 8 DMA Interrupt Mask Registers 9 35 9 3 Functional Description of DMAC 9 39 9 3 1 Cause of DMA Request 9 39 9 3 2 DMA Transfer Processing Procedure 9 49 9 3 3 Starting DMA 9 50 9 3 4 Priority of DMA Channels 9 50 9 3 5 Gaining and Releasing Cont...

Page 10: ... TMS Old Measure Registers TMS0OLDMR3 0 10 49 10 3 8 Operation of TMS Measure Input 10 50 10 4 TML Input Related 32 bit Timers 10 52 10 4 1 Outline of the TML 10 52 10 4 2 Functional Outline of the TML 10 53 10 4 3 TML Related Register Map 10 54 10 4 4 TML Control Register 10 55 10 4 5 TML Counters 10 56 10 4 6 TML Measure Registers 10 57 10 4 7 TML Old Measure Registers 10 58 10 4 8 Operation of ...

Page 11: ...ut Correction Function 10 6 15 Operation of TOM in Single shot PWM Output Mode 10 109 without Correction Function 10 6 16 Operation of TOM in Successive Output Mode 10 111 without Correction Function 10 6 17 TOM Output Disable Function 10 113 10 6 18 Example for Using the TOM in Motor Control Applications 10 116 CHAPTER 11 A D CONVERTERS 11 1 Outline of the A D Converters 11 2 11 1 1 Conversion Mo...

Page 12: ... 12 2 12 2 Serial I O Related Registers 12 8 12 2 1 SIO Interrupt Related Registers 12 10 12 2 2 SIO Interrupt Control Registers 12 12 12 2 3 SIO Transmit Control Registers 12 19 12 2 4 SIO Transmit Receive Mode Registers 12 21 12 2 5 SIO Transmit Buffer Registers 12 24 12 2 6 SIO Receive Buffer Registers 12 25 12 2 7 SIO Receive Control Registers 12 26 12 2 8 SIO Baud Rate Registers 12 29 12 3 Tr...

Page 13: ...ion 12 53 12 6 6 Processing at End of UART Transmission 12 54 12 6 7 Transmit Interrupt 12 54 12 6 8 Transmit DMA Transfer Request 12 54 12 6 9 Typical UART Transmit Operation 12 56 12 7 Receive Operation in UART Mode 12 58 12 7 1 Initial Settings for UART Reception 12 58 12 7 2 Starting UART Reception 12 60 12 7 3 Processing at End of UART Reception 12 60 12 7 4 Typical UART Receive Operation 12 ...

Page 14: ... 6 Receiving Data Frames 13 89 13 6 1 Data Frame Reception Procedure 13 89 13 6 2 Data Frame Receive Operation 13 91 13 6 3 Reading Out a Received Data Frame 13 93 13 7 Transmitting Remote Frames 13 95 13 7 1 Remote Frame Transmission Procedure 13 95 13 7 2 Remote Frame Transmit Operation 13 97 13 7 3 Reading Out a Received Data Frame When Set for Remote Frame Transmission 13 100 13 8 Receiving Re...

Page 15: ...ol Register 15 13 15 2 5 TIN Interrupt Status Register 15 14 15 2 6 DACNT Control Register 15 16 15 2 7 TPD Control Register 15 17 15 2 8 DACNT Counter 15 18 15 2 9 TPD Counter 15 19 15 2 10 TPD Measure Registers 15 20 15 2 11 PD Calculation Interrupt Control Register 15 22 15 2 12 PD Calculation Interrupt Status Register 15 23 15 2 13 Position Detection Accuracy Select Register 15 25 15 2 14 TEP ...

Page 16: ...16 2 5 D A Control Register 16 12 16 2 6 D A Conversion Registers 16 13 16 2 7 D A0 Data Registers 16 14 16 3 Functional Description of the D A Converters 16 15 16 3 1 Single Mode 16 15 16 3 2 Continuous Mode 16 15 CHAPTER 17 EXTERNAL BUS INTERFACE 17 1 External Bus Interface Related Signals 17 2 17 2 Read Write Operations 17 14 17 3 Bus Arbitration 17 20 17 4 Example for Connecting External Exten...

Page 17: ...Circuit 20 2 20 1 2 System Clock Output Function 20 3 20 1 3 Oscillation Stabilization Time at Power on 20 4 20 2 Clock Generator Circuit 20 5 CHAPTER 21 JTAG 21 1 Outline of the JTAG 21 2 21 2 Configuration of the JTAG Circuit 21 3 21 3 JTAG Registers 21 4 21 3 1 Instruction Register JTAGIR 21 4 21 3 2 Data Registers 21 5 21 4 Basic Operation of the JTAG 21 6 21 4 1 Outline of the JTAG Operation ...

Page 18: ...22 6 CHAPTER 23 ELECTRICAL CHARACTERISTICS 23 1 Absolute Maximum Ratings 23 2 23 2 Recommended Operating Conditions 23 3 23 3 DC Characteristics 23 5 23 3 1 Electrical Characteristics 23 5 23 3 2 Flash Related Electrical Characteristics 23 9 23 4 A D Conversion Characteristics 23 10 23 5 D A Conversion Characteristics 23 11 23 5 1 D A Conversion Characteristics 23 11 23 6 AC Characteristics 23 12 ...

Page 19: ... 3 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise Appendix 3 2 Appendix 3 1 1 Reduction of Wiring Length Appendix 3 2 Appendix 3 1 2 Inserting a Bypass Capacitor between VSS and VCC Lines Appendix 3 4 Appendix 3 1 3 Processing Analog Input Pin Wiring Appendix 3 5 Appendix 3 1 4 Consideration about the Oscillator Appendix 3 6 Appendix 3 1 5 Processing Input Output Ports Appendix 3 8 1...

Page 20: ... This is a blank page 16 ...

Page 21: ...1 1 Overview 1 2 Block Diagram 1 3 Pin Functions 1 4 Pin Layout CHAPTER 1 CHAPTER 1 OVERVIEW ...

Page 22: ... just load and store instructions or register to register operation instructions compound instructions such as Load Address Update and Store Address Update also are executed in one cycle Instructions are entered into the execution stage in the order they are fetched but this does not always mean that the first instruction entered is executed first If the execution of a load or store instruction en...

Page 23: ...hen combined with high speed data transfer instructions such as Load Address Update and Store Address Update they enable the M32R to exhibit high data processing capability comparable to that of DSP 1 1 3 Built in Flash Memory and RAM The 32172 32173 contains flash memory and RAM that can be accessed with no wait states making it possible to build a high speed embedded system The internal flash me...

Page 24: ...r created software as well as can be triggered by a signal generated by the internal peripheral I O A D converter input output timer or serial I O The microcomputer also supports cascaded operation between DMA channels starting DMA transfer on a channel at the end of transfer on another channel This makes advanced transfer processing possible without causing any additional CPU load 3 Built in two ...

Page 25: ...tate which are assigned to each interrupt source It also handles external interrupt requests generated upon detection of power outage or generated by the watchdog timer as System Break Interrupt SBI 7 Three operation modes The M32R E supports three operation modes single chip external extended and processor modes The M32R E s address space and external pin functions are switched over according to ...

Page 26: ...tic circuits that operate along with PD Phase Digital sensors With various arithmetic circuits needed for position predictive operations incorporated and the timers interlocked with the D A converters fast data processing is possible When not using the PD circuit the PD sensor handling timers can be used as ordinary input measurement timers or input event counters 1 1 9 Built in Debug Function The...

Page 27: ... 16KB Internal Flash Memory 256KB M32R CPU Core max 40MHz Multiplier accumulator DMAC 10 channels Input output Timer 26 channels Serial I O 8 channels A D Converter x 2 A D0 10 bit A D 8 channels A D1 10 bit A D 4 channels Wait Controller Interrupt Controller interrupt sources in 8 levels Real time Debugger RTD External Bus Interface Internal 16 bit Bus Internal 32 bit Bus Input output Ports JTAG ...

Page 28: ... General purpose register 32 bits x 16 Control register 32 bits x 5 Instruction set 16 bit 32 bit instruction formats 83 discrete instructions 6 addressing modes Built in multiplier accumulator 32 x 16 56 Table 1 2 2 Features of the Internal Memory Functional Block Features RAM Capacity M32172F2 16 Kbytes M32173F2 32 Kbytes No wait access By using the RTD Real time Debugger the internal RAM can be...

Page 29: ...its second during UART mode Real time debugger Can rewrite monitor the internal RAM by command input from the outside independently of the CPU Comes with dedicated clock synchronized serial port Interrupt controller Controls interrupt requests from internal peripheral I Os Eight priority levels including interrupt disabled state Wait controller Controls wait state when accessing external extended ...

Page 30: ...A15 A22 8 P46 A13 CS3 P47 A14 Port 2 Port 3 Port 4 Interrupt controller P61 P63 Port 6 P64 SBI 3 Bus control serial I O Clock P93 RXD3 AD0IN8 P94 TXD6 P95 RXD6 P96 CTX1 P97 CRX1 Port 9 CAN P100 P103 TO8 TO11 P105 TO13 SCLKO4 P106 TO14 TXD4 P104 TO12 SCLKI4 P107 TO15 RXD4 Port 10 Input output timer Input output timer serial I O P110 P113 TO0 TO3 P115 TO5 SCLKO5 P116 TO6 TXD5 P114 TO4 SCLKI5 P117 TO...

Page 31: ...X1 Port 9 CAN P100 P103 TO8 TO11 P105 TO13 SCLKO4 P106 TO14 TXD4 P104 TO12 SCLKI4 P107 TO15 RXD4 Port 10 Input output timer Input output timer serial I O P110 P113 TO0 TO3 P115 TO5 SCLKO5 P116 TO6 TXD5 P114 TO4 SCLKI5 P117 TO7 RXD5 Port 11 Input output timer Input output timer serial I O A D converter AVCC0 VREF0 AD0IN0 AD0IN7 AVSS0 AD1IN0 AD1IN3 P125 TIN0B AD1IN9 P126 TIN1A AD0IN10 P124 TIN0A AD0...

Page 32: ...ock operates at 40 MHz __ When this signal is Write WR during extemal write access it indicates the valid data on the data bus to transfer input clock BCLK output 20 MHz when the external input clock is 10 MHz OSC VCC Power supply Power supply for the PLL circuit Connect OSC VCC to the power supply 3 3 V OSC VSS Ground Connect OSC VSS to ground VCNT PLL control Input PLL circuit control pin Connec...

Page 33: ... Indicates the byte position to which valid data will be write enable ___ transferred when writing to an external device BHW ___ ___ BLW BLE Byte low Output ___ BHE is output for the upper address side D0 D7 is write enable ___ ___ valid while BLW BLE is output for the lower address side D8 D15 is valid ____ WAIT Wait Input ____ If input on WAIT is low when the M32R accesses an external device the...

Page 34: ...nalog input Input 8 channel analog input pins for the A D0 converter AD0IN7 AD1IN0 Analog input Input 4 channel analog input pins for the A D1 converter AD1IN3 AD0IN8 Analog input Input 20 channel analog input pins used to monitor the pin levels AD0IN15 AD1IN4 AD1IN15 D A DA0 Analog output Output Analog output pin for the D A0 converter converter DA1 Analog output Output Analog output pin for the ...

Page 35: ...ate SCLKI5 For CSIO mode Transmit receive clock input when external clock is selected SCLKO4 Clock output Output For UART mode Clock output derived from BRG by SCLKO5 dividing it by 2 For CSIO mode Transmit receive clock output TXD0 TXD7 Transmit data Output Serial I O transmit data output pins RXD0 RXD7 Received data Input Serial I O received data input pins Overview 1 3 Pin Functions ...

Page 36: ...in hardware CAN CTX0 CTX1 Data output Output These pins output the data from the CAN module CRX0 CRX1 Data input Input These pins take in the data for the CAN module JTAG JTMS Test mode Input Test mode select input to control the state transition of the test circuit JTCK Clock Input Clock input for the debug module and test circuit JTRST Test reset Input Test reset input to initialize the test cir...

Page 37: ...put output port 10 Input Output Programmable input output port P110 P117 Input output port 11 Input Output Programmable input output port P124 P127 Input output port 12 Input Output Input only port P130 P137 Input output port 13 Input Output Input only port P150 P153 Input output port 15 Input Output Programmable input output port P172 P175 Input output port 17 Input Output Programmable input outp...

Page 38: ...6 DB14 P17 DB15 P82 TXD0 P83 RXD0 P174 TXD2 P175 RXD2 VSS VCCI VREF0 AVCC0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 P173 TIN11 AD1IN7 P172 TIN10 AD1IN6 DA1 AD1IN5 DA0 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 AVSS0 P85 TXD1 P86 RXD1 P87 SCLKI1 SCLKO1 VSS P84 SCLKI0 SCLKO0 VCCE P13 DB11 2 4 3 5 6 7 8 9 35 22 23 24 25 26 27 28 29 30 31 32 33 34 11 12 13 14 15 16 17 18 19 20 21 10 1 36 VCNT O...

Page 39: ... P87 SCLKI1 SCLKO1 12 P34 A19 42 VREF0 72 VSS 13 P35 A20 43 AVCC0 73 FVCC 14 P36 A21 44 AD0IN0 74 P61 15 P37 A22 45 AD0IN1 75 P62 16 P20 A23 46 AD0IN2 76 P63 17 P21 A24 47 AD0IN3 77 ___ P64 SBI 18 P22 A25 48 AD0IN4 78 __ P70 BCLK WR 19 P23 A26 49 AD0IN5 79 ____ P71 WAIT 20 VCCE 50 AD0IN6 80 ____ P72 HREQ 21 VSS 51 AD0IN7 81 ____ P73 HACK TXD3 22 P24 A27 52 AD1IN0 82 P74 RTDTXD 23 P25 A28 53 AD1IN1...

Page 40: ...10 TO0 117 P106 TO14 TXD4 137 VCCI 98 P111 TO1 118 P107 TO15 RXD4 138 VSS 99 P112 TO2 119 P124 TIN0A ADIN9 139 __ P43 RD 100 P113 TO3 120 P125 TIN0B AD1IN9 140 ___ P44 CS0 101 P114 TO4 SCLKI5 121 P126 TIN1A AD0IN10 141 ___ P45 CS1 102 P115 TO5 SCLKO5 122 P127 TIN1B AD1IN10 142 ___ P46 A13 CS3 103 P116 TO6 TXD5 123 VCCI 143 P47 A14 104 P117 TO7 RXD5 124 P130 TIN16 PWMOFF0 AD0IN11 144 P220 CTX0 105 ...

Page 41: ...RXD P05 DB5 P06 DB6 P07 DB7 N C AD0IN2 AD0IN6 AD1IN2 TIN10 AD1IN6 TIN11 AD1IN7 TRDATA0 N C P174 TXD2 P10 DB8 P11 DB9 P16 DB14 N C AVCC0 AD0IN3 AD0IN7 AD1IN3 VSS TRDATA3 P82 TXD0 P85 TXD1 N C N C P13 DB11 P12 DB10 P17 DB15 AD0IN0 AD0IN4 AD1IN0 DA0 AD1IN14 VCCI TRDATA2 VCCE SCLKI0 SCLKO0 P14 DB12 P15 DB13 VREF0 AD0IN1 AD0IN5 AD1IN1 DA1 AD1IN15 AVSS0 TRDATA1 P175 RXD2 P83 RXD0 C A D E F G H J K L M N...

Page 42: ...P22 A25 B2 P47 A14 E2 OSC VCC H2 P21 A24 B3 N C E3 XOUT H3 P20 A23 B4 N C E4 P30 A15 H4 P23 A26 B5 VSS E5 H5 B6 P153 TIN9 RXD7 AD1IN15 E6 H6 B7 P136 TIN22 AD0IN14 E7 H7 B8 P132 TIN18 AD01N12 E8 H8 B9 P127 TIN1B AD1IN10 E9 H9 B10 P125 TIN0B AD1IN9 E10 H10 B11 P105 TO13 SCLKO4 E11 H11 B12 JTDI E12 P113 TO3 H12 P97 CRX1 B13 N C E13 P116 TO6 TXD5 H13 MOD0 B14 JTMS E14 P115 TO5 SCLKO5 H14 ____________ ...

Page 43: ...2 P11 VCCE K12 TRDATA4 M12 N C P12 P84 SCLKI0 SCLKO0 K13 P76 RTDACK M13 ___ P64 SB1 P13 N C K14 P77 RTDCLK M14 __ P70 BCLK WR P14 P61 K15 P93 RXD3 AD0IN8 M15 ____ P71 WAIT P15 FVCC L1 P02 DB2 N1 P10 DB8 R1 P14 DB12 L2 P03 DB3 N2 P11 DB9 R2 P15 DB13 L3 P04 DB4 N3 P16 DB14 R3 N C L4 P01 DB1 N4 N C R4 VREF0 L5 N5 AVCC0 R5 AD0IN1 L6 N6 AD0IN3 R6 AD0IN5 L7 N7 AD0IN7 R7 AD1IN1 L8 N8 AD1IN3 R8 DA1 AD1IN1...

Page 44: ...1 1 24 Rev 1 0 This is a blank page Overview 1 4 Pin Layout ...

Page 45: ...CHAPTER 2 CHAPTER 2 CPU 2 1 CPU Registers 2 2 General purpose Registers 2 3 Control Registers 2 4 Accumulator 2 5 Program Counter 2 6 Data Formats ...

Page 46: ... R14 is used as a link register and R15 is used as a stack pointer The link register is used to store the return address when executing a subroutine call instruction The stack pointer is switched between an interrupt stack pointer SPI and a user stack pointer SPU depending on the value of the Processor Status Word register PSW s stack mode SM bit Figure 2 2 1 General purpose Registers 31 31 0 0 R8...

Page 47: ...edicated MVTC and MVFC instructions are used to set and read these control registers Figure 2 3 1 Control Registers Control Registers CR0 CR1 CR2 CR3 0 31 PSW CBR SPI SPU Processor status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer BPC CR6 Backup PC CRn Notes 1 CRn n 0 3 6 denotes control register numbers 2 Dedicated MVTC and MVFC instructions are used to set an...

Page 48: ... is accepted 17 BIE Backup IE Holds the value of IE bit when EIT Indeterminate is accepted 23 BC Backup C Holds the value of C bit when EIT Indeterminate is accepted 24 SM Stack Mode 0 Interrupt stack pointer is used 0 1 User stack pointer is used 25 IE Interrupt Enable 0 No interrupt is accepted 0 1 Interrupt is accepted 31 C Condition bit Depending on instruction execution it indicates 0 whether...

Page 49: ...general purpose register R15 In this case whether R15 is used as SPI or as SPU depends on the PSW s Stack Mode SM bit 2 3 4 Backup PC BPC CR6 The Backup PC BPC is a register used to save the value of the Program Counter PC when an EIT occurs Bit 31 is fixed to 0 When an EIT occurs the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this regis...

Page 50: ...and MVFACMI instructions are used to read data from the accumulator The MVFACHI instruction reads data from the 32 high order bits bits 0 31 the MVFACLO instruction reads data from the 32 low order bits bits 32 63 and the MVFACHI instruction reads data from the 32 middle bits bits 16 47 CPU 2 4 Accumulator Note Bits 0 7 always show the sign extended value of bit 8 Writes to this bit field are igno...

Page 51: ...ntegers Values of signed integers are represented by 2 s complements Figure 2 6 1 Data Types CPU 2 6 Data Formats Signed byte 8 bit integer Unsigned byte 8 bit integer Signed halfword 16 bit integer Unsigned halfword 16 bit integer Signed word 32 bit integer Unsigned word 32 bit integer 0 MSB 0 MSB 0 MSB 0 MSB 0 MSB 0 MSB 7 LSB 7 LSB 15 LSB 15 LSB 31 LSB 31 LSB S S S S Sign bit ...

Page 52: ...he ST instruction stores the entire 32 bit data of the register the STH instruction stores the least significant 16 bit data and the STB instruction stores the least significant 8 bit data Figure 2 6 2 Data Formats in Register Rn 0 MSB 31 LSB When loading Byte Rn 0 MSB 31 LSB Halfword Rn 0 MSB 31 LSB Word Sign extended LDB instruction or zero extended LDUB instruction From memory LDB LDUB instruct...

Page 53: ... LSB address bit 0 and word data must be located at word boundaries where two LSB address bits 00 If an attempt is made to access memory data across these halfword or word boundaries an address exception is generated Figure 2 6 3 Data Formats in Memory CPU 2 6 Data Formats Address Byte Halfword Word 0 address 1 address 2 address 3 address 31 Byte 7 8 15 16 23 24 MSB 15 LSB 0 MSB 31 LSB Byte Byte B...

Page 54: ...B MSB LSB MSB LSB Ex 0x01234567 byte 67 45 23 01 byte 01 23 45 67 byte 01 23 45 67 Note The M32R s endian method is big endian for both bit and byte 7 0 31 24 15 8 23 16 Figure 2 6 4 Endian Methods Bit endian Byte endian Big endian Little endian Note Even for bit big endian H 01 is not B 10000000 H 01 H 01234567 MSB LSB HH HL LH LL H 01 H 23 H 45 H 67 MSB LSB LL LH HL HH H 67 H 45 H 23 H 01 MSB LS...

Page 55: ... imm16 31 0 SETH Rdest imm16 00 8 15 00 00 Register to register transfer MV Rdest Rsrc Control register transfer MVFC Rdest CRsrc MVTC Rsrc CRdest Note For the MVTC instruction the condition bit C does not change unless CRdest is CR0 PSW Rsrc 31 0 Rdest 31 0 Rsrc 31 0 CRdest 31 0 MVTC Rsrc CRdest MV Rdest Rsrc 4 Transfer instructions Figure 2 6 6 Transfer instructions ...

Page 56: ...32 bits LD24 Rsrc label LD Rdest Rsrc Signed 16 bits LD24 Rsrc label LDH Rdest Rsrc Signed 8 bits LD24 Rsrc label LDB Rdest Rsrc label Rdest 31 0 0 1 2 3 Rdest label 00 00 FF FF Check the MSB 0 positive 1 negative 31 0 0 1 2 3 Rdest label 00 00 00 FF FF FF 31 0 0 1 2 3 Memory Register Check the MSB 0 positive 1 negative 5 Memory signed to register transfer Figure 2 6 7 Memory signed to register tr...

Page 57: ...and those in memory are different Figure 2 6 9 Difference in Data Arrangements Data in memory Data in register Word data 32 bits 0 1 2 3 D0 D31 HH HL LH LL D0 D31 HH HL LH LL Half word data 16 bits 0 1 2 3 D0 D31 H L D0 D15 H L Byte data 8 bits 0 1 2 3 D0 D31 D0 D7 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB R0 R15 R0 R15 R0 R15 ...

Page 58: ...2 2 14 Rev 1 0 This is a blank page CPU 2 6 Data Formats ...

Page 59: ... Address Space 3 2 Operation Modes 3 3 Internal ROM and External Extended Areas 3 4 Internal RAM and SFR Areas 3 5 EIT Vector Entry 3 6 ICU Vector Table 3 7 Precautions on Address Space CHAPTER 3 CHAPTER 3 ADDRESS SPACE ...

Page 60: ...rnal RAM areas and the SFR Special Function Register area i e internal peripheral I O registers Of these the internal ROM and external extended areas are allocated to different addresses depending on mode settings which are described later 2 Boot program space A 1 Gbytes of space in addresses from H 8000 0000 to H BFFF FFFF is the boot program space This space stores a program boot program which e...

Page 61: ...a 16 Kbytes H 0080 3FFF H 0080 4000 User ROM Area Note 1 External Extended Area 8 Mbytes 1 Gbytes 1 Gbytes 2 Gbytes Ghost Areas 16 Mbytes Each Internal RAM 16 Kbytes H 0080 7FFF H 8000 0000 H 8000 1FFF Ghost Areas 16 Kbytes Each Reserved Area 8 Kbytes Reserved Area 96 Kbytes H 0080 8000 H 8000 3FFF H 8000 2000 H 8000 4000 H BFFF FFFF H 0040 0000 H 003F FFFF H 000F FFFF H 0010 0000 H 0003 FFFF Rese...

Page 62: ...FF H 0010 0000 H 0003 FFFF H 001F FFFF H 0020 0000 H 0004 0000 H 0060 0000 H 005F FFFF H 0080 0000 H 007F FFFF H 00FF FFFF H 0081 FFFF H 0082 0000 Logical Space of the M32173F2 User Space Boot Program Space Note 2 System Space Logical Address 1 Gbytes 1 Gbytes 2 Gbytes Boot ROM Area 8 Kbytes 16 Mbytes Reserved Area 8 Kbytes Ghost Areas 16 Mbytes Each Ghost Areas 16 Kbytes Each EIT Vector Entry Ext...

Page 63: ...n the above table refer to Section 6 5 Programming the Internal Flash Memory The locations of the internal ROM and external extended areas in the address space of the 32172 32173 vary depending on its operation mode All other areas in address space located the same way Also during external extended mode the available size of the external extended area varies _______ _______ _______ _______ with pi...

Page 64: ...or mode External extended mode H 001F FFFF H 0020 0000 CS0 Area 1 Mbytes H 000F FFFF H 0010 0000 H 003F FFFF H 0040 0000 External Extended Area CS2 Area 2 Mbytes CS3 Area 2 Mbytes Reserved Area 768 Kbytes CS1 Area 2 Mbytes CS2ReservedArea 2 Mbytes CS3ReservedArea 2 Mbytes CS0 Area 2 Mbytes External Extended Area Internal ROM Area 256 Kbytes Internal ROM Area 256 Kbytes H 005F FFFF H 0060 0000 H 00...

Page 65: ...f CS0 Area CS1 Area 512 Kbytes Ghost of CS1 Area CS2 Area 512 Kbytes Ghost of CS2 Area CS0 Area 256 Kbytes Ghost of CS0 Area CS1 Area 256 Kbytes Ghost of CS1 Area CS2 Area 256 Kbytes Ghost of CS2 Area CS3 Area 256 Kbytes Ghost of CS3 Area Internal ROM Area 256 Kbytes CS3 Area 256 Kbytes Ghost of CS3 Area CS3 Area 256 Kbytes Ghost of CS3 Area CS1 Area 256 Kbytes Ghost of CS1 Area CS1 Area 256 Kbyte...

Page 66: ...ip operation mode For access to the external extended area the 32172 32173 outputs the control signals that are required for accessing an external device ___ ___ ___ ___ The 32172 32173 s CS0 CS1 CS2 and CS3 signals are output according to the address into ___ which the external extended area is mapped Namely the CS0 signal is output for the CS0 area ___ ___ ___ the CS1 signal is output for the CS...

Page 67: ...nal RAM Area For the M32172F2 the internal RAM is allocated to addresses H 0080 4000 through H 0080 7FFF 16 Kbytes For the M32173F2 the internal RAM is allocated to addresses H 0080 4000 through H 0080 BFFF 32 Kbytes 3 4 2 SFR Special Function Register Area Addresses H 0080 0000 to H 0080 3FFF are the SFR Special Function Register area Located in this area are the internal peripheral I O registers...

Page 68: ...nal RAM Area and SFR Special Function Register Area of the M32173F2 H 0080 0000 SFR area 16 Kbytes Internal RAM 32 Kbytes H 0080 3FFF H 0080 4000 H 0080 BFFF Virtual flash emulation area separated in units of 8 or 4 Kbytes can be mapped into this area For details see Section 6 7 ...

Page 69: ...be transparent to the CPU 0 7 8 15 0 address 1 address 0 address 1 address 0 7 8 15 H 0080 0D8C H 0080 0DDE H 0080 0400 DMAC H 0080 0478 CAN0 H 0080 1000 H 0080 11FE H 0080 0700 Input output Ports H 0080 0744 H 0080 3FFE CAN1 H 0080 1400 H 0080 15FE H 0080 1800 H 0080 18BA Flash Control H 0080 07E0 H 0080 07F2 H 0080 0A00 H 0080 0A46 Serial I O4 7 H 0080 0A80 H 0080 0AEE A D1 Converter H 0080 0800...

Page 70: ...D0 Comparate Data Register AD0CMP H 0080 008C H 0080 0092 H 0080 0094 10 bit A D0 Data Register 0 AD0DT0 10 bit A D0 Data Register 1 AD0DT1 10 bit A D0 Data Register 2 AD0DT2 10 bit A D0 Data Register 3 AD0DT3 10 bit A D0 Data Register 4 AD0DT4 10 bit A D0 Data Register 5 AD0DT5 10 bit A D0 Data Register 6 AD0DT6 10 bit A D0 Data Register 7 AD0DT7 10 bit A D0 Data Register 8 AD0DT8 10 bit A D0 Dat...

Page 71: ...3SEL SIO0 Transmit Control Register S0TCNT SIO0 Transmit Receive Mode Register S0MOD SIO0 Receive Control Register S0RCNT H 0080 0124 SIO1 Baud Rate Register S1BAUR SIO1 Transmit Buffer Register S1TXB SIO1 Receive Buffer Register S1RXB SIO1 Transmit Control Register S1TCNT SIO1 Transmit Receive Mode Register S1MOD SIO1 Receive Control Register S1RCNT SIO2 Baud Rate Register S2BAUR SIO2 Transmit Bu...

Page 72: ...rupt Request Status Register DM04ITST H 0080 0400 H 0080 0408 DMA5 9 Interrupt Mask Register DM59ITMK DMA5 9 Interrupt Request Status Register DM59ITST DMA5 Channel Control Register DM5CNT DMA5 Transfer Count Register DM5TCT DMA5 Source Address Register DM5SA DMA5 Destination Address Register DM5DA DMA6 Channel Control Register DM6CNT DMA6 Transfer Count Register DM6TCT H 0080 042A H 0080 042C H 0...

Page 73: ...8 Source Address Register DM8SA DMA8 Destination Address Register DM8DA DMA9 Channel Control Register DM9CNT DMA9 Transfer Count Register DM9TCT DMA9 Source Address Register DM9SA DMA9 Destination Address Register DM9DA DMA4 Software Request Generation Register DM4SRI DMA5 Software Request Generation Register DM5SRI DMA6 Software Request Generation Register DM6SRI DMA7 Software Request Generation ...

Page 74: ...ol Register BUSMODC P0 Direction Register P0DIR P1 Direction Register P1DIR H 0080 077E Flash Mode Register FMOD Flash Control Register 1 FCNT1 Flash Status Register 1 FSTAT1 Flash Control Register 2 FCNT2 Flash Control Register 3 FCNT3 Flash Control Register 4 FCNT4 Virtual flash L Bank Register 0 FELBANK0 Virtual flash L Bank Register 2 FELBANK2 H 0080 0742 H 0080 0740 P0 Operation Mode Register...

Page 75: ...rupt Mask Register 4 TINIMA4 TIN Interrupt Status Register 5 TINIST5 TIN Interrupt Mask Register 5 TINIMA5 TIN Interrupt Status Register 8 TINIST8 TIN Interrupt Mask Register 8 TINIMA8 TML0 Control Register 0 TML0CR Prescaler 1 PRS1 TML0 Measurement 3 Register H TML0MR3H TML0 Measurement 3 Register L TML0MR3L TML0 Measurement 2 Register H TML0MR2H TML0 Measurement 2 Register L TML0MR2L TML0 Measur...

Page 76: ...t Buffer Register S6TXB SIO6 Receive Buffer Register S6RXB SIO6 Receive Control Register S6RCNT SIO6 Baud Rate Register S6BAUR SIO7 Transmit Control Register S7TCNT SIO7 Transmit Receive Mode Register S7MOD SIO7 Transmit Buffer Register S7TXB SIO7 Receive Buffer Register S7RXB SIO7 Receive Control Register S7RCNT SIO7 Baud Rate Register S7BAUR H 0080 0A88 H 0080 0A92 H 0080 0A9C H 0080 0AAA A D1 S...

Page 77: ... D1 Data Register 3 AD18DT3 8 bit A D1 Data Register 4 AD18DT4 8 bit A D1 Data Register 5 AD18DT5 8 bit A D1 Data Register 12 AD18DT12 8 bit A D1 Data Register 6 AD18DT6 8 bit A D1 Data Register 8 AD18DT8 8 bit A D1 Data Register 9 AD18DT9 8 bit A D1 Data Register 10 AD18DT10 8 bit A D1 Data Register 11 AD18DT11 8 bit A D1 Data Register 13 AD18DT13 8 bit A D1 Data Register 14 AD18DT14 8 bit A D1 D...

Page 78: ...d 1 Register TOM02RL1 TOM0_2 Reload 0 Register TOM02RL0 TOM0_3 Counter TOM03CT TOM0_3 Reload 1 Register TOM03RL1 TOM0_3 Reload 0 Register TOM03RL0 TOM0_4 Counter TOM04CT TOM0_4 Reload 1 Register TOM04RL1 TOM0_4 Reload 0 Register TOM04RL0 TOM0_5 Counter TOM05CT TOM0_5 Reload 1 Register TOM05RL1 TOM0_5 Reload 0 Register TOM05RL0 TOM0_6 Counter TOM06CT TOM0_6 Reload 1 Register TOM06RL1 TOM0_6 Reload ...

Page 79: ...r TOM11RL0 TOM1_2 Counter TOM12CT TOM1_2 Reload 1 Register TOM12RL1 TOM1_2 Reload 0 Register TOM12RL0 TOM1_3 Counter TOM13CT TOM1_3 Reload 1 Register TOM13RL1 TOM1_3 Reload 0 Register TOM13RL0 TOM1_4 Counter TOM14CT TOM1_4 Reload 1 Register TOM14RL1 TOM1_4 Reload 0 Register TOM14RL0 TOM1_5 Counter TOM15CT TOM1_5 Reload 1 Register TOM15RL1 TOM1_5 Reload 0 Register TOM15RL0 TOM1_6 Counter TOM16CT TO...

Page 80: ...L9CNT CAN0 Message Slot 11 Control Register C0MSL11CNT CAN0 Message Slot 13 Control Register C0MSL13CNT CAN0 Message Slot 15 Control Register C0MSL15CNT CAN0 Message Slot 6 Control Register C0MSL6CNT CAN0 Message Slot 8 Control Register C0MSL8CNT CAN0 Message Slot 10 Control Register C0MSL10CNT CAN0 Message Slot 12 Control Register C0MSL12CNT CAN0 Message Slot 14 Control Register C0MSL14CNT H 0080...

Page 81: ...Data 3 C0MSL2DT3 CAN0 Message Slot 2 Data 1 C0MSL2DT1 CAN0 Message Slot 2 Data Length Register C0MSL2DLC CAN0 Message Slot 2 Extended ID1 C0MSL2EID1 CAN0 Message Slot 2 Standard ID1 C0MSL2SID1 CAN0 Message Slot 1 Data 7 C0MSL1DT7 H 0080 1130 H 0080 1132 H 0080 1136 H 0080 1138 H 0080 113E H 0080 113C H 0080 1134 H 0080 113A CAN0 Message Slot 3 Data 6 C0MSL3DT6 CAN0 Message Slot 3 Timestamp C0MSL3T...

Page 82: ... 0080 119E CAN0 Message Slot 8 Data 6 C0MSL8DT6 CAN0 Message Slot 8 Timestamp C0MSL8TSP CAN0 Message Slot 8 Data 7 C0MSL8DT7 CAN0 Message Slot 8 Data 4 C0MSL8DT4 CAN0 Message Slot 8 Data 2 C0MSL8DT2 CAN0 Message Slot 8 Data 0 C0MSL8DT0 CAN0 Message Slot 8 Extended ID2 C0MSL8EID2 CAN0 Message Slot 8 Extended ID0 C0MSL8EID0 CAN0 Message Slot 8 Standard ID0 C0MSL8SID0 CAN0 Message Slot 8 Data 5 C0MSL...

Page 83: ... C0MSL13SID1 H 0080 11D6 H 0080 11D8 H 0080 11DA H 0080 11DE H 0080 11E0 H 0080 11E6 H 0080 11E4 H 0080 11DC H 0080 11E2 H 0080 11D4 H 0080 11E8 H 0080 11EA H 0080 11EE H 0080 11F0 H 0080 11F6 H 0080 11F4 H 0080 11EC H 0080 11F2 H 0080 11F8 H 0080 11FA H 0080 11FE H 0080 11FC CAN0 Message Slot 14 Data 6 C0MSL14DT6 CAN0 Message Slot 14 Timestamp C0MSL14TSP CAN0 Message Slot 14 Data 7 C0MSL14DT7 CAN...

Page 84: ...1MSL11CNT CAN1 Message Slot 13 Control Register C1MSL13CNT CAN1 Message Slot 15 Control Register C1MSL15CNT CAN1 Message Slot 6 Control Register C1MSL6CNT CAN1 Message Slot 8 Control Register C1MSL8CNT CAN1 Message Slot 10 Control Register C1MSL10CNT CAN1 Message Slot 12 Control Register C1MSL12CNT CAN1 Message Slot 14 Control Register C1MSL14CNT H 0080 1412 CAN1 Error Interrupt Status Register CA...

Page 85: ...1MSL2DT1 CAN1 Message Slot 2 Data Length Register C1MSL2DLC CAN1 Message Slot 2 Extended ID1 C1MSL2EID1 CAN1 Message Slot 2 Standard ID1 C1MSL2SID1 CAN1 Message Slot 1 Data 7 C1MSL1DT7 H 0080 1530 H 0080 1532 H 0080 1536 H 0080 1538 H 0080 153E H 0080 153C H 0080 1534 H 0080 153A CAN1 Message Slot 3 Data 6 C1MSL3DT6 CAN1 Message Slot 3 Timestamp C1MSL3TSP CAN1 Message Slot 3 Data 7 C1MSL3DT7 CAN1 ...

Page 86: ... 0080 159E CAN1 Message Slot 8 Data 6 C1MSL8DT6 CAN1 Message Slot 8 Timestamp C1MSL8TSP CAN1 Message Slot 8 Data 7 C1MSL8DT7 CAN1 Message Slot 8 Data 4 C1MSL8DT4 CAN1 Message Slot 8 Data 2 C1MSL8DT2 CAN1 Message Slot 8 Data 0 C1MSL8DT0 CAN1 Message Slot 8 Extended ID2 C1MSL8EID2 CAN1 Message Slot 8 Extended ID0 C1MSL8EID0 CAN1 Message Slot 8 Standard ID0 C1MSL8SID0 CAN1 Message Slot 8 Data 5 C1MSL...

Page 87: ... C1MSL13SID1 H 0080 15D6 H 0080 15D8 H 0080 15DA H 0080 15DE H 0080 15E0 H 0080 15E6 H 0080 15E4 H 0080 15DC H 0080 15E2 H 0080 15D4 H 0080 15E8 H 0080 15EA H 0080 15EE H 0080 15F0 H 0080 15F6 H 0080 15F4 H 0080 15EC H 0080 15F2 H 0080 15F8 H 0080 15FA H 0080 15FE H 0080 15FC CAN1 Message Slot 14 Data 6 C1MSL14DT6 CAN1 Message Slot 14 Timestamp C1MSL14TSP CAN1 Message Slot 14 Data 7 C1MSL14DT7 CAN...

Page 88: ...t Register 5 TPDMR5 TPD Measurement Register 6 TPDMR6 TPD Measurement Register 7 TPDMR7 H 0080 1848 H 0080 1870 H 0080 1868 PD Calculation Interrupt Status Register PDIST TEP0P Control Register TEP0PCR TEP0M Control Register TEP0MCR TEP0P Counter TEP0PCT TEP0M Counter TEP0MCT PD0 Data Update Disable Event Select Register PDNSEL0R AB0 Mask Register ABD0MK PICH0 Compare Register PITCH0CMR POLDLT0 Re...

Page 89: ... POLDLT1 MNEWLT1 Register MNEWLT1 MOLDLT1 Register MOLDLT1 PSUBLT1 Register PSUBLT1 MSUBLT1 Register MSUBLT1 RSUMLT1 Register RSUMLT1 H 0080 18AE H 0080 18BA TEP1P Counter TEP1PCT TEP1M Counter TEP1MCT PD1 Data Update Disable Event Select Register PDNSEL1R PD1 Data Update Control Register PDNCNT1R ABD1 Mask Register ABD1MK S Error 1 Detection Range Select Register SNEW1MK ABD1 Compare Register ABD...

Page 90: ...ster 29 DA0DT29 D A0 Data Register 30 DA0DT30 D A0 Data Register 31 DA0DT31 D A0 Data Register 32 DA0DT32 D A0 Data Register 33 DA0DT33 D A0 Data Register 34 DA0DT34 D A0 Data Register 35 DA0DT35 D A0 Data Register 36 DA0DT36 D A0 Data Register 37 DA0DT37 D A0 Data Register 38 DA0DT38 D A0 Data Register 39 DA0DT39 D A0 Data Register 40 DA0DT40 D A0 Data Register 41 DA0DT41 D A0 Data Register 42 DA...

Page 91: ...DT123 D A0 Data Register 124 DA0DT124 D A0 Data Register 125 DA0DT125 D A0 Data Register 126 DA0DT126 D A0 Data Register 127 DA0DT127 D A0 Data Register 128 DA0DT128 D A0 Data Register 129 DA0DT129 D A0 Data Register 130 DA0DT130 D A0 Data Register 131 DA0DT131 D A0 Data Register 132 DA0DT132 D A0 Data Register 133 DA0DT133 D A0 Data Register 134 DA0DT134 D A0 Data Register 135 DA0DT135 D A0 Data ...

Page 92: ...a Register 211 DA0DT211 D A0 Data Register 212 DA0DT212 D A0 Data Register 213 DA0DT213 D A0 Data Register 214 DA0DT214 D A0 Data Register 215 DA0DT215 D A0 Data Register 216 DA0DT216 D A0 Data Register 217 DA0DT217 D A0 Data Register 218 DA0DT218 D A0 Data Register 219 DA0DT219 D A0 Data Register 220 DA0DT220 D A0 Data Register 221 DA0DT221 D A0 Data Register 222 DA0DT222 D A0 Data Register 223 D...

Page 93: ...AP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE Address Exception EI External Interrupt Note H 0000 0044 H 0000 0048 H 0000 004C H 0000 0050 H 0000 0054 H 0000 0058 H 0000 005C H 0000 0060 H 0000 0064 H 0000 0068 H 0000 006C H 0000 0070 H 0000 0074 H 0000 0078 H 0000 007C H 0000 0080 RI Reset Interrupt SBI System Break Interrupt RIE Reserved Instruction Exception H 0000 0030 H 0000 00...

Page 94: ...B0 H 0000 00B2 H 0000 00B4 H 0000 00B6 H 0000 00B8 H 0000 00BA H 0000 00BC H 0000 00BE H 0000 00C0 H 0000 00C2 H 0000 00C4 H 0000 00C6 MJT Input Interrupt 4 Handler Start Address A0 A15 MJT Input Interrupt 4 Handler Start Address A16 A31 Blank areas are reserved for future use MJT Input Interrupt 3 Handler Start Address A0 A15 MJT Input Interrupt 3 Handler Start Address A16 A31 MJT Input Interrupt...

Page 95: ... 0100 H 0000 0102 H 0000 0104 H 0000 0106 H 0000 0108 H 0000 010A H 0000 010C H 0000 010E CAN0 Transmit Receive Error Interrupt Handler Start Address A0 A15 CAN0 Transmit Receive Error Interrupt Handler Start Address A16 A31 A D1 Conversion Interrupt Handler Start Address A0 A15 A D1 Conversion Interrupt Handler Start Address A16 A31 SIO2 3 Transmit Receive Interrupt Handler Start Address A0 A15 S...

Page 96: ...locks of the internal RAM beginning with the first address into the internal flash memory areas divided in units of 8 Kbytes L banks as well as mapping up to two 4 Kbyte blocks of the internal RAM beginning with the H 0080 A000 area into the internal flash memory areas divided in units of 4 Kbytes S banks the latter available for only the 32173 This is referred to as the virtual flash emulation fu...

Page 97: ...EIT Processing Mechanism 4 5 Accepting EIT Events 4 6 Saving and Restoring PC and PSW 4 7 EIT Vector Entry 4 8 Exception Handling 4 9 Interrupt Handling 4 10 Trap Handling 4 11 EIT Priority 4 12 Example of EIT Processing 4 13 Precautions on EIT CHAPTER 4 CHAPTER 4 EIT ...

Page 98: ...category of this type of event 2 Interrupt This event occurs independently of the context being executed It is generated by a signal sent by means of hardware from the outside In the M32R E External Interrupt EI System Break Interrupt SBI and Reset Interrupt RI fall under the category of this type of event 3 Trap This refers to a software interrupt which is issued by executing the TRAP instruction...

Page 99: ... an emergency interrupt which is issued when power outage is detected or a fault condition is notified from an external watchdog timer This interrupt can be used only when after interrupt processing the CPU does not as a rule return to the program it was executing when the interrupt occurred 3 External Interrupt EI The External Interrupt EI is an interrupt request from one of the internal peripher...

Page 100: ... preprocessing Save BPC B PSW and general purpose registers to the stack Branch instruction Restore general purpose registers B PSW and BPC from the stack SBI System Break Interrupt processing Hardware postprocessing SBI Terminate the program or reset the system User created processing program B PSW PSW BPC PC Processing by handler Note B PSW denotes the PSW Register s BPSW field 4 3 EIT Processin...

Page 101: ...y operation performed here Therefore it is necessary to save to the stack in a user created EIT handler the BPC Register the PSW Register including the BPSW field and the general purpose registers to be used in the EIT handler Remember that these registers must be saved to the stack in a program by the user When processing by the EIT handler is completed restore the registers from the stack to whi...

Page 102: ...ler It also has backup registers for the PC and PSW BPC Register and the BPSW fild of the PSW register The M32R E s internal EIT processing mechanism is shown below Figure 4 4 1 EIT Processing Mechanism of the M32R E Interrupt Controller ICU SBI EI Internal Peripheral I O RESET RI AE RIE TRAP IE Flag PSW M32R CPU Core SBI Low High Priority SBI EI RI M32R E PSW Register PSW BPSW BPC Register PC Reg...

Page 103: ...e of the instruction that Exception RIE cancel type execution generated RIE Address Exception Instruction processing During instruction PC value of the instruction that AE cancel type execution generated AE Reset Interrupt RI Instruction processing Each machine cycle Indeterminate value abandon type System Break Instruction processing Break in instructions PC value of the next instruction Interrup...

Page 104: ...to 0 SBI EI RI IE Set to 0 C Set to 0 c Save the PC Register BPC PC d Set the vector address in the PC Register Branches to the EIT vector and executes the branch instruction BRA instruction written in it thereby transferring control to EIT handler processing written by the user 2 Hardware postprocessing when executing the RTE instruction e Restore the PSW Register BSM BIE and BC bits SM BSM IE BI...

Page 105: ...tore the BPC value into the PC After executing the RTE instruction the value of the BPC is indeterminate e Restore the BSM BIE and BC bits After executing the RTE instruction the values of the BSM BIE and BC bits are indeterminate BSM BIE BC SM IE C IE C 0 0 BPC PC SM IE C BSM BIE BC C a f e 16 17 23 24 25 31 LSB 15 8 7 0 MSB SM IE C BC BSM BIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P...

Page 106: ... TRAP5 H 0000 0054 Unchanged 0 PC of the TRAP instruction 4 TRAP6 H 0000 0058 Unchanged 0 PC of the TRAP instruction 4 TRAP7 H 0000 005C Unchanged 0 PC of the TRAP instruction 4 TRAP8 H 0000 0060 Unchanged 0 PC of the TRAP instruction 4 TRAP9 H 0000 0064 Unchanged 0 PC of the TRAP instruction 4 TRAP10 H 0000 0068 Unchanged 0 PC of the TRAP instruction 4 TRAP11 H 0000 006C Unchanged 0 PC of the TRA...

Page 107: ...IE and BC BSM SM BIE IE BC C 2 Updating the SM IE and C bits The PSW Registmer SM IE and C bits are updated in the manner shown below SM Unchanged IE 0 C 0 3 Saving the PC The PC value of the instruction that caused the Reserved Instruction Exception is set in the BPC Register For example if the instruction that caused the Reserved Instruction Exception is at address 4 then the value 4 is set in t...

Page 108: ...andler The M32R E executes the BRA instruction written at the EIT vector entry address H 0000 0020 by the user thereby branching to the start address of the user created handler At the beginning of the user created EIT handler the BPC and PSW Registers and the necessary general purpose registers must first be saved to the stack 6 Returning from the EIT handler At the end of the EIT handler restore...

Page 109: ... SM IE and C bits The PSW Register SM IE and C bits are saved to the backup bits BSM BIE and BC BSM SM BIE IE BC C 2 Updating the SM IE and C bits The PSW Register SM IE and C bits are updated in the manner shown below SM Unchanged IE 0 C 0 3 Saving the PC The PC value of the instruction that caused the Address Exception is set in the BPC Register For example if the instruction that caused the Add...

Page 110: ...The M32R E executes the BRA instruction written at the EIT vector entry address H 0000 0030 by the user thereby branching to the start address of the user created handler At the beginning of the user created EIT handler the BPC and PSW Registers and the necessary general purpose registers must first be saved to the stack 6 Returning from the EIT handler At the end of the EIT handler restore the ge...

Page 111: ...IE 0 C 0 For Reset Interrupt the values of the BSM BIE and BC bits become indeterminate 2 Branching to the EIT vector entry Control branches to a user space address H 0000 0000 During boot mode however control goes to the beginning of the boot ROM address H 8000 0000 For details refer to Section 6 5 Programming the Internal Flash Memory 3 Branching from the EIT vector entry to the user program The...

Page 112: ...ed with the PSW Register IE bit Therefore the System Break Interrupt can only be used when some fatal event has already occurred in the system when the interrupt is detected Also this interrupt must be used on condition that after processing with the SBI handler the control will not return to the program it was executing when the system break interrupt occurred Occurrence condition ___ A System Br...

Page 113: ...ser space address H 0000 0010 This is the last operation in hardware preprocessing performed by the M32R E 5 Branching from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at the EIT vector entry address H 0000 0010 by the user thereby branching to the start address of the user created handler The System Break Interrupt can only be used when some fa...

Page 114: ...to Chapter 5 Interrupt Controller For details about the causes of interrupts refer to each relevant chapter where the internal peripheral I O in interest is described Occurrence condition External Interrupts are managed by the Interrupt Controller based on interrupt requests from each internal peripheral I O and are notified to the M32R CPU by the Interrupt Controller The M32R E checks for this re...

Page 115: ...s H 0080 4000 For details refer to Section 6 5 Programming the Internal Flash Memory This is the last operation in hardware preprocessing performed by the M32R E 5 Branching from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at the EIT vector entry address H 0000 0080 by the user thereby branching to the start address of the user created handler A...

Page 116: ...The PSW Register SM IE and C bits are updated in the manner shown below SM Unchanged IE 0 C 0 3 Saving the PC When the TRAP instruction is executed the PC value of TRAP instruction 4 is set in the BPC Register For example if the TRAP instruction is located at address 4 then the value H 08 is set in the BPC Register if located at address 6 the value H 0A is set in the BPC Register The value of the ...

Page 117: ...EIT vector entry to the user created handler The M32R E executes the BRA instruction written at the EIT vector entry addresses H 0000 0040 through H 0000 007C by the user thereby branching to the start address of the user created handler At the beginning of the user created EIT handler the BPC and PSW Registers and the necessary general purpose registers must first be saved to the stack 6 Returnin...

Page 118: ...on AE Instruction processing PC of the instruction that generated EIT cancel type 2 Reserved Instruction Instruction processing PC of the instruction that generated EIT Exception RIE cancel type Trap TRAP Instruction processing TRAP instruction 4 complete type 3 System Break Instruction processing PC of the next instruction Interrupt SBI complete type 4 External Interrupt EI Instruction processing...

Page 119: ... EI when They Occurred Simultaneously RTE instruction IE 0 IE 1 BPC Register return address A IE 1 Occurrence of a single RIE AE SBI EI or TRAP event Return address A If IE 0 remains unchanged nothing but reset and SBI are accepted EIT handler RTE instruction IE 0 RIE AE or TRAP is accepted first BPC Register return address A IE 1 Occurrence of an RIE AE or TRAP simultaneously with EI Return addre...

Page 120: ...ave general purpose registers to stack Processing by EIT handler Restore general purpose registers Restore PSW Restore BPC EIT event occurred SBI Processing of System Break Interrupt Terminate the program or reset the system Other than SBI PC BPC PSW B PSW Hardware preprocessing Hardware postprocessing B PSW PSW BPC PC Figure 4 12 3 Example of EIT Processing ...

Page 121: ...e as when using other addressing modes Applicable instructions LD Rdest Rsrc ST Rsrc1 Rsrc2 ST Rsrc1 Rsrc2 If the above applies take into account the fact that the register value becomes indeterminate when programming the system processing to be performed after occurrence of the exception If an Address Exception occurs it means that some fatal fault already occurred in the system at that point in ...

Page 122: ...4 4 26 Rev 1 0 This is a blank page EIT 4 13 Precautions on EIT ...

Page 123: ... ICU 5 2 Interrupt Sources of Internal Peripheral I Os 5 3 ICU Related Registers 5 4 ICU Vector Table 5 5 Description of Interrupt Operation 5 6 Description of System Break Interrupt SBI Operation CHAPTER 5 CHAPTER 5 INTERRUPT CONTROLLER ICU ...

Page 124: ...y reading the Interrupt Status Register of the internal peripheral I O On the other hand the System Break Interrupt SBI is an interrupt generated by a falling edge of ___ the SBI input signal This interrupt is always accepted regardless of the status of the PSW Register IE bit and is used as an emergency interrupt which is issued when power failure is detected or a fault condition is notified from...

Page 125: ...d hardware priority IMASK compared ILEVEL Resolved according to interrupt priority level System Break Interrupt request generated SBI EI SBI Interrupt Controller Interrupt Control Register SBI Control Register SBICR SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuit Edge Interrupt control circuit Interrupt control circuit Interrupt control circuit Edge Edge Level Interrupt request Interrupt r...

Page 126: ...3 transmit receive SIO2 3 reception finished or receive error interrupt 2 Level interrupt transmit buffer empty interrupt SIO4 transmit interrupt SIO4 transmit buffer empty interrupt 1 Edge SIO4 receive interrupt SIO4 reception finished or receive error interrupt 1 Edge SIO5 transmit interrupt SIO5 transmit buffer empty interrupt 1 Edge SIO5 receive interrupt SIO5 reception finished or receive err...

Page 127: ...input interrupt 4 Timer input interrupt group 4 TIN10 TIN11 input 2 Level Timer input interrupt 3 Timer input interrupt group 3 TIN20 TIN21 input 3 Level Timer input interrupt 2 Timer input interrupt group 2 TIN22 TIN23 input 3 Level Timer input interrupt 1 Timer input interrupt group 1 TIN16 TIN17 input 3 Level Timer input interrupt 0 Timer input interrupt group 0 TIN18 TIN19 input 3 Level Note T...

Page 128: ...CR4 Timer Input Interrupt Control Register 5 IMJTICR5 PWM Off Input Interrupt Control Register IPWMOFFCR PDC Input Error Detection Interrupt Control Register IPDCCR SIO2 3 Transmit Receive Interrupt Control Register ISIO23CR DMA5 9 Interrupt Control Register IDMA59CR Interrupt Vector Register IVECT H 0080 0060 CAN1 Transmit Receive Error Interrupt Control Register ICAN1CR H 0080 0062 H 0080 0064 B...

Page 129: ...vector table address for the accepted interrupt source are set in the IVECT Register The EIT handler reads the content of the IVECT Register using the LDH instruction to get the ICU vector table address needed When the IVECT Register is read out operations 1 through 4 below are automatically performed in hardware 1 Set the accepted new IMASK value NEW_IMASK in the IMASK Register 2 Clear the accept...

Page 130: ...ccepted The Interrupt Mask Register IMASK is used to set an interrupt mask to be compared with the priority level that has been set for each interrupt source i e the Interrupt Control Register ILEVEL bit to determine whether or not to accept the interrupt request When the Interrupt Vector Register IVECT described above is read out a new mask value NEW_IMASK is set in this IMASK Register Upon writi...

Page 131: ... W Writable for only clearing see the explanation below ___ The SBI System Break Interrupt is an interrupt generated by a falling edge of the SBI input signal When an SBI interrupt occurs the SBI Control Register SBIREQ SBI request bit is set to 1 The SBIREQ bit cannot be set in software To clear the SBIREQ bit after being set follow the procedure described below However do not perform this cleari...

Page 132: ...06C SIO1 Receive Interrupt Control Register ISIO1RXCR Address H 0080 006D SIO0 Transmit Interrupt Control Register ISIO0TXCR Address H 0080 006E SIO0 Receive Interrupt Control Register ISIO0RXCR Address H 0080 006F A D0 Conversion Interrupt Control Register IAD0CCR Address H 0080 0070 DMA0 4 Interrupt Control Register IDMA04CR Address H 0080 0071 TID1 Output Interrupt Control Register ITID1CR Addr...

Page 133: ...quest bit D3 or D11 When an interrupt request from internal peripheral I O occurs the IREQ interrupt request bit is set to 1 This bit can be set and cleared in software for only the edge input type of interrupt sources and cannot for the level type The IREQ bit when set for an interrupt request generated by an edge input type of interrupt source is automatically cleared to 0 upon reading the Inter...

Page 134: ...3 11 Data bus D5 7 13 15 3 F F set set clear IREQ Figure 5 3 2 Configuration of the Interrupt Control Register Edge Type Figure 5 3 3 Configuration of the Interrupt Control Register Level Type Interrupt priority resolving circuit Interrupt request from each peripheral equipment group Interrupt enabled D3 11 Data bus D5 7 13 15 RD 3 IREQ Read only circuit ILEVEL 0 7 levels Group interrupt ...

Page 135: ...lly compares its priority with the IMASK value to determine whether to forward an EI request to the CPU or keep it pending The relationship between ILEVEL values and the IMASK values at which interrupts are accepted is shown below Table 5 3 1 ILEVEL Settings and the Accepted IMASK Values LEVEL set value IMASK values at which interrupts are accepted 0 ILEVEL 000 Accepted when IMASK is 1 7 1 ILEVEL ...

Page 136: ...BB TMS0 output interrupt H 0000 00BC H 0000 00BF TID0 output interrupt H 0000 00C0 H 0000 00C3 TID1 output interrupt H 0000 00C4 H 0000 00C7 DMA0 4 interrupt H 0000 00C8 H 0000 00CB A D0 converter interrupt H 0000 00CC H 0000 00CF SIO0 receive interrupt H 0000 00D0 H 0000 00D3 SIO0 transmit interrupt H 0000 00D4 H 0000 00D7 SIO1 receive interrupt H 0000 00D8 H 0000 00DB SIO1 transmit interrupt H 0...

Page 137: ...rt Address A16 A31 Blank areas are reserved for future use Timer Input Interrupt 3 Handler Start Address A0 A15 Timer Input Interrupt 3 Handler Start Address A16 A31 Timer Input Interrupt 2 Handler Start Address A0 A15 Timer Input Interrupt 2 Handler Start Address A16 A31 Timer Input Interrupt 1 Handler Start Address A0 A15 Timer Input Interrupt 1 Handler Start Address A16 A31 Timer Input Interrup...

Page 138: ... 00F4 H 0000 00F6 H 0000 00F8 H 0000 00FA H 0000 00FC H 0000 00FE H 0000 0100 H 0000 0102 H 0000 0104 H 0000 0106 H 0000 0108 H 0000 010A H 0000 010C H 0000 010E CAN0 Transmit Receive Error Interrupt Handler Start Address A0 A15 CAN0 Transmit Receive Error Interrupt Handler Start Address A16 A31 Blank areas are reserved for future use A D1 Conversion Interrupt Handler Start Address A0 A15 A D1 Con...

Page 139: ...e interrupt request with the highest priority If the selected interrupt requests have the same ILEVEL value they are arbitrated according to the fixed hardware priority The ILEVEL of the finally selected interrupt request is compared with the IMASK value and if its priority is higher than the IMASK value an EI request for it is sent to the CPU Interrupt requests may be masked setting the Interrupt...

Page 140: ...00 00C0 H 0000 00C3 Level TID1 output interrupt IRQ17 H 0000 00C4 H 0000 00C7 Level DMA0 4 interrupt H 0000 00C8 H 0000 00CB Level A D0 converter interrupt H 0000 00CC H 0000 00CF Edge SIO0 receive interrupt H 0000 00D0 H 0000 00D3 Edge SIO0 transmit interrupt H 0000 00D4 H 0000 00D7 Edge SIO1 receive interrupt H 0000 00D8 H 0000 00DB Edge SIO1 transmit interrupt H 0000 00DC H 0000 00DF Edge A D1 ...

Page 141: ...values at which interrupts are accepted 0 ILEVEL 000 Accepted when IMASK is 1 7 1 ILEVEL 001 Accepted when IMASK is 2 7 2 ILEVEL 010 Accepted when IMASK is 3 7 3 ILEVEL 011 Accepted when IMASK is 4 7 4 ILEVEL 100 Accepted when IMASK is 5 7 5 ILEVEL 101 Accepted when IMASK is 6 7 6 ILEVEL 110 Accepted when IMASK is 7 7 ILEVEL 111 Not accepted interrupt disabled ...

Page 142: ...t reading the IVECT causes NEW_IMASK to be set in the IMASK Register and the accepted interrupt request to be cleared not cleared in the case of level recognized interrupt sources however The IVECT Register has set in it the 16 low order bits of the ICU vector table address for the accepted interrupt source Read the IVECT Register using a signed halfword load instruction LDH instruction to get the...

Page 143: ...to stack Save PSW to stack Save general purpose registers to stack Restore BPC Restore PSW Restore general purpose registers Read Interrupt Mask Register IMASK and save to stack IMASK H 0080 0000 PSW Register IE bit 1 PSW Register IE bit 0 Restore Interrupt Mask Register IMASK 1 2 3 4 6 7 8 5 9 10 10 1 8 5 Processing by interrupt handler for EI When enabling another interrupt in an interrupt ICU v...

Page 144: ...ignal regardless of how the PSW Register IE bit is set and cannot be masked 5 6 2 SBI Processing by Handler After processing for the SBI is finished always be sure to terminate or reset the system without returning to the program the CPU was executing when the interrupt occurred Figure 5 6 1 Example of Operation for SBI Interrupt H 0000 0010 BRA instruction SBI System Break Interrupt handler SBI S...

Page 145: ...al Flash Memory 6 4 Internal Flash Memory Related Registers 6 5 Programming the Internal Flash Memory 6 6 Boot ROM 6 7 Virtual flash Emulation Function 6 8 Connecting a Serial Programmer 6 9 Precautions on Rewriting Flash Memory CHAPTER 6 CHAPTER 6 INTERNAL MEMORY ...

Page 146: ...nection Connects to 32 bit bus Dual port By using the RTD Real time Debugger data can be read out monitored or written to any area of the internal RAM via serial communication from the outside independently of the CPU For details refer to Chapter 14 Real time Debugger 6 3 Internal Flash Memory Specifications of the internal flash memory are shown below Table 6 3 1 Specifications of the Internal Fl...

Page 147: ...address 1 address D8 D15 H 0080 07E4 Flash Control Register 1 FCNT1 Flash Mode Register FMOD Flash Status Register 1 FSTAT1 Flash Control Register 2 FCNT2 Flash Control Register 3 FCNT3 Flash Control Register 4 FCNT4 H 0080 07E6 H 0080 07E8 H 0080 07EA H 0080 07EC H 0080 07EE Virtual flash L Bank Register 0 FELBANK0 Virtual flash S Bank Register 0 FESBANK0 Note Virtual flash S Bank Register 1 FESB...

Page 148: ... 4 1 Flash Mode Register Flash Mode Register FMOD Address H 0080 07E0 The Flash Mode Register FMOD is a read only status register with FPMOD showing the status of the FP Flash Protect pin The flash memory is enabled for write only when FPMOD 1 Write to the flash memory executed when FPMOD 0 has no effect INTERNAL MEMORY 6 4 Internal Flash Memory Related Registers ...

Page 149: ... erasing the flash memory Flash Status Register 1 FSTAT1 Address H 0080 07E1 INTERNAL MEMORY 6 4 Internal Flash Memory Related Registers When reset H 01 D Bit Name Function R W 8 14 No functions assigned 0 15 FSTAT 0 Busy Ready Busy status 1 Ready The Flash Status Register 1 FSTAT1 is a read only status register used to know the status of whether the flash memory is being programmed or erased When...

Page 150: ... bit is used to determine whether the operation is under way or finished when programming or erasing the flash memory The programming erase operation is under way when FBUSY 0 or finished when FBUSY 1 2 ERASE auto erase operating status bit D10 The ERASE bit is used to determine whether an error occurred after the CPU has finished erasing the flash memory The erase operation terminated normally wh...

Page 151: ...ion for which this bit is set to 1 is that even when the write operation was executed a specified number of times repeatedly the flash memory could not be programmed Note This status register is provided within the flash memory so that by writing a read status command H 7070 to any address of the internal flash memory this register is enabled for readout For details refer to Section 6 5 Programmin...

Page 152: ...ontrol Register 1 FCNT1 consists of the following two bits that control the internal flash memory 1 FENTRY flash mode entry bit D3 The FENTRY bit controls state transition to flash E W enable mode Flash E W enable mode can be entered only when FENTRY 1 To set the FENTRY bit to 1 write 0 and then 1 to this bit successively while the FP pin high The FENTRY bit is cleared under the following conditio...

Page 153: ...olled using an interrupt Table 6 4 1 EI Vector Entry Transition by FENTRY FENTRY EI Vector Entry Address 0 Flash area H 0000 0080 1 Internal RAM area H 0080 4000 2 FEMMOD virtual flash emulation mode bit D7 The FEMMOD bit controls state transition to virtual flash emulation mode The CPU is placed in virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 For details refe...

Page 154: ... is disabled by setting the FPROT bit to 1 so that blocks of the flash memory protected by lock bits can be erased programmed To set the FPROT bit to 1 write 0 and then 1 to this bit successively while the FENTRY bit 1 The FPROT bit is cleared to 0 immediately after chip reset or by writing 0 to this bit pulling input on the FP pin low or resetting the FENTRY bit to 0 Figure 6 4 2 Protection Unloc...

Page 155: ...al level Erase margin up 1 Increases erase margin The Flash Control Register 3 FCNT3 controls the depth of erase levels when erasing the internal flash memory with an erase command By setting the FELEVEL bit is set to 1 the flash memory erase level can be deepened which will result in an increased reliability margin INTERNAL MEMORY 6 4 Internal Flash Memory Related Registers ...

Page 156: ...r program operation in the middle or initializing each status bit of Flash Status Register 2 FSTAT2 Setting the FRESET bit to 1 cancels the erase or program operation in the middle and initializes each status bit of the FSTAT2 Register to H 80 The FRESET bit is effective only when the FENTRY bit 1 Information of the FRESET bit is ignored unless the FENTRY bit 1 When programming or erasing the flas...

Page 157: ... Program erase flash memory Error detected Program erase operation terminated normally FRESET 0 Program erase flash memory FENTRY 0 Figure 6 4 3 Example for Using the FCNT4 Register INTERNAL MEMORY 6 4 Internal Flash Memory Related Registers ...

Page 158: ...ssed in halfwords 1 MODENL virtual flash emulation enable bit D0 After entering virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 set the MODENL bit to 1 and the virtual flash emulation function is enabled for the L bank area selected with LBANKAD bits 2 LBANKAD L bank address bits D8 D14 The LBANKAD bits select one of the L banks divided in units of 8 KB Use these...

Page 159: ...virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 set the MODENS bit to 1 and the virtual flash emulation function is enabled for the S bank area selected with SBANKAD bits 2 SBANKAD S bank address bits D8 D15 The SBANKAD bits select one of the S banks divided in units of 4 KB Use these eight SBANKAD bits to set the start address A12 A19 of the 32 bit address of th...

Page 160: ...ransferred into the RAM to write to the internal flash memory 2 When a write program already exists in the internal flash memory Set the FP pin high MOD0 low and MOD1 low to enter single chip mode Transfer the flash write program from the internal flash memory in which it was prepared beforehand into the internal RAM Then jump to the RAM and by using the program in the RAM set the Flash Control Re...

Page 161: ...ramming the Internal Flash Memory EI vector entry Internal ROM area Internal RAM H 0000 0080 H 0000 0000 H 00FF FFFF H 0080 4000 Internal ROM area Internal RAM H 0080 3FFF Flash E W enable mode FENTRY 1 Normal mode FENTRY 0 H 0000 0000 H 0080 3FFF EI vector entry H 0080 4000 H 0080 4000 H 00FF FFFF ...

Page 162: ...ory Step 2 Step 3 M32R E M32R E M32R E External device Flash write data Flash memory MOD0 L Boot ROM MOD1 L FP H MOD0 H MOD1 L FP H MOD0 H RESET L RESET H RESET H Write data Flash memory Boot ROM Flash write program Boot ROM External device Write data Set the FP pin high MOD0 pin high and MOD1 pin low to place the microcomputer in boot mode Negate reset then start up from the boot program Transfer...

Page 163: ...oot program Select mode Negate reset Write to the flash memory using the boot program Set up using the boot program Figure 6 5 3 Timing at Which Writing to the Internal Flash Memory when no write programs exist in the flash memory INTERNAL MEMORY 6 5 Programming the Internal Flash Memory ...

Page 164: ... write program exists in the flash memory Ordinary program in the flash memory is being executed Step 2 Step 3 M32R E M32R E M32R E External device Flash write data Flash memory MOD0 L Boot ROM MOD1 L FP H MOD0 L MOD1 L FP H MOD0 L Flash memory Boot ROM Flash write program Boot ROM Set the FP pin high MOD0 pin low and MOD1 pin low to place the microcomputer in single chip mode After inspecting the...

Page 165: ...sing the flash write program Flash rewrite starts Flash mode ON Flash mode OFF Transfer the flash rewrite program to the RAM Set up using the flash write program Figure 6 5 5 Timing at Which Writing to the Internal Flash Memory when write program exists in the flash memory INTERNAL MEMORY 6 5 Programming the Internal Flash Memory ...

Page 166: ...ess start address flash E W H 0000 0000 H 0080 4000 enable 1 1 0 0 Boot mode Boot program area Flash area start address H 0000 0080 H 8000 0000 1 1 0 1 Boot mode Boot program area Internal RAM flash E W start address start address enable H 8000 0000 H 0080 4000 1 0 1 1 External extended Flash memory Internal RAM mode flash start address start address E W enable H 0000 0000 H 0080 4000 1 1 reserved...

Page 167: ...Register H 0080 0708 MOD0DT and MOD1DT bits P8 Port Data Register P8DATA Address H 0080 0708 INTERNAL MEMORY 6 5 Programming the Internal Flash Memory When reset Indeterminate D Bit Name Function R W 0 MOD0DT 0 MOD0 pin low MOD0 data 1 MOD0 pin high 1 MOD1DT 0 MOD1 pin low MOD1 data 1 MOD1 pin high 2 P82DT When the direction bit is set to 0 Port P82 data input mode by Port Direction Register 3 P83...

Page 168: ... flash entry FENTRY bit to 1 Execute flash E W command and various read commands Note Change to the flash E W program Wait for 1 µs as counted by hardware or software timer Jump to flash memory or reset the microcomputer Change to normal mode Check MOD0 1 and FP pin levels OK NO END FMOD H 0080 07E0 FPMOD P8DATA H 0080 0708 MOD0DT MOD1DT Note For details about each command refer to Section 6 5 3 P...

Page 169: ... be issued in flash E W enable mode are listed below Note During flash E W enable mode the flash memory cannot be accessed for read write wordwise Table 6 5 2 Commands in Flash E W Enable Mode Command Name Command Data Issued Read Array command H FFFF Page Program command H 4141 Lock Bit Program command H 7777 Block Erase command H 2020 Erase All Unlock Blocks command H A7A7 Read Status Register c...

Page 170: ...ormed 3 Lock Bit Program command The flash memory can be protected against write and erase in units of blocks The Lock Bit Program command is used to protect any memory block Write the lock bit command data H 7777 to any address of the internal flash memory Next write the Verify command data H D0D0 to the last even address of the memory block to be protected and this memory block is protected agai...

Page 171: ...F H 0001 0000 Internal flash memory area 256 KB Block 2 Block 3 Block 4 H 0000 5FFF H 0000 6000 64KB H 0002 FFFF Block 5 64KB Block 0 Block 6 Uneven blocks Even blocks H 0003 0000 H 0003 FFFF H 0004 0000 Block 1 Figure 6 5 7 M32172F2 M32173F2 Flash Memory Block Configuration INTERNAL MEMORY 6 5 Programming the Internal Flash Memory ...

Page 172: ...ernal flash memory and all of the unprotected memory blocks are erased 6 Read Status Register command The Read Status Register command reads the content of Flash Status Register 2 FSTAT2 that indicates whether programming or erase operation on flash memory has terminated normally or in an error To read Flash Status Register 2 write the command data H 7070 to any address of the internal flash memor...

Page 173: ...ead are 0 it means that the memory block is protected If the FLBST0 lock bit 0 and FLBST1 lock bit 1 bits of the data you read are 1 it means that the memory block is not protected Lock Bit Status Register FLBST INTERNAL MEMORY 6 5 Programming the Internal Flash Memory When reset Indeterminate D Bit Name Function R W 0 No functions assigned 1 FLBST0 0 Protected Lock bit 0 1 Not protected 2 8 No fu...

Page 174: ...and H A7A7 to erase the memory block you want to unprotect This is the only way to remove protection from a memory block The lock bits cannot alone be set to 1 c Lock bit status when reset The lock bits are nonvolatile bits so that they are unaffected by resetting or powering off the microcomputer 9 Command execution flow The diagrams below show command execution flow for each command used Figure ...

Page 175: ...timer FSTAT bit 1 TIME OUT 0 5s YES NO Forcibly terminated YES NO Go to the next page Note 1 Start writing from the beginning of the 256 byte boundary lower address H 00 Note 2 After programming operation starts the flash memory is automatically in the same condition as when the Read Status Register command is entered There is no need to issue the Read Status Register command until entering any ot...

Page 176: ... 1 TIME OUT 0 5s YES NO Forcibly terminated YES NO Note 1 After programming operation starts the flash memory is automatically in the same condition as when the Read Status Register command is entered There is no need to issue the Read Status Register command until entering any other command Note 2 Inspect the Flash Status Register 2 FSTAT2 ERASE auto erase operating status WRERR1 program operatin...

Page 177: ...AT bit 1 TIME OUT 1s YES NO Forcibly terminated YES NO Note 1 After erase operation starts the flash memory is automatically in the same condition as when the Read Status Register command is entered There is no need to issue the Read Status Register command until entering any other command Note 2 Inspect the Flash Status Register 2 FSTAT2 ERASE auto erase operating status WRERR1 program operating ...

Page 178: ...t 1 TIME OUT 10s YES NO Forcibly terminated YES NO Note 1 After erase operation starts the flash memory is automatically in the same condition as when the Read Status Register command is entered There is no need to issue the Read Status Register command until entering any other command Note 2 Inspect the Flash Status Register 2 FSTAT2 ERASE auto erase operating status WRERR1 program operating stat...

Page 179: ...ss Read any internal flash memory address END Figure 6 5 13 Read Status Register Command Figure 6 5 14 Clear Status Register Command Figure 6 5 15 Read Lock Bit Status Register Command INTERNAL MEMORY 6 5 Programming the Internal Flash Memory START Write Read Lock Bit Status Register command H 7171 to any internal flash memory address Read the last even address of the desired block END ...

Page 180: ... x number of blocks 350 ms Total flash programming time entire 256 KB area When communicating in UART mode at a rate of 57 600 bps the flash programming time is extremely short as compared with the serial communication time and can therefore be ignored In this case the flash programming time can be calculated using the equation below 50 5 s When writing data at high speed by increasing the serial ...

Page 181: ...rates with no wait cycles when internal CPU memory clock 40 MHz Internal bus connection Connects to a 32 bit bus Readout Can only be read out when FP 1 MOD0 1 and MOD1 0 If read out in any other mode the read value is indeterminate Cannot be accessed for write Other Because the boot ROM area is a reserved area that can only be used during boot mode the program in it cannot be modified INTERNAL MEM...

Page 182: ...s of flash memory specified by the Virtual Flash Bank Register Therefore applications that require changes of data during program operation can have data dynamically changed using 8 or 4 Kbytes of RAM area The RAM used for virtual flash emulation can be accessed for read and write from both the internal RAM and the internal flash memory areas When this function is used in combination with the inte...

Page 183: ...0 A000 H 0080 B000 RAM bank L block 1 FELBANK1 8 Kbytes RAM bank L block 2 FELBANK2 8 Kbytes RAM bank S block 0 FESBANK0 4 Kbytes RAM bank S block 1 FESBANK1 4 Kbytes H 0080 BFFF Figure 6 7 2 Configuration of the M32173F2 s Internal RAM Banks INTERNAL MEMORY 6 7 Virtual flash Emulation Function ...

Page 184: ... with the address H 0080 A000 In this way the M32172F2 can have two 8 Kbyte L banks selected For the M32173F2 three 8 Kbyte L banks and two 4 Kbyte S banks for a total of up to five banks can be selected Note1 If the Virtual Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual Flash Bank Registers the internal RAM area 8 or 4 Kbyte to be replaced with is sel...

Page 185: ...reas of the M32172F2 Divided in Units of 8 Kbytes Figure 6 7 4 Virtual Flash Emulation Areas of the M32172F2 Divided in Units of 8 Kbytes INTERNAL MEMORY 6 7 Virtual flash Emulation Function H 0000 0000 H 0000 2000 Internal flash L bank 1 8 Kbytes L bank 0 8 Kbytes H 0000 4000 L bank 2 8 Kbytes L bank 31 8 Kbytes L bank 30 8 Kbytes H 0003 E000 H 0003 C000 Internal RAM 8 Kbytes 8 Kbytes 8 Kbytes 4 ...

Page 186: ...ore Virtual Flash Bank Registers the internal RAM area to be replaced with is selected by priority FELBANK0 FELBANK1 FELBANK2 FESBANK0 FESBANK1 Note 2 When access is made to the 4 Kbyte area S bank selected by Virtual Flash S Bank Register 0 or 1 what is actually accessed is the internal RAM area During virtual flash emulation mode the RAM can be read and written to from both the internal RAM and ...

Page 187: ... 00 H 02 H 04 H 3C H 3E Note Note Set seven bits A12 A18 of the start address 32 bit of each L bank of flash memory divided every 8 kbyte in the Virtual Flash L Bank Register L bank address LBANKAD bits Note Set eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 kbyte in the Virtual Flash S Bank Register S bank address SBANKAD bits Figure 6 7 6 Values Set...

Page 188: ...0 H 0003 E000 H 0003 F000 H 00 H 01 H 02 H 3E H 3F Note Note Set eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbyte in the Virtual Flash S Bank Register S bank address SBANKAD bits Figure 6 7 8 Values Set in the M32173F2 s Virtual Flash Bank Register when Divided in Units of 4 Kbyte INTERNAL MEMORY 6 7 Virtual flash Emulation Function ...

Page 189: ...ulation mode the internal RAM area H 0080 4000 through H 0080 7FFF for the M32172F2 or H 0080 4000 through H 0080 BFFF for the M32173F2 can be accessed as internal RAM Figure 6 7 9 Setup Sequence for Virtual Flash Emulation Mode INTERNAL MEMORY 6 7 Virtual flash Emulation Function Set RAM location address in virtual flash bank register LBANKAD address A12 A18 SBANKAD address A12 A19 Write flash da...

Page 190: ...MEMORY 6 7 Virtual flash Emulation Function Replacement area Flash RAM block 0 Data write to RAM0 RAM block 1 1 Operation when reset Replace Data write to RAM1 2 Program operation with RAM block 0 RAM block 0 Flash Initial value Initial value RAM block 0 RAM block 1 Replace 3 Changing program operation from RAM block 0 to RAM block 1 RAM block 0 Flash Initial value RAM block 0 RAM block 1 RAM bloc...

Page 191: ... Replace 5 Changing program operation from RAM block 1 to RAM block 0 RAM block 0 Flash Initial value RAM block 0 RAM block 1 RAM block 1 Bank xx Specify bank xx Specify bank xx settings have no effect 6 Go to item 2 Note shows the effective area Figure 6 7 11 Usage Example for Virtual Flash Emulation 2 2 INTERNAL MEMORY 6 7 Virtual flash Emulation Function ...

Page 192: ...eceive enable output Pullup required FP 94 Flash memory protect MOD0 92 Operation mode 0 MOD1 93 Operation mode 1 Connect to ground _____ RESET 91 Reset XIN 4 Clock input XOUT 5 Clock output VCNT 7 PLL circuit control input OSC VCC 6 PLL circuit power supply Connect to 3 3 V power supply OSC VSS 3 PLL circuit ground Connect to ground VREF0 42 A D converter reference voltage input Connect to 5 V po...

Page 193: ...V power supply Connects to the 3 3 V power supply P85 TXD1 P86 RXD1 P87 SCLKI1 SCLKO1 P84 SCLKI0 SCLKO0 Connector Flash programmer signals MOD0 FP RESET VSS Sets microcomputer operating conditions XIN XOUT VCNT AVSS0 OSC VSS To the system circuit RxD input TxD output SCLKO output BUSY input MOD0 output FP output RESET output GND output 5 V input User system board FVCC Connects to the 5 V power sup...

Page 194: ...th the system that are used by a serial programmer take measures not to affect the system when connecting a serial programmer If the flash memory needs to be protected set any ID in the flash memory protect ID check area H 0000 0084 H 0000 0093 If the flash memory does not need to be protected fill the flash memory protect ID check area H 0000 0084 H 0000 0093 with data H FF INTERNAL MEMORY 6 9 Pr...

Page 195: ...7 1 Outline of Reset 7 2 Reset Operation 7 3 Internal State Immediately after Reset 7 4 Precautions to Be Taken Immediately after Reset CHAPTER 7 CHAPTER 7 RESET ...

Page 196: ... 7 2 1 Power on Reset _____ When powering on the microcomputer hold the input signal on the RESET pin low until the internal multiply by 4 clock generator becomes oscillating stably 7 2 2 Reset during Operation _____ To reset the microcomputer during operation hold the RESET input low for more than four clock periods of XIN signal 7 2 3 Reset Vector Movement during Flash Rewrite When placed in boo...

Page 197: ...l where each internal peripheral I O in interest is described Table 7 3 1 Internal State Immediately after Reset Register State after reset PSW CR0 B 0000 0000 0000 0000 00 000 0000 0000 BSM BIE BC bits indeterminate CBR CR1 H 0000 0000 C bit 0 SPI CR2 Indeterminate SPU CR3 Indeterminate BPC CR6 Indeterminate PC H 0000 0000 Executed beginning with address H 0000 0000 Note ACC Accumulator Indetermi...

Page 198: ...put Input Input MOD1 and FP Port P0 P1 Input Input Input Input P2 P3 Input Input Hi Z Input P41 Input Input Hi Z Input P42 P43 P45 P46 P47 Input Input Hi Z Input P6 P7 Input Input Input Input P8 P12 Input Input Input Input P9 P13 P10 P15 P11 P17 P220 P221 P225 Input Input Hi Z Input DA0 DA1 Input Input Input Input AD0IN0 7 Input Input Input Input AD1IN0 3 JTAG JTMS Input Input Input Input JTCK Inp...

Page 199: ... disabled against input in order to prevent electric current from flowing through the pins To use any ports in input mode enable them for input using the Port Input Function Enable Register PIEN s PIEN0 bit For details refer to Section 8 3 Input Output Port Related Registers RESET 7 4 Precautions to Be Taken Immediately after Reset ...

Page 200: ...7 7 6 Rev 1 0 This is a blank page RESET 7 4 Precautions to Be Taken Immediately after Reset ...

Page 201: ... Input Output Ports 8 2 Selecting Pin Functions 8 3 Input Output Port Related Registers 8 4 Port Peripheral Circuits 8 5 Precautions on Using Input Output Port CHAPTER 8 CHAPTER 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS ...

Page 202: ...le function pins The pin functions are selected depending on selected chip operation mode or by using the input output port operation mode registers If any internal peripheral I O has still another function the register for that internal peripheral I O needs to be set to select the desired pin function Each input port contains a port input function enable bit that may be used to prevent electric c...

Page 203: ... input only port Pin function Dual functions with peripheral I O or external extended signals or multiple functions with two or more peripheral I O functions Pin function P0 P4 Note2 P225 Depends on CPU operation mode determined by setting selection MOD0 and MOD1 pins P6 Note3 P22 Selected by setting input output port operation mode registers However peripheral I O pin functions are selected using...

Page 204: ...nded signal pin or input output port pin Note 2 VCC VSS Processor mode External extended signal pin External extended signal pin VCC VCC Reserved use inhibited Note 1 VCC connects to 5 V and VSS connects to GND Note 2 Only when the CPU is operating in external extended mode P0 P4 except P46 have their pin functions switched by setting operation mode registers Only when the PCU is operating in exte...

Page 205: ...N14 TIN23 AD1IN14 TXD2 CTX0 A12 CS2 Note3 BCLK WR BLW BLE BHW BHE CRX0 RXD2 TIN8 TXD7 AD0IN15 TIN9 RXD7 AD1IN15 SBI TIN11 AD1IN7 TIN10 AD1IN6 P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P14 P15 P5 Chip operation mode settings Note1 Reserved P16 P17 P18 P19 P20 P21 P22 TIN16 PWMOFF0 AD0IN11 P13 Input output port operation mode register settings Input output port operation mode register settings Note2 No...

Page 206: ...a Register P0DATA P2 Data Register P2DATA P4 Data Register P4DATA P6 Data Register P6DATA P8 Data Register P8DATA P10 Data Register P10DATA P1 Data Register P1DATA P3 Data Register P3DATA P7 Data Register P7DATA P9 Data Register P9DATA P11 Data Register P11DATA P15 Data Register P15DATA H 0080 0720 H 0080 0722 H 0080 0724 H 0080 0726 H 0080 0728 H 0080 072A H 0080 072C H 0080 072E P0 Direction Reg...

Page 207: ...ode Register P22MOD H 0080 0756 Blank areas are reserved for future use Note The registers enclosed in the thick frames must always be accessed in halfwords H 0080 0742 H 0080 0740 P0 Operation Mode Register P0MOD P1 Operation Mode Register P1MOD P2 Operation Mode Register P2MOD P3 Operation Mode Register P3MOD P4 Operation Mode Register P4MOD H 0080 0764 H 0080 0766 H 0080 0768 H 0080 076A H 0080...

Page 208: ...s respectively Note 4 Ports P93 P97 P124 P127 P130 P137 P172 P173 and P221 are available for only input mode Writing to the P93DT P97DT P124 127DT P130 P137DT P172DT P173DT and P221DT bit has no effect 8 3 1 Port Data Registers P0 Data Register P0DATA Address H 0080 0700 P1 Data Register P1DATA Address H 0080 0701 P2 Data Register P2DATA Address H 0080 0702 P3 Data Register P3DATA Address H 0080 0...

Page 209: ...and P221DIR bits are nonexistent Note 5 Ports P80 and P81 are available for only input mode The P80DIR and P81DIR bits are nonexistent 8 3 2 Port Direction Registers P0 Direction Register P0DIR Address H 0080 0720 P1 Direction Register P1DIR Address H 0080 0721 P2 Direction Register P2DIR Address H 0080 0722 P3 Direction Register P3DIR Address H 0080 0723 P4 Direction Register P4DIR Address H 0080...

Page 210: ... operation mode 1 P01 2 P02MOD 0 DB2 Port P02 operation mode 1 P02 3 P03MOD 0 DB3 Port P03 operation mode 1 P03 4 P04MOD 0 DB4 Port P04 operation mode 1 P04 5 P05MOD 0 DB5 Port P05 operation mode 1 P05 6 P06MOD 0 DB6 Port P06 operation mode 1 P06 7 P07MOD 0 DB7 Port P07 operation mode 1 P07 Note The value set in the P0 Operation Mode Register takes effect only when the CPU operates in external ext...

Page 211: ...ion mode 1 P13 12 P14MOD 0 DB12 Port P14 operation mode 1 P14 13 P15MOD 0 DB13 Port P15 operation mode 1 P15 14 P16MOD 0 DB14 Port P16 operation mode 1 P16 15 P17MOD 0 DB15 Port P17 operation mode 1 P17 Note The value set in the P1 Operation Mode Register takes effect only when the CPU operates in external extended mode INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers D...

Page 212: ...peration mode 1 P23 4 P24MOD 0 A27 Port P24 operation mode 1 P24 5 P25MOD 0 A28 Port P25 operation mode 1 P25 6 P26MOD 0 A29 Port P26 operation mode 1 P26 7 P27MOD 0 A30 Port P27 operation mode 1 P27 Note The value set in the P2 Operation Mode Register takes effect only when the CPU operates in external extended mode INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers D0 1...

Page 213: ...P31 10 P32MOD 0 A17 Port P32 operation mode 1 P32 11 P33MOD 0 A18 Port P33 operation mode 1 P33 12 P34MOD 0 A19 Port P34 operation mode 1 P34 13 P35MOD 0 A20 Port P35 operation mode 1 P35 14 P36MOD 0 A21 Port P36 operation mode 1 P36 15 P37MOD 0 A22 Port P37 operation mode 1 P37 Note The value set in the P3 Operation Mode Register takes effect only when the CPU operates in external extended mode I...

Page 214: ..._ 0 RD Port P43 operation mode 1 P43 4 P44MOD ___ 0 CS0 Port P44 operation mode 1 P44 5 P45MOD ___ 0 CS1 Port P45 operation mode 1 P45 6 No functions assigned 0 7 P47MOD 0 A14 Port P47 operation mode 1 P47 Note The value set in the P4 Operation Mode Register takes effect only when the CPU operates in external extended mode INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Register...

Page 215: ... operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK TXD3 12 P74MOD 0 P74 Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P77 Port P77 operation mode 1 RTDCLK INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72M...

Page 216: ...OD 0 P82 Port P82 operation mode 1 TXD0 3 P83MOD 0 P83 Port P83 operation mode 1 RXD0 4 P84MOD 0 P84 Port P84 operation mode 1 SCLKI0 SCLKO0 5 P85MOD 0 P85 Port P85 operation mode 1 TXD1 6 P86MOD 0 P86 Port P86 operation mode 1 RXD1 7 P87MOD 0 P87 Port P87 operation mode 1 SCLKI1 SCLKO1 Note Ports P80 and P81 are nonexistent INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Regist...

Page 217: ...s assigned 0 11 P93MOD 0 P93 Port P93 operation mode 1 RXD3 12 P94MOD 0 P94 Port P94 operation mode 1 TDX6 13 P95MOD 0 P95 Port P95 operation mode 1 RXD6 14 P96MOD 0 P96 Port P96 operation mode 1 CTX1 15 No functions assigned 0 Note 1 Ports P90 P92 are nonexistent Note 2 P97 is a CAN1 input only pin INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 218: ...1 P101MOD 0 P101 Port P101 operation mode 1 TO9 2 P102MOD 0 P102 Port P102 operation mode 1 TO10 3 P103MOD 0 P103 Port P103 operation mode 1 TO11 4 P104MOD 0 P104 Port P104 operation mode 1 TO12 SCLKI4 5 P105MOD 0 P105 Port P105 operation mode 1 TO13 SCLKO4 6 P106MOD 0 P106 Port P106 operation mode 1 TO14 TXD4 7 P107MOD 0 P107 Port P107 operation mode 1 TO15 RXD4 INPUT OUTPUT PORTS AND PIN FUNCTIO...

Page 219: ...O0 9 P111MOD 0 P111 Port P111 operation mode 1 TO1 10 P112MOD 0 P112 Port P112 operation mode 1 TO2 11 P113MOD 0 P113 Port P113 operation mode 1 TO3 12 P114MOD 0 P114 Port P114 operation mode 1 TO4 SCLKI5 13 P115MOD 0 P115 Port P115 operation mode 1 TO5 SCLKO5 14 P116MOD 0 P116 Port P116 operation mode 1 TO6 TXD5 15 P117MOD 0 P117 Port P117 operation mode 1 TO7 RXD5 INPUT OUTPUT PORTS AND PIN FUNC...

Page 220: ...ction R W 0 3 No functions assigned 0 4 P124MOD 0 P124 Port P124 operation mode 1 TIN0A 5 P125MOD 0 P125 Port P125 operation mode 1 TIN0B 6 P126MOD 0 P126 Port P126 operation mode 1 TIN1A 7 P127MOD 0 P127 Port P127 operation mode 1 TIN1B Note Ports P120 P123 are nonexistent INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 221: ...P131 Port P131 operation mode 1 TIN17 PWMOFF1 10 P132MOD 0 P132 Port P132 operation mode 1 TIN18 11 P133MOD 0 P133 Port P133 operation mode 1 TIN19 12 P134MOD 0 P134 Port P134 operation mode 1 TIN20 13 P135MOD 0 P135 Port P135 operation mode 1 TIN21 14 P136MOD 0 P136 Port P136 operation mode 1 TIN22 15 P137MOD 0 P137 Port P137 operation mode 1 TIN23 Note Ports P130 P137 are input only pins INPUT O...

Page 222: ... H 00 D Bit Name Function R W 8 P150MOD 0 P150 Port P150 operation mode 1 TIN8 TXD7 9 10 No functions assigned 0 11 P153MOD 0 P153 Port P153 operation mode 1 TIN9 TXD7 12 15 No functions assigned 0 Note Ports P151 P152 P154 P157 are nonexistent INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 223: ...unctions assigned 0 10 P172MOD 0 P172 Port P172 operation mode 1 TIN10 11 P173MOD 0 P173 Port P173 operation mode 1 TIN11 12 P174MOD 0 P174 Port P174 operation mode 1 TXD2 13 P175MOD 0 P175 Port P175 operation mode 1 RXD2 14 15 No functions assigned 0 Note Ports P170 P171 P176 P177 are nonexistent INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 224: ...igned 0 5 P225MOD 0 P225 Port P225 operation mode 1 use inhibited 6 7 No functions assigned 0 Note 1 P221 is a CAN0 input only pin Note 2 P225 has its pin function altered depending on how the MOD0 and MOD1 pins are set Use of this port requires caution because it has a debug event function Note 3 P222 P224 P226 and P227 are nonexistent INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Re...

Page 225: ...0080 0764 D0 1 2 3 4 5 6 D7 P46SMOD When reset H 00 D Bit Name Function R W 0 5 No functions assigned 0 6 P46SMOD 0 A13 Selects port P46 peripheral output _______ 1 CS3 7 No functions assigned 0 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 226: ... D8 9 10 11 12 13 14 D15 P73SMOD When reset H 00 D Bit Name Function R W 8 10 No functions assigned 0 11 P73SMOD __________ 0 HACK Selects port P73 peripheral output 1 TXD3 12 15 No functions assigned 0 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 227: ...ral output 1 TXD4 7 P107SMOD 0 TO15 Selects port P107 peripheral output 1 RXD4 8 11 No functions assigned 0 12 P114SMOD 0 TO4 Selects port P114 peripheral output 1 SCLKI5 13 P115SMOD 0 TO5 Selects port P115 peripheral output 1 SCLKO5 14 P116SMOD 0 TO6 Selects port P116 peripheral output 1 TXD5 15 P117SMOD 0 TO7 Selects port P117 peripheral output 1 RXD5 Note This register must always be accessed i...

Page 228: ...S AND PIN FUNCTIONS 8 3 Input Output Port Related Registers D8 9 10 11 12 13 14 D15 P150SMOD P153SMOD When reset H 00 D Bit Name Function R W 8 P150SMOD 0 TIN8 Port P150 operation mode 1 TXD7 9 10 No functions assigned 11 P153SMOD 0 TIN9 Port P153 operation mode 1 RXD7 12 15 No functions assigned 0 ...

Page 229: ...unction R W 0 4 No functions assigned 0 5 P225SMOD 0 A12 Selects port P225 peripheral output ___ 1 CS2 6 7 No functions assigned 0 Note The value set in the P22 Peripheral Output Select Register takes effect only when the CPU operates in external extended mode INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers ...

Page 230: ...be controlled by the port input function enable bit in each mode are listed below Table 8 3 1 Pins Controllable by Port Input Function Enable Bit Mode Name Controllable Pin Noncontrollable Pin P00 P07 P10 P17 P20 P27 P64 P93 P97 P30 P37 P41 P47 P61 P63 P124 P127 Single chip P70 P77 P82 P87 P94 P96 P130 P137 P221 P100 P107 P110 P117 FP MOD0 MOD1 RESET P150 P153 P174 P175 P220 P225 P61 P63 P70 P77 P...

Page 231: ...eration mode register Input function enable Port output latch P70 BCLK WR P76 RTDACK P82 TXD0 P85 TXD1 P94 TXD6 P96 CTX1 P174 TXD2 P220 CTX0 Operation mode register Direction register Port output latch Data bus DB0 DB15 Peripheral function output Input function enable Note 2 denotes a pin Note 3 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE Note 1 Althou...

Page 232: ...Port output latch Data bus DB0 DB15 WAIT Input function enable Note 2 denotes a pin Note 3 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE Note 1 Although P46 P61 P63 and P225 serve as external bus interface control signal pins during external extended and processor modes their functional description in this block diagram is omitted INPUT OUTPUT PORTS AND ...

Page 233: ...function enable Port output latch Peripheral function output selector Peripheral function output 1 Peripheral function output 2 P75 RTDRXD P77 RTDCLK P83 RXD0 P86 RXD1 P175 RXD2 Data bus DB0 DB15 Direction register Operation mode register Input function enable Port output latch Peripheral function input Note 1 denotes a pin Note 2 denotes a parasitic diode Make sure the voltage applied to each por...

Page 234: ...n select bit Internal external clock select bit SCLKOi output RESET XIN JTRST Input function enable MOD0 MOD1 MOD0 MOD1 FP FP JTDI JTCK JTMS RESET XIN JTRST JTDI JTCK JTMS Note 1 denotes a pin Note 2 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE JTDO JTDO OSC VCC VCCI VDD VCCE OSC VCC VCCI VDD VCCE INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 4 Port Peripheral...

Page 235: ...P137 TIN23 AD1IN14 P172 TIN10 AD1IN9 P173 TIN11 AD1IN7 P95 RXD5 AD1IN8 P150 TIN8 TXD7 AD0IN15 Data bus DB0 DB15 Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input A D input P97 CRX1 P221 CRX0 Data bus DB0 DB15 CRX0 CRX1 RD Note 1 denotes a pin Note 3 denotes a parasitic diode Ma...

Page 236: ...ut disable P104 TO12 SCLKI4 P114 TO4 SCLKI5 Data bus DB0 DB15 Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input PWM output disable Note 1 denotes a pin Note 2 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE INPUT OUTPUT PORTS AND PIN FU...

Page 237: ...tput 2 P107 TO15 RXD4 P117 TO7 RXD5 Data bus DB0 DB15 Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input Note 1 denotes a pin Note 2 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE Figure 8 4 7 Port Peripheral Circuit Diagram 7 INPUT OUT...

Page 238: ...n input 2 Peripheral function input 1 Peripheral function input 2 A D input P153 TIN9 RXD7 AD1IN15 Operation mode register Input function enable A D input P130 TIN16 PWMOFF0 AD0IN11 P131 TIN17 PWMOFF1 AD1IN11 Data bus DB0 DB15 Note 1 denotes a pin Note 2 denotes a parasitic diode Make sure the voltage applied to each port will not exceed VCCE INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 4 Port Periphera...

Page 239: ... reset the Port Data Register values are indeterminate Therefore write the initial output value to the Port Data Register before setting the Port Direction Register for output Note that if the Port Direction Register is set for output before writing to the Port Data Register an indeterminate value may be output for a while until the write data is set in the Port Data Register ...

Page 240: ...8 8 40 Rev 1 0 This is a blank page INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 5 Precautions on Input Output Ports ...

Page 241: ...9 1 Outline of DMAC 9 2 DMAC Related Registers 9 3 Functional Description of DMAC 9 4 Precautions on Using DMAC CHAPTER 9 CHAPTER 9 DMAC ...

Page 242: ...annel 9 fixed priority Maximum transfer rate 13 3 Mbytes per second when internal peripheral clock 20 MHz Interrupt request Group interrupt request can be generated when any transfer count register underflows Transfer area 64 Kbytes in H 0080 0000 through H 0080 FFFF transferable in the entire internal RAM and SFR area DMAC 9 1 Outline of DMAC Note The DMA channels can be cascaded in the manner sh...

Page 243: ...ss register Destination address register Transfer count register udf Timer TID0_udf ovf Timer TID1_udf ovf Timer TIN16 input signal Timer TIN18 input signal Timer TOM07_udf Serial I O 5 reception completed One DMA9 transfer completed PD module PD_CMP0 PD module PD_CMP1 DMA request selector DMA channel 3 Software start Serial I O 1 reception completed All DMA1 transfers completed Source address reg...

Page 244: ...or DMA channel 8 Software start Serial I O 3 reception completed All DMA1 transfers completed Source address register Destination address register Transfer count register udf Timer TID0_udf ovf Timer TID1_udf ovf Timer TIN16 input signal Timer TIN21 input signal Timer TOM17_udf Serial I O 6 transmit buffer empty One DMA9 transfer completed PD module PD_CMP0 PD module PD_CMP1 All DMA3 transfers com...

Page 245: ...DMA5 Channel Control Register DM5CNT DMA5 Transfer Count Register DM5TCT DMA6 Channel Control Register DM6CNT DMA6 Transfer Count Register DM6TCT H 0080 042C H 0080 042E H 0080 043C H 0080 043E DMA7 Channel Control Register DM7CNT DMA7 Transfer Count Register DM7TCT H 0080 041A H 0080 041C H 0080 041E Blank areas are reserved for future use DMA0 Source Address Register DM0SA DMA0 Destination Addre...

Page 246: ...on Register DM9SRI H 0080 0470 H 0080 0472 H 0080 0474 H 0080 0476 H 0080 0478 Blank areas are reserved for future use DMA3 Source Address Register DM3SA DMA3 Destination Address Register DM3DA DMA8 Source Address Register DM8SA DMA8 Destination Address Register DM8DA DMA4 Source Address Register DM4SA DMA4 Destination Address Register DM4DA DMA9 Source Address Register DM9SA DMA9 Destination Addr...

Page 247: ... request transfer completed 01 A D0 conversion completed 10 Timer TOM00_udf 11 Extended request cause Note 4 TENL0 0 Disables transfer DMA0 transfer enable 1 Enables transfer 5 TSZSL0 0 16 bits Selects DMA0 transfer size 1 8 bits 6 SADSL0 0 Fixed Selects DMA0 source address direction 1 Increment 7 DADSL0 0 Fixed Selects DMA0 destination 1 Increment address direction W Only writing 0 is effective W...

Page 248: ...mpleted 4 TENL1 0 Disables transfer DMA1 transfer enable 1 Enables transfer 5 TSZSL1 0 16 bits Selects DMA1 transfer size 1 8 bits 6 SADSL1 0 Fixed Selects DMA1 source address direction 1 Increment 7 DADSL1 0 Fixed Selects DMA1 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended request c...

Page 249: ...sfer completed 4 TENL2 0 Disables transfer DMA2 transfer enable 1 Enables transfer 5 TSZSL2 0 16 bits Selects DMA2 transfer size 1 8 bits 6 SADSL2 0 Fixed Selects DMA2 source address direction 1 Increment 7 DADSL2 0 Fixed Selects DMA2 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended re...

Page 250: ...d request cause Note 4 TENL3 0 Disables transfer DMA3 transfer enable 1 Enables transfer 5 TSZSL3 0 16 bits Selects DMA3 transfer size 1 8 bits 6 SADSL3 0 Fixed Selects DMA3 source address direction 1 Increment 7 DADSL3 0 Fixed Selects DMA3 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Exten...

Page 251: ...quest cause Note 4 TENL4 0 Disables transfer DMA4 transfer enable 1 Enables transfer 5 TSZSL4 0 16 bits Selects DMA4 transfer size 1 8 bits 6 SADSL4 0 Fixed Selects DMA4 source address direction 1 Increment 7 DADSL4 0 Fixed Selects DMA4 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended ...

Page 252: ...01 All DMA0 transfers completed 10 Serial I O 2 reception completed 11 Extended request cause Note 4 TENL5 0 Disables transfer DMA5 transfer enable 1 Enables transfer 5 TSZSL5 0 16 bits Selects DMA5 transfer size 1 8 bits 6 SADSL5 0 Fixed Selects DMA5 source address direction 1 Increment 7 DADSL5 0 Fixed Selects DMA5 destination 1 Increment address direction W Only writing 0 is effective Writing 1...

Page 253: ...ransfer completed 4 TENL6 0 Disables transfer DMA6 transfer enable 1 Enables transfer 5 TSZSL6 0 16 bits Selects DMA6 transfer size 1 8 bits 6 SADSL6 0 Fixed Selects DMA6 source address direction 1 Increment 7 DADSL6 0 Fixed Selects DMA6 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended...

Page 254: ...ransfer completed 4 TENL7 0 Disables transfer DMA7 transfer enable 1 Enables transfer 5 TSZSL7 0 16 bits Selects DMA7 transfer size 1 8 bits 6 SADSL7 0 Fixed Selects DMA7 source address direction 1 Increment 7 DADSL7 0 Fixed Selects DMA7 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended...

Page 255: ...equest cause Note 4 TENL8 0 Disables transfer DMA8 transfer enable 1 Enables transfer 5 TSZSL8 0 16 bits Selects DMA8 transfer size 1 8 bits 6 SADSL8 0 Fixed Selects DMA8 source address direction 1 Increment 7 DADSL8 0 Fixed Selects DMA8 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended...

Page 256: ...ransfer completed 4 TENL9 0 Disables transfer DMA9 transfer enable 1 Enables transfer 5 TSZSL9 0 16 bits Selects DMA9 transfer size 1 8 bits 6 SADSL9 0 Fixed Selects DMA9 source address direction 1 Increment 7 DADSL9 0 Fixed Selects DMA9 destination 1 Increment address direction W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Note When Extended...

Page 257: ...ing Even when a new DMA transfer request occurs for a channel whose DMA transfer request flag is already set to 1 the next DMA transfer request is not accepted until after a transfer on the channel is completed 3 REQSLn cause of DMAn request select bits D2 D3 These bits select the cause of DMA request on each DMA channel Note If Extended request cause is selected for the cause of DMA request alway...

Page 258: ...ed cause 0010 TID1_udf ovf 0011 TIN16 input signal 0100 TIN0A input signal 0101 Serial I O 2 transmit buffer empty 0110 Serial I O 7 transmit buffer empty 0111 No selection 1xxx No selection Figure 9 2 3 Block Diagram of the DMA0 Request Extended Cause DMAC 9 2 DMAC Related Registers S DMA0 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN0A SIO2 TXD SIO7 TXD DM0REQ REQESEL0 DM0CNT ...

Page 259: ...nal 0100 TIN17 input signal 0101 TOM02_udf 0110 Serial I O 4 reception completed 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 4 Block Diagram of the DMA1 Request Extended Cause S DMA1 DM1REQ REQESEL1 DM1CNT REQSL1 S H 0080 0426 H 0080 0420 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN17 One DMA9 transfer completed TOM0...

Page 260: ...ignal 0100 TIN18 input signal 0101 TOM07_udf 0110 Serial I O 5 reception completed 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 5 Block Diagram of the DMA2 Request Extended Cause S DMA2 DM2REQ REQESEL2 DM2CNT REQSL2 S H 0080 0436 H 0080 0430 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN18 TOM07_udf SIO5_RXD PD_CMP0 PD_...

Page 261: ...t signal 0100 TIN19 input signal 0101 TOM03_udf 0110 A D1 conversion completed 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 6 Block Diagram of the DMA3 Request Extended Cause S DMA3 DM3REQ REQESEL3 DM3CNT REQSL3 S H 0080 0446 H 0080 0440 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN19 TOM03_udf A D1 conversion complete...

Page 262: ...nal 0100 TIN23 input signal 0101 TOM04_udf 0110 Serial I O 3 transmit buffer empty 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP 101x No selection 11xx No selection S DMA4 DM4REQ REQESEL4 DM4CNT REQSL4 S H 0080 0456 H 0080 0450 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN23 TOM04_udf SIO3 TXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA3 transf...

Page 263: ...input signal 0101 TOM16_udf 0110 Serial I O 4 transmit buffer empty 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 8 Block Diagram of the DMA5 Request Extended Cause S DMA5 DM5REQ REQESEL5 DM5CNT REQSL5 S H 0080 041E H 0080 0418 All DMA1 transfers completed TID0_udf ovf TID1_udf ovf TIN16 TIN1A TOM16_udf SIO4 TXD PD_CMP0 PD_CMP1 One DMA9 t...

Page 264: ...gnal 0100 TIN20 input signal 0101 TOM05_udf 0110 Serial I O 6 reception completed 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 9 Block Diagram of the DMA6 Request Extended Cause S DMA6 DM6REQ REQESEL6 DM6CNT REQSL6 S H 0080 042E H 0080 0428 All DMA1 transfer completed TID0_udf ovf TID1_udf ovf TIN16 TIN20 TOM05_udf SIO6 RXD PD_CMP0 PD_CM...

Page 265: ...al 0100 TIN1B input signal 0101 TOM06_udf 0110 Serial I O 5 transmit buffer empty 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 10 Block Diagram of the DMA7 Request Extended Cause S DMA7 DM7REQ REQESEL7 DM7CNT REQSL7 S H 0080 043E H 0080 0438 All DMA1 transfer completed TID0_udf ovf TID1_udf ovf TIN16 TIN1B TOM06_udf SIO5 TXD PD_CMP0 PD_C...

Page 266: ...al 0100 TIN21 input signal 0101 TOM17_udf 0110 Serial I O 6 transmit buffer empty 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 11 Block Diagram of the DMA8 Request Extended Cause S DMA8 DM8REQ REQESEL8 DM8CNT REQSL8 S H 0080 044E H 0080 0448 All DMA1 transfer completed TID0_udf ovf TID1_udf ovf TIN16 TIN21 TOM17_udf SIO6 TXD PD_CMP0 PD_C...

Page 267: ...nal 0100 TIN22 input signal 0101 TOM10_udf 0110 Serial I O 7 reception completed 0111 One DMA9 transfer completed 1000 PD_CMP0 1001 PD_CMP1 101x No selection 11xx No selection Figure 9 2 12 Block Diagram of the DMA9 Request Extended Cause S DMA9 DM9REQ REQESEL9 DM9CNT REQSL9 S H 0080 045E H 0080 0458 All DMA1 transfer completed TID0_udf ovf TID1_udf ovf TIN16 TIN22 TOM10_udf SIO7 RXD PD_CMP0 PD_CM...

Page 268: ...ese bits select a DMA transfer request extended source for each DMA channel Note The DMA transfer request extended source selected with the REQESELn DMAn request extended source select bits is effective only when Extended request source has been selected with the DMA Channel Control Register s cause of DMA request select REQSLn bits Figure 9 2 13 Block Diagram of the DMAn Request Extended Source D...

Page 269: ...egisters DM9SRI Address H 0080 0478 When reset indeterminate D Bit Name Function R W 0 15 DM0SRI DM9SRI A DMA transfer request is generated Generates DMA software request by writing any data to this register Note This register can be accessed in either bytes or halfwords The DMA Software Request Generation Register is used to generate a DMA transfer request in software A DMA transfer request is ge...

Page 270: ...ent register its read value is always the current value When a DMA transfer is finished at which the transfer count register underflows the source address remains unchanged or changes depending on the selected transfer address direction If Address fixed is selected the source address remains the same as the set value before the DMA transfer started if Address increment is selected the source addre...

Page 271: ...omprised of a current register its read value is always the current value When a DMA transfer is finished at which the transfer count register underflows the destination address remains unchanged or changes depending on the selected transfer address direction If Address fixed is selected the destination address remains the same as the set value before the DMA transfer started if Address increment ...

Page 272: ...32 channel ring buffer mode The DMA Transfer Count Register is used to set the number of times data is transferred in each channel However the value in this register is ignored during ring buffer mode The transfer count is the value set in the transfer count register 1 Because the DMA Transfer Count Register is comprised of a current register the value you get by reading this register is always th...

Page 273: ... Register helps to know the status of interrupt requests on DMA channels 0 4 If the DMAn interrupt request status bit n 0 4 is set to 1 it means that the channel has a DMA interrupt request generated DMITSTn DMAn interrupt request status bit n 0 4 The DMAn interrupt request status bit is set in hardware and cannot be set in software The DMAn interrupt request status bit is cleared by writing 0 in ...

Page 274: ... the status of interrupt requests on DMA channels 5 9 If the DMAn interrupt request status bit n 5 9 is set to 1 it means that the channel has a DMA interrupt request generated DMITSTn DMAn interrupt request status bit n 5 9 The DMAn interrupt request status bit is set in hardware and cannot be set in software The DMAn interrupt request status bit is cleared by writing 0 in software Note The DMAn ...

Page 275: ...pt request 12 DMITMK3 DMA3 interrupt request mask 13 DMITMK2 DMA2 interrupt request mask 14 DMITMK1 DMA1 interrupt request mask 15 DMITMK0 DMA0 interrupt request mask The DMA0 4 Interrupt Mask Register masks interrupt requests on DMA channels 0 4 DMITMKn DMAn interrupt request mask bits n 0 4 Setting the DMAn interrupt request mask bit to 1 masks a DMAn interrupt request However whenever an interr...

Page 276: ...TMK8 DMA8 interrupt request mask 13 DMITMK7 DMA7 interrupt request mask 14 DMITMK6 DMA6 interrupt request mask 15 DMITMK5 DMA5 interrupt request mask The DMA5 9 Interrupt Mask Register masks interrupt requests on DMA channels 5 9 DMITMKn DMAn interrupt request mask bits n 5 9 Setting the DMAn interrupt request mask bit to 1 masks a DMAn interrupt request However whenever an interrupt request occur...

Page 277: ...ITMK3 F F b12 b5 DMITST2 F F DMITMK2 F F b13 b6 DMITMK1 F F F F b14 b7 DMITST0 F F DMITMK0 F F b15 Level 5 source inputs DM04ITST H 0080 0400 DM04ITMK H 0080 0401 DMA4UDF DMA1UDF DMA0UDF DMA3UDF DMA2UDF DMITST1 Figure 9 2 14 Block Diagram of DMA Transfer Interrupt 0 DMAC 9 2 DMAC Related Registers ...

Page 278: ...ata bus b3 DMITST9 F F DMITMK9 F F b11 b4 DMITST8 F F DMITMK8 F F b12 b5 DMITST7 F F DMITMK7 F F b13 b6 DMITMK6 F F F F b14 b7 DMITST5 F F DMITMK5 F F b15 Level 5 source inputs DM59ITST H 0080 0408 DM59ITMK H 0080 0409 DMA9UDF DMA6UDF DMA5UDF DMA8UDF DMA7UDF DMITST6 DMAC 9 2 DMAC Related Registers ...

Page 279: ...are Request One DMA2 transfer completed Generation Register software start or one transfer on DMA2 is completed cascade mode 0 1 A D0 conversion completed When A D0 conversion is completed 1 0 Timer TOM00_udf When TOM00 timer underflows 1 1 Extended request cause Table 9 3 2 DMA Request Extended Causes on DMA0 and the Timing at Which Requests are Generated REQESEL0 DMA Request Extended Cause DMA R...

Page 280: ...MA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN17 input signal When the timer s TIN17 input signal is generated 0101 TOM02_udf When TOM02 timer underflows 0110 Serial I O 4 reception completed When serial I O 4 receptio...

Page 281: ...ll transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN18 input signal When the timer s TIN18 input signal is generated 0101 TOM07_udf When TOM07 timer underflows 0110 Serial I O 5 reception completed When seri...

Page 282: ...en all transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN19 input signal When the timer s TIN19 input signal is generated 0101 TOM03_udf When TOM03 timer underflows 0110 A D1 conversion completed When A D1 co...

Page 283: ...transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN23 input signal When the timer s TIN23 input signal is generated 0101 TOM04_udf When TOM04 timer underflows 0110 Serial I O 3 When serial I O 3 transmit buffe...

Page 284: ...Timing 0000 All DMA1 transfers completed When all transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN1A input signal When PD module s TIN1A input signal is generated 0101 TOM16_udf When TOM16 timer underflows ...

Page 285: ...all transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN20 input signal When the timer s TIN20 input signal is generated 0101 TOM05_udf When TOM05 timer underflows 0110 Serial I O 6 reception completed When ser...

Page 286: ...l transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN1B input signal When PD module s TIN1B input signal is generated 0101 TOM06_udf When TOM06 timer underflows 0110 Serial I O 5 When serial I O 5 transmit buf...

Page 287: ...l transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN21 input signal When the timer s TIN21 input signal is generated 0101 TOM17_udf When TOM17 timer underflows 0110 Serial I O 6 When serial I O 6 transmit buf...

Page 288: ...all transfers on DMA1 are completed cascade mode 0001 TID0_udf ovf When TID0 timer underflows or overflows 0010 TID1_udf ovf When TID1 timer underflows or overflows 0011 TIN16 input signal When the timer s TIN16 input signal is generated 0100 TIN22 input signal When the timer s TIN22 input signal is generated 0101 TOM10_udf When TOM10 timer underflows 0110 Serial I O 7 reception completed When ser...

Page 289: ...ed Set DMA0 Channel Control Register Set DMA0 4 Interrupt Request Status Register Set DMA0 Channel Control Register Set DMA0 Request Extended Cause Register Note Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register DMAC related register settings DMA transfer start DMA transfer complete Transfers disabled Clear the interrupt request status bit Set DMA0 4 In...

Page 290: ...red 300 ns when operating with the internal peripheral clock 20 MHz The above required time for DMA transfer to start after detecting the TIN input signal is calculated assuming that the external bus is unused and that HOLD and the LOCK instruction are not used To ensure that changes of state of the TIN input signal will be detected correctly make sure the TIN input signal has a pulse width of at ...

Page 291: ...ne DMA transfer 8 or 16 bits referred to as the transfer unit is selected for each channel with the TSZSL DMA transfer size select bit 9 3 7 Transfer Count The transfer count or the number of times a DMA transfer is performed is set for each channel by using the DMA Transfer Count Register DMA transfer can be performed up to 256 times The value of the transfer count register is decremented by one ...

Page 292: ... bus timing both are the same as in peripheral module access from the CPU 3 Transfer rate The maximum transfer rate is calculated using the equation below 4 Address count direction and address change The directions in which the source and destination addresses are counted address fixed or address increment are set for each channel by using the SADSL source address direction select bit and DADSL de...

Page 293: ...address transfers as well as even to even address and odd to odd address transfers are possible When the transfer unit 16 bits the LSB of the address register address register D15 bit is ignored and the two bytes of data transferred are always aligned with the 16 bit bus The diagram below shows the valid transfer byte positions Figure 9 3 3 Transfer Byte Positions DMAC 9 3 Functional Description o...

Page 294: ...ginning with the start address the bits are reset to B 000000 by the next increment action thus returning to the start address It is the source address if the source has been set to increment or the destination address if the destination has been set to increment that returns to the start address in this way If the source and destination addresses both have been set to increment both addresses ret...

Page 295: ...hed interrupt requests are generated Nor are DMA transfer finished interrupt requests are generated when ring buffer mode transfer is terminated by clearing the transfer enable bit 9 3 11 Register Status after End of DMA Transfer When a DMA transfer ends the Source Address and Destination Address Registers are in the following state 1 When address fixed The address remains fixed i e the same as th...

Page 296: ...r DMA related registers Transfers enabled Transfers disabled Can be accessed 5 Cannot be accessed Even for a few exceptional registers that can be accessed for write while transfers are enabled make sure the following conditions are met DMA Channel Control Register s transfer enable bit and transfer request flag For all other bits of the channel control register write the same data as they had bef...

Page 297: ...itten by a DMA transfer through channel 0 About the DMA Interrupt Request Status Register When writing to the DMA Interrupt Request Status Register to clear some bits be sure to write 1 to all bits other than those to be cleared Any bit of this register is unaffected by writing 1 the bit retains the value it had before writing About the stable operation of DMA transfers To ensure stable operation ...

Page 298: ...9 9 58 Rev 1 0 This is a blank page DMAC 9 4 Precautions on Using DMAC ...

Page 299: ...Output Timers 10 2 Common Timer Unit 10 3 TMS Input Related 16 bit Timers 10 4 TML Input Related 32 bit Timers 10 5 TID Input Related 16 bit Timers 10 6 TOM Output Related 16 bit Timers CHAPTER 10 CHAPTER 10 INPUT OUTPUT TIMERS ...

Page 300: ...L Input related 4 32 bit input measurement timer Timer 32 bit timers With new old captured data hold function Measure up counters Large TID Input related 2 Four modes are available that can be selected in software Timer 16 bit timers Fixed period mode Input up down counters Event count mode Derivation Multiply by 4 event count mode Up down event count mode TOM Output related 16 Four output modes a...

Page 301: ...7 TID1 outputs TID1 output interrupt 1 Table 10 1 3 DMA Transfer Request Generating Functions of Timers Signal Name DMA Transfer Request Source DMA Input Channel DRQ0 TID0 underflow overflow Channel 0 to channel 9 DRQ1 TID1 underflow overflow Channel 0 to channel 9 DRQ2 TOM0_0 underflow Channel 0 DRQ3 TOM0_1 underflow Channel 1 DRQ4 TOM0_2 underflow Channel 1 DRQ5 TOM0_3 underflow Channel 3 DRQ6 T...

Page 302: ...on Start Request Source A D Converter AD0TRG TIN16 input TOM0_6 underflow Can be input for A D0 conversion start trigger or TOM0 enable event AD1TRG TIN16 input TOM0_6 underflow Can be input for A D1 conversion start trigger or TOM1_6 underflow INPUT OUTPUT TIMERS 10 1 Outline of the Input Output Timers ...

Page 303: ... Converter IRQ28 IRQ28 PWMOFF0S TIN8S TIN9S TIN16 PWMOFF0 S S clk TID1 TIN10 TIN11 I 2 Internal Peripheral Clock IRQ17 clk TOM1_0 udf F F8 clk TOM1_1 udf F F9 TO8 TO9 clk TOM1_2 udf F F10 clk TOM1_3 udf F F11 TO10 TO11 clk TOM1_4 udf F F12 clk TOM1_5 udf F F13 TO12 TO13 clk TOM1_6 udf F F14 clk TOM1_7 udf F F15 TO14 TO15 IRQ20 IRQ20 IRQ20 IRQ20 IRQ22 IRQ20 IRQ20 IRQ20 CLK1 CLK2 PRS3 EN EN EN EN EN...

Page 304: ...lock IRQ19 TIN16S TIN17S TIN18S TIN19S PRS0 IRQ23 TIN16S1 IRQ22 TIN18S1 clk TML0 cap3 cap2 cap1 cap0 S S TIN20 TIN21 TIN22 TIN23 IRQ25 IRQ25 IRQ24 IRQ24 I 2 Internal Peripheral Clock TIN20S TIN21S TIN22S TIN23S PRS1 IRQ25 TIN20S1 IRQ24 TIN22S1 S DRQ17 DRQ18 DRQ19 DRQ20 DRQ13 DRQ14 DRQ15 DRQ16 To A D0 1 Converter or PD Module INPUT OUTPUT TIMERS 10 1 Outline of the Input Output Timers ...

Page 305: ...TOM16_udf TIN1A SIO2 RXD SIO4 TXD TOM05_udf TIN20 SIO1 TXD SIO6 RXD TOM06_udf TIN1B SIO2 TXD SIO5 TXD TOM17_udf TIN21 SIO3 RXD SIO6 TXD S TOM10_udf TIN22 SIO3 TXD SIO7 RXD udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 DMAIRQ0 DMAIRQ0 DMAIRQ0 DMAIRQ0 DMAIRQ1 DMAIRQ1 DMAIRQ1 DMAIRQ1 DMAIRQ1 S S S S S S S S S TID0_udf ovf TID1_udf...

Page 306: ...es the following blocks Prescaler unit Input processing control unit Output flip flop control unit Interrupt control unit 10 2 1 Register Map of the Common Timer Unit The next page shows a register map of the common timer unit INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 307: ...pt Mask Register 0 TINIMA0 TIN Interrupt Status Register 0 TINIST0 TIN Interrupt Mask Register 1 TINIMA1 TIN Interrupt Status Register 1 TINIST1 TIN Interrupt Mask Register 2 TINIMA2 TIN Interrupt Status Register 2 TINIST2 TIN Interrupt Mask Register 3 TINIMA3 TIN Interrupt Status Register 3 TINIST3 TIN Interrupt Mask Register 4 TINIMA4 TIN Interrupt Status Register 4 TINIST4 TIN Interrupt Mask Re...

Page 308: ...uation below Prescaler Register 0 PRS0 Address H 0080 08EB Prescaler Register 1 PRS1 Address H 0080 088B Prescaler Register 2 PRS2 Address H 0080 0CD0 Prescaler Register 3 PRS3 Address H 0080 0DD0 D8 9 10 11 12 13 14 D15 PRS0 PRS3 D0 1 2 3 4 5 6 D7 When reset H 00 D Bit Name Function R W 0 7 PRS2 3 Sets the prescaler s divide by value 8 15 PRS0 1 Prescaler Registers 0 and 1 start counting after re...

Page 309: ...to generate the signal to be fed to each timer for the enable measurement and count source signals There are following input processing control registers TIN Input Processing Control Register 0 TINCR0 TIN Input Processing Control Register 1 TINCR1 TIN Input Processing Control Register 2 TINCR2 TIN Input Processing Control Register 3 TINCR3 TIN Input Processing Control Register 4 TINCR4 TIN Input P...

Page 310: ...Processing Control Registers INPUT OUTPUT TIMERS 10 2 Common Timer Unit Rising edge Falling edge Both edges Low level High level TIN Internal edge signal TIN Internal edge signal TIN Internal edge signal TIN Internal level signal TIN Internal level signal ...

Page 311: ...igned 0 2 3 TIN21S 00 Ignores input Selects TIN21 input processing 01 Rising edge 10 Falling edge 11 Both edges 4 5 TIN20S1 00 Ignores input Selects TIN20 input processing 01 Rising edge for TML measurement 2 10 Falling edge 11 Both edges 6 7 TIN20S 00 Ignores input Selects TIN20 input processing 01 Rising edge 10 Falling edge 11 Both edges INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 312: ...igned 0 10 11 TIN23S 00 Ignores input Selects TIN23 input processing 01 Rising edge 10 Falling edge 11 Both edges 12 13 TIN22S1 00 Ignores input Selects TIN22 input processing 01 Rising edge for TML measurement 0 10 Falling edge 11 Both edges 14 15 TIN22S 00 Ignores input Selects TIN22 input processing 01 Rising edge 10 Falling edge 11 Both edges INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 313: ...igned 0 2 3 TIN17S 00 Ignores input Selects TIN17 input processing 01 Rising edge 10 Falling edge 11 Both edges 4 5 TIN16S1 00 Ignores input Selects TIN16 input processing 01 Rising edge for TML measurement 2 10 Falling edge 11 Both edges 6 7 TIN16S 00 Ignores input Selects TIN16 input processing 01 Rising edge 10 Falling edge 11 Both edges INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 314: ...igned 0 10 11 TIN19S 00 Ignores input Selects TIN19 input processing 01 Rising edge 10 Falling edge 11 Both edges 12 13 TIN18S1 00 Ignores input Selects TIN18 input processing 01 Rising edge for TML measurement 0 10 Falling edge 11 Both edges 14 15 TIN18S 00 Ignores input Selects TIN18 input processing 01 Rising edge 10 Falling edge 11 Both edges INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 315: ...FF0 by TIN16 Set the TIN16S2 write control TIN16S2P bit to 1 Subsequently after writing in 1 above set the TIN16S2 write control TIN16S2P bit to 0 and the TIN16 PWMOFF0 select TIN16S2 bits to 000 001 010 011 10X or 11X Note If a write cycle for any other area occurs between 1 and 2 the values written to the TIN16 PWMOFF0 select TIN16S2 bits have no effect TIN Input Processing Control Register 4 TI...

Page 316: ... TIN17S2 bits Set the TINCR4 Register TIN17S2P bit to 1 Note The data that is set here may be 000 001 010 011 10X or 11X Set the TINCR4 Register TIN17S2P bit to 0 Set data in TINCR4 Register TIN17S2 bits If a write cycle for any other area occurs within this interval no data are set in the TIN16S2 bits Set the TINCR4 Register TIN16S2P bit to 1 Note The data that is set here may be 000 001 010 011 ...

Page 317: ... Both edges 10 11 TIN10S 00 Ignores input Selects TIN10 input processing 01 Rising edge 10 Falling edge 11 Both edges 12 13 TIN9S 00 Ignores input Selects TIN9 input processing 01 Rising edge 10 Falling edge 11 Both edges 14 15 TIN8S 00 Ignores input Selects TIN8 input processing 01 Rising edge 10 Falling edge 11 Both edges D8 9 10 11 12 13 14 D15 TIN11S TIN10S TIN9S TIN8S INPUT OUTPUT TIMERS 10 2...

Page 318: ...h Timer Timer Mode Timing at which signal for output flip flop is generated TMS 16 bit measurement input No signal generating function TML 32 bit measurement input No signal generating function TID Fixed period count mode No signal generating function Event count mode No signal generating function Multiply by 4 event count mode No signal generating function Up down event count mode No signal gener...

Page 319: ...n WR Dn Output Control ON OFF TOn Port Operation Mode Register PnMOD F Fn Output Data FDn TOM_udf Note Dn denotes the data bus F F F F F F Figure 10 2 4 Configuration of the F F Output Circuit INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 320: ...ct F F Protect Register 1 FFP1 Address H 0080 0DD5 D8 9 10 11 12 13 14 D15 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 When reset H 00 D Bit Name Function R W 8 FP8 F F8 protect 0 Enables write to F F output bit 9 FP9 F F9 protect 1 Disables write to F F output bit 10 FP10 F F10 protect 11 FP11 F F11 protect 12 FP12 F F12 protect 13 FP13 F F13 protect 14 FP14 F F14 protect 15 FP15 F F15 protect INPUT OU...

Page 321: ...hen reset H 00 D Bit Name Function R W 8 FD8 F F8 output data 0 F F output data 0 9 FD9 F F9 output data 1 F F output data 1 10 FD10 F F10 output data 11 FD11 F F11 output data 12 FD12 F F12 output data 13 FD13 F F13 output data 14 FD14 F F14 output data 15 FD15 F F15 output data These registers set the output data in the respective output flip flops F Fs Although the F F output normally varies wi...

Page 322: ... Control Register 5 TINIR5 TIN Interrupt Control Register 8 TINIR8 TOM0 Interrupt Mask Register TOM0IMA TOM0 Interrupt Status Register TOM0IST TOM1 Interrupt Mask Register TOM1IMA TOM1 Interrupt Status Register TOM1IST For interrupts which have only one interrupt source for one interrupt vector table no interrupt control registers are provided within the timer and the interrupt status flags are au...

Page 323: ...ect the bit retains its status Because the status bit is unaffected by the interrupt mask bit it can also be used to check operation of the peripheral function During interrupt processing make sure that among the grouped interrupt flags only the flag which has had its associated interrupt serviced is cleared If any flag for which the interrupt has not been serviced is cleared unexecuted interrupt ...

Page 324: ...s Interrupt request b4 event occurs Only b6 is cleared b4 retains data b4 5 6 b7 1 1 0 1 Write to interrupt status Example for clearing interrupt status 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 Figure 10 2 6 Example for Clearing Interrupt Status INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 325: ...IRQ23 TIN16 TIN17 Timer input interrupt 1 3 IRQ24 TIN22 TIN23 Timer input interrupt 2 3 IRQ25 TIN20 TIN21 Timer input interrupt 3 3 IRQ27 TIN10 TIN11 Timer input interrupt 4 2 IRQ28 TIN8 TIN9 Timer input interrupt 5 2 IRQ30 PWMOFF0 PWMOFF1 PWM off input interrupt 2 Note 1 For details see Chapter 5 Interrupt Controller ICU Note 2 TMS0 TID0 and TID1 have only one interrupt source in the respective i...

Page 326: ...N20IS TIN20 interrupt status W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing INPUT OUTPUT TIMERS 10 2 Common Timer Unit TIN Interrupt Mask Register 0 TINIMA0 Address H 0080 0841 D8 9 10 11 12 13 14 D15 TIN21IM TIN20IM1 TIN20IM When reset H 00 D Bit Name Function R W 8 12 No functions assigned 0 13 TIN21IM TIN21 interrupt mask 0 Enables interrup...

Page 327: ...F TIN21IM F F b13 b6 TIN20IS1 F F TIN20IM1 F F b14 b7 TIN20IS F F TIN20IM F F b15 Level 3 source inputs TIN21edge TIN20edge TIN20edge TINIMA0 H 0080 0841 TINIST0 H 0080 0840 Figure 10 2 7 Block Diagram of Timer Input Interrupt 3 INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 328: ... 4 7 No functions assigned 0 W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing INPUT OUTPUT TIMERS 10 2 Common Timer Unit TIN Interrupt Mask Register 1 TINIMA1 Address H 0080 0843 When reset H 00 D Bit Name Function R W 8 No functions assigned 0 9 TIN23IM TIN23 interrupt mask 0 Enables interrupt request 10 TIN22IM1 1 Masks disables interrupt requ...

Page 329: ...F TIN21IM F F b9 b2 TIN22IS1 F F TIN22IM1 F F b10 b3 TIN22IS F F TIN22IM F F b11 Level 3 source inputs TIN23edge TIN22edge TIN22edge TINIMA1 H 0080 0843 TINIST1 H 0080 0842 Figure 10 2 8 Block Diagram of Timer Input Interrupt 2 INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 330: ... 0 is effective Writing 1 has no effect the bit retains the value it had before writing D0 1 2 3 4 5 6 D7 TIN17IS TIN16IS1 TIN16IS INPUT OUTPUT TIMERS 10 2 Common Timer Unit TIN Interrupt Mask Register 2 TINIMA2 Address H 0080 0845 When reset H 00 D Bit Name Function R W 8 12 No functions assigned 0 13 TIN17IM TIN17 interrupt mask 0 Enables interrupt request 14 TIN16IM1 1 Masks disables interrupt ...

Page 331: ...F TIN17IM F F b13 b6 TIN16IS1 F F TIN16IM1 F F b14 b7 TIN16IS F F TIN16IM F F b15 Level 3 source inputs TIN17edge TIN16edge TIN16edge TINIMA2 H 0080 0845 TINIST2 H 0080 0844 Figure 10 2 9 Block Diagram of Timer Input Interrupt 1 INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 332: ... 0 is effective Writing 1 has no effect the bit retains the value it had before writing D0 1 2 3 4 5 6 D7 TIN19IS TIN18IS1 TIN18IS INPUT OUTPUT TIMERS 10 2 Common Timer Unit TIN Interrupt Mask Register 3 TINIMA3 Address H 0080 0847 When reset H 00 D Bit Name Function R W 8 No functions assigned 0 9 TIN19IM TIN19 interrupt mask 0 Enables interrupt request 10 TIN18IM1 1 Masks disables interrupt requ...

Page 333: ...t 0 Timer input interrupt 0 IRQ22 Data bus b1 TIN19IS F F TIN19IM F F b9 b2 TIN18IS1 F F TIN18IM1 F F b10 b3 TIN18IS F F TIN18IM F F b11 Level 3 source inputs TIN19edge TIN18edge TIN18edge TINIMA3 H 0080 0847 TINIST3 H 0080 0846 INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 334: ... TIN9IS TIN8IS INPUT OUTPUT TIMERS 10 2 Common Timer Unit Figure 10 2 11 Block Diagram of Timer Input Interrupt 5 TIN Interrupt Mask Register 4 TINIMA4 Address H 0080 0849 Timer input interrupt 5 IRQ28 Data bus b6 TIN9IS F F TIN9IM F F b14 b7 TIN8IS F F TIN8IM F F b15 Level 2 source inputs TIN9edge TIN8edge TINIMA4 H 0080 0849 TINIST4 H 0080 0848 When reset H 00 D Bit Name Function R W 8 13 No fun...

Page 335: ...S TIN10IS Figure 10 2 12 Block Diagram of Timer Input Interrupt 4 INPUT OUTPUT TIMERS 10 2 Common Timer Unit Timer input interrupt 4 IRQ27 Data bus b2 TIN11IS F F TIN11IM F F b10 b3 TIN10IS F F TIN10IM F F b11 Level 2 source inputs TIN11edge TIN10edge TINIMA5 H 0080 084B TINIST5 H 0080 084A TIN Interrupt Mask Register 5 TINIMA5 Address H 0080 084B When reset H 00 D Bit Name Function R W 8 9 No fun...

Page 336: ...e writing When reset H 00 D Bit Name Function R W 8 13 No functions assigned 0 6 PWOFIM1 0 Enables interrupt request PMW output disable interrupt mask 1 1 Masks disables interrupt request 7 PWOFIM0 PMW output disable interrupt mask 0 D8 9 10 11 12 13 14 D15 PWOFIM1 PWOFIM0 TIN Interrupt Mask Register 8 TINIMA8 Address H 0080 0851 INPUT OUTPUT TIMERS 10 2 Common Timer Unit Figure 10 2 13 Block Diag...

Page 337: ...OM00IMA TOM0_0 interrupt mask INPUT OUTPUT TIMERS 10 2 Common Timer Unit When reset H 00 D Bit Name Function R W 8 TOM07IST TOM0_7 interrupt status 0 Interrupt not requested 9 TOM06IST TOM0_6 interrupt status 1 Interrupt requested 10 TOM05IST TOM0_5 interrupt status 11 TOM04IST TOM0_4 interrupt status 12 TOM03IST TOM0_3 interrupt status 13 TOM02IST TOM0_2 interrupt status 14 TOM01IST TOM0_1 interr...

Page 338: ...3IST F F TOM03IMA F F b4 TOM0IMA H 0080 0CD2 TOM0IST H 0080 0CD3 TOM07udf TOM06udf TOM05udf TOM04udf TOM03udf b13 TOM02IST F F TOM02IMA F F b5 b14 TOM01IST F F TOM01IMA F F b6 b15 TOM00IST F F F F b7 TOM02udf TOM01udf TOM00udf TOM00IMA TOM0 output interrupt IRQ21 Level Figure 10 2 14 Block Diagram of TOM0 Output Interrupt INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 339: ...terrupt status 0 Interrupt not requested 9 TOM16IST TOM1_6 interrupt status 1 Interrupt requested 10 TOM15IST TOM1_5 interrupt status 11 TOM14IST TOM1_4 interrupt status 12 TOM13IST TOM1_3 interrupt status 13 TOM12IST TOM1_2 interrupt status 14 TOM11IST TOM1_1 interrupt status 15 TOM10IST TOM1_0 interrupt status W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had...

Page 340: ...15IMA F F b2 b11 TOM14IST F F TOM14IMA F F b3 b12 TOM13IST F F TOM13IMA F F b4 TOM1IMA H 0080 0DD2 TOM1IST H 0080 0DD3 TOM17udf TOM16udf TOM15udf TOM14udf TOM13udf b13 TOM12IST F F TOM12IMA F F b5 b14 TOM11IST F F TOM11IMA F F b6 b15 TOM10IST F F F F b7 TOM12udf TOM11udf TOM10udf TOM10IMA TOM1 output interrupt IRQ20 Level INPUT OUTPUT TIMERS 10 2 Common Timer Unit ...

Page 341: ...it old measure register 4 pcs Timer start Started by writing to the enable bit in software Interrupt generation Can be generated by counter overflow 10 3 2 Functional Outline of the TMS In TMS when the timer is activated by writing to the enable bit in software the counter starts operating The counter is a 16 bit up counter When a measure signal is asserted by means of external input the value of ...

Page 342: ...2 internal peripheral clock Old Measure Register 3 Measure Register 2 Old Measure Register 2 Measure Register 1 Old Measure Register 1 Measure Register 0 Old Measure Register 0 TIN16S1 IRQ23 TIN18S1 IRQ22 To A D0 1 and PD module DRQ13 DRQ14 DRQ15 DRQ16 To TML0 Figure 10 3 1 Block Diagram of TMS Input Related 16 bit Timers INPUT OUTPUT TIMERS 10 3 TMS Input Related 16 bit Timers ...

Page 343: ...asure 1 Register TMS0MR1 H 0080 08EA Prescaler Register 0 PRS0 H 0080 08E8 TMS0 Control Register TMS0CR TMS0 Measure 3 Register TMS0MR3 TMS0Measure 0 Register TMS0MR0 H 0080 08F2 H 0080 08F4 H 0080 08F6 TMS0 Old Measure 2 Register TMS0OLDMR2 TMS0 Old Measure 1 Register TMS0OLDMR1 H 0080 08F8 TMS0 Old Measure 3 Register TMS0OLDMR3 TMS0 Old Measure 0 Register TMS0OLDMR0 Note The registers enclosed i...

Page 344: ...Input Related 16 bit Timers TMS0 Control Register TMS0CR Address H 0080 08EA When reset H 00 D Bit Name Function R W 0 TMS0SS0 0 External input TIN19 Selects TMS0 measure 0 source 1 External input TIN18 1 No functions assigned 0 2 TMS0SS2 0 External input TIN17 Selects TMS0 measure 2 source 1 External input TIN16 3 6 No functions assigned 0 7 TMSLCEN 0 Stops counting TMS TML count enable 1 Starts ...

Page 345: ...erminate D Bit Name Function R W 0 15 TMS0CT 16 bit counter value Note This register must always be accessed in halfwords The TMS counter is a 16 bit up counter which starts counting when the timer is activated by writing to the enable bit in software The counter can be read out on the fly INPUT OUTPUT TIMERS 10 3 TMS Input Related 16 bit Timers ...

Page 346: ...80 08E8 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TMS0MR3 0 When reset indeterminate D Bit Name Function R W 0 15 TMS0MR3 TMS0MR0 16 bit counter value Note 1 This register is a read only register Note 2 This register can be accessed in either bytes or halfwords The TMS measure registers are used to capture the content of the counter upon event input The TMS measure registers are a read only register...

Page 347: ... D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TMS0OLDMR3 0 When reset indeterminate D Bit Name Function R W 0 15 TMS0OLDMR3 TMS0OLDMR0 TMS0 measure register value Note 1 This register is a read only register Note 2 This register can be accessed in either bytes or halfwords The TMS old measure registers are used to capture the contents of the respective TMS measure registers upon event input The TMS old...

Page 348: ...ignal is entered from an external source A TMS interrupt can be generated when the counter overflows Figure 10 3 3 Typical Operation of TMS Measure Input INPUT OUTPUT TIMERS 10 3 TMS Input Related 16 bit Timers Count clock Counter H FFFF H 0000 Enabled by writing to the enable bit Measure event 1 occurs Indeterminate Enable bit Note Detailed timing information is not shown in this diagram Measure ...

Page 349: ...recautions to be observed when using TMS measure input If measure event input and write to the counter occur simultaneously in the same clock cycle the write value is set in the counter and also latched into the measure register INPUT OUTPUT TIMERS 10 3 TMS Input Related 16 bit Timers ...

Page 350: ... Specifications of the TML are listed below A block diagram of the TML is shown in the next page Table 10 4 1 Specifications of TML Input Related 32 bit Timers Item Specification Number of channels 4 channels Counter 32 bit up counter Measure register 32 bit measure register 4 pcs Timer start Started by writing to the enable bit in software INPUT OUTPUT TIMERS 10 4 TML Input Related 32 bit Timers ...

Page 351: ...he timer is activated by writing to the enable bit in software the counter starts operating The counter is a 32 bit up counter When a measure event signal is asserted by means of external input the content of each measure register 32 bit is latched into each old measure register 32 bit while the counter value is latched into each measure register 32 bit Counting is stopped immediately by writing t...

Page 352: ...ster High TML0MR2H TML0 Measure 1 Register Low TML0MR1L TML0 Measure 1 Register High TML0MR1H TML0 Measure 0 Register Low TML0MR0L TML0 Measure 0 Register High TML0MR0H Note The registers enclosed in the thick frames must always be accessed in words H 0080 08A0 H 0080 08A2 H 0080 08A4 H 0080 08A6 TML0 Old Measure 3 Register Low TML0OLDMR3L H 0080 08A8 H 0080 08AA H 0080 08AC H 0080 08AE TML0 Old M...

Page 353: ...lects TML0 measure 2 source 1 External input TIN20 11 14 No functions assigned 0 15 TML0CKS 0 Prescaler 1 PRS1 Selects TML0 clock source 1 Prescaler 0 PRS0 The TML0 Control Register is used to select TML0 input event and the count clock Note The counter can be written to normally only when the selected clock source is a 1 2 internal peripheral clock When using any other clock source the counter ca...

Page 354: ...t counter value 16 high order bits TML0CTL 32 bit counter value 16 low order bits Note This register must always be accessed words 32 bits beginning with the TML0CTH address The TML0 Counter is a 32 bit up counter which starts counting when the timer is activated by writing to the enable bit in software The TML0CTH and TML0CTL registers accommodate the 16 high order bits and the 16 low order bits ...

Page 355: ...0MR0L 16 low order bits When reset indeterminate D Bit Name Function R W 0 15 TML0MR3H 0H 32 bit measure register value 16 high order bits TML0MR3L 0L 32 bit measure register value 16 low order bits Note 1 These registers are a read only register Note 2 These registers must always be accessed words 32 bits beginning with each word boundary The TML0 Measure Registers are used to capture the content...

Page 356: ...ML0OLDMR0L 16 low order bits When reset indeterminate D Bit Name Function R W 0 15 TML0OLDMR3H 0H 32 bit old measure register value 16 high order bits TML0OLDMR3L 0L 32 bit old measure register value 16 low order bits Note 1 These registers are a read only register Note 2 These registers must always be accessed words 32 bits beginning with each word boundary The TML0 Old Measure Registers are used...

Page 357: ...Figure 10 4 3 Typical Operation of TML Measure Input INPUT OUTPUT TIMERS 10 4 TML Input Related 32 bit Timers Count clock Counter 32 bit H FFFF FFFF H 0000 0000 Enabled by writing to the enable bit Measure event 1 occurs Indeterminate Enable bit Note Detailed timing information is not shown in this diagram Measure 0 register Overflow occurs TIN22 interrupt Indeterminate TIN23 interrupt by overflow...

Page 358: ...r If the timer operates with any clock other than the 1 2 internal peripheral clock while clock bus 1 is selected for the count clock the captured value is one that leads the actual counter value by one clock period However during the 1 2 internal peripheral clock interval from the count clock this problem dose not occur and the counter value is captured at exact timing The diagram below shows the...

Page 359: ...ed below A block diagram of the TID is shown in the next page INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timers Table 10 5 1 Specifications of TID Input Related 16 bit Timers Item Specification Number of channels 2 channels Counter 16 bit up down counter Reload register 16 bit reload register Timer start Started by writing to the enable bit in software Mode selection Input mode Fixed period...

Page 360: ...nternal peripheral clock Edge control CLK1 CLK2 TOM1_0 7 Reload register clk DRQ1 To TOM0_0 7 EN and A D0TRG control circuits To TOM1_0 7 EN control circuit To TOM0_0 7 EN and A D0TRG control circuits To TOM1_0 7 EN control circuit TIN11S IRQ27 TIN10S IRQ27 TIN9S IRQ28 TIN8S IRQ28 Figure 10 5 1 Block Diagram of TID Input Related 16 bit Timers INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timer...

Page 361: ...15 H 0080 0C8E TID0 Counter TID0CT TID0 Control Prescaler 2 Enable Register TID0PRS2EN H 0080 0CD0 Note The registers enclosed in the thick frames must always be accessed in halfwords TID0 Reload Register TID0RL Prescaler Register 2 PRS2 H 0080 0D8C H 0080 0D8E TID1 Counter TID1CT TID1 Control Prescaler 3 Enable Register TID1PRS3EN H 0080 0DD0 TID1 Reload Register TID1RL Prescaler Register 3 PRS3 ...

Page 362: ...1 Starts counting 12 14 TOM0ENS X0X Disables event enable Selects TOM0_0 7 010 TID0 output enable source 011 TOM0_7 output 110 TID1 or TOM1_7 output 111 External input TIN18 15 PRS2EN 0 Stops counting Prescaler 2 enable 1 Starts counting Note Operation mode can only be set or changed when the counter is inactive The TID0 Control Prescaler 2 Enable Register is used to select TID0 operation mode fix...

Page 363: ... TOM1ENS X0X Disables event enable Selects TOM1_0 7 010 TID1 output enable source 011 TOM1_7 output 110 TID0 or TOM0_7 output 111 External input TIN19 15 PRS3EN 0 Stops counting Prescaler 3 enable 1 Starts counting Note Operation mode can only be set or changed when the counter is inactive The TID1 Control Prescaler 3 Enable Register is used to select TID1 operation mode fixed period count event c...

Page 364: ...T TID1CT When reset indeterminate D Bit Name Function R W 0 15 TID0CT TID1CT 16 bit counter value Note This register must always be accessed in halfwords The TID Counters are a 16 bit up down counter which starts counting synchronously with the count clock after the timer is enabled by writing to the enable bit in software INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timers ...

Page 365: ...register must always be accessed in halfwords The TID Reload Registers are used to reload the TID Counter Registers TID0CT and TID1CT with data The following shows the timing at which the content of the reload register is loaded into the corresponding counter When the counter underflows in fixed count mode When the counter is enabled in fixed count mode Simply because data is written to the reload...

Page 366: ...nter is loaded with the content of the reload register again from which it continues counting To stop the counter write to the enable bit in software to disable counting Also an interrupt can be generated each time the counter underflows The reload register set value 1 is the valid count value Figure 10 5 3 Typical Operation of TID in Fixed Period Count Mode INPUT OUTPUT TIMERS 10 5 TID Input Rela...

Page 367: ... to the enable bit in software the counter starts counting up from its set value synchronously with the generated clock An interrupt can be generated when the counter overflows To stop the counter write to the enable bit in software to disable counting or fix the externally sourced signal level high or low Figure 10 5 4 Typical Operation of the TID in Event Count Mode Basic Operation Figure 10 5 5...

Page 368: ...rnal clock When after setting the counter the timer is enabled by writing to the enable bit in software the counter starts counting from its set value synchronously with the generated clock For details on whether the counter counts up or down see Table 10 5 2 An interrupt can be generated when the counter overflows or underflows To stop the counter write to the enable bit in software to disable co...

Page 369: ...N9 Up count Down count 8001 8000 8001 7FFE Counter value Counter 7FFF 7FFE Timer enable Switched over Count disabled Count enabled Count disabled Count enabled Count disabled 7FFF Enabled Figure 10 5 6 Up Down Count Operation Switchover Timing Figure 10 5 7 Up Down Count Operation Count Enabled Disabled INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timers ...

Page 370: ...TIN9 Up count Down count FFFF 0000 0001 0000 FFFF FFFF 0000 0002 Counter value Counter 0001 FFFE FFFD FFFE FFFD Switched over Figure 10 5 8 Up Down Count Operation Interrupt Timing INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timers ...

Page 371: ...unter starts counting up or down from its set value synchronously with the generated clock The direction in which the counter counts is determined by the input level of the up down signal see Table 10 5 3 An interrupt can be generated when the counter overflows or underflows To stop the counter write to the enable bit in software to disable counting or fix the externally sourced clock signal level...

Page 372: ...r value FFFE TIN9 TIN11 FFFF 0000 0001 0002 0003 0002 0001 0000 FFFF FFFE FFFD FFFD TID interrupt by overflow or underflow Figure 10 5 10 Up Down Count Operation Interrupt Timing INPUT OUTPUT TIMERS 10 5 TID Input Related 16 bit Timers ...

Page 373: ...ls 16 channels two blocks 8 channels each for a total of 16 channels Counter 16 bit down counter 16 pcs Reload register 16 bit reload register 16 pcs Timer start TOM0_0 7 Started by writing to the enable bit in software or by an underflow overflow signal from TID0 timer an underflow signal from TOM0_7 an underflow overflow signal from TID1 timer or an underflow signal from TOM1_7 TOM1_0 7 Started ...

Page 374: ...MOFF0 S S clk TID1 TIN10 TIN11 1 2 internal peripheral clock IRQ17 clk TOM1_0 udf F F8 clk TOM1_1 udf F F9 TO8 TO9 clk TOM1_2 udf F F10 clk TOM1_3 udf F F11 TO10 TO11 clk TOM1_4 udf F F12 clk TOM1_5 udf F F13 TO12 TO13 clk TOM1_6 udf F F14 clk TOM1_7 udf F F15 TO14 TO15 IRQ20 IRQ20 IRQ20 IRQ20 IRQ22 IRQ20 IRQ20 IRQ20 CLK1 CLK2 PRS3 EN EN EN EN EN EN ovf udf EN EN DRQ1 DRQ10 DRQ11 DRQ12 PWM output ...

Page 375: ...imer write to the enable bit to disable counting and the timer immediately stops not synchronized to the PWM output period An interrupt and a DMA transfer request can be generated the second the fourth and other even numbered times the counter underflows after being enabled 2 Single shot output mode without correction function In single shot output mode the TOM generates a pulse in duration of the...

Page 376: ... is not inverted when the counter is enabled An interrupt and a DMA transfer request can be generated the second time the counter underflows after being enabled 4 Successive output mode without correction function In successive output mode the counter counts down from its set value and upon underflowing it is loaded with the value of the reload 0 register Therefore this operation is repeated each ...

Page 377: ...0RL1 TOM0_0 Counter TOM00CT TOM0_2 Counter TOM02CT TOM0_1 Reload 0 Register TOM01RL0 TOM0_1 Reload 1 Register TOM01RL1 TOM0_3 Counter TOM03CT TOM0_2 Reload 0 Register TOM02RL0 TOM0_2 Reload 1 Register TOM02RL1 TOM0_4 Counter TOM04CT TOM0_3 Reload 0 Register TOM03RL0 TOM0_3 Reload 1 Register TOM03RL1 TOM0_5 Counter TOM05CT TOM0_4 Reload 0 Register TOM04RL0 TOM0_4 Reload 1 Register TOM04RL1 TOM0_5 R...

Page 378: ...e Register is used to control TID0 Note 2 The registers enclosed in the thick frames must always be accessed in halfwords H 0080 0CDA H 0080 0CDC H 0080 0CDE TOM0 Control Register TOM0CR TOM0 Enable Protect Register TOM0PRO TOM0 Count Enable Register TOM0CEN Blank ares are reserved for future use TOM1_0 Counter TOM10CT H 0080 0DA0 H 0080 0DA2 H 0080 0DA4 H 0080 0DA6 TOM1_3 Counter TOM13CT H 0080 0...

Page 379: ...egister 1 FFP1 F F Data Register 1 FFD1 Note 1 The Prescaler Register 3 is shared with TOM1_0 7 and TID1 and the TID1 Control Prescaler 3 Enable Register is used to control TID1 Note 2 The registers enclosed in the thick frames must always be accessed in halfwords H 0080 0DDA H 0080 0DDC H 0080 0DDE TOM1 Control Register TOM1CR TOM1 Enable Protect Register TOM1PRO TOM1 Count Enable Register TOM1CE...

Page 380: ... 0 enables output 1 disables output bits in this register must be written correctly by following the procedure described below Write procedure Set the PWMOFF1S write control PWMOFF1P bit to 1 Subsequently after writing in above set the PWMOFF1S write control PWMOFF1P bit to 0 and the port P100 P105 output disable select PWMOFF1S bit to 0 or 1 Note If a write cycle for any other area occurs between...

Page 381: ...r must be written correctly by following the procedure described below Write procedure Set the PWMOFF0S write control PWMOFF0P bit to 1 Subsequently after writing in above set the PWMOFF0S write control PWMOFF0P bit to 0 and the port P110 P115 output disable select PWMOFF0S bit to 0 or 1 Note If a write cycle for any other area occurs between and the value set in the PWMOFF0S write control PWMOFF0...

Page 382: ...whether the three phase PWM signals turn on simultaneously Or because its behavior depends on the port output status it may also be used to check ports for duplicates 1 PLVSEL1 port P100 P105 output disable level select bit D6 This bit selects the port P100 P105 level high or low at which to disable PWM output To disable PWM output when the port level is low set this bit to 0 To disable PWM output...

Page 383: ...t to 1 validates the PWM output disable level selected with the PLVSEL1 bit so that PWM output is disabled when the port P100 P105 is at the level selected with the PLVSEL1 bit Setting this bit to 0 invalidates the PWM output disable level selected with the PLVSEL1 bit so that PWM output cannot be disabled according to the port P100 P105 level INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Tim...

Page 384: ... Or because its behavior depends on the port output status it may also be used to check ports for duplicates 1 PLVSEL0 port P110 P115 output disable level select bit D14 This bit selects the port P110 P115 level high or low at which to disable PWM output To disable PWM output when the port level is low set this bit to 0 To disable PWM output when the port level is high set this bit to 1 The follow...

Page 385: ...it to 1 validates the PWM output disable level selected with the PLVSEL1 bit so that PWM output is disabled when the port P110 P115 is at the level selected with the PLVSEL0 bit Setting this bit to 0 invalidates the PWM output disable level selected with the PLVSEL1 bit so that PWM output cannot be disabled according to the port P110 P115 level INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Ti...

Page 386: ...01M 10 Successive output mode Selects TOM0_1 operation mode 11 PWM output mode 4 5 TOM02M Selects TOM0_2 operation mode 6 7 TOM03M Selects TOM0_3 operation mode 8 9 TOM04M Selects TOM0_4 operation mode 10 11 TOM05M Selects TOM0_5 operation mode 12 13 TOM06M Selects TOM0_6 operation mode 14 15 TOM07M Selects TOM0_7 operation mode The TOM0 Control Registers are used to select operation modes of TOM0...

Page 387: ...ve output mode Selects TOM1_1 operation mode 11 PWM output mode 4 5 TOM12M Selects TOM1_2 operation mode 6 7 TOM13M Selects TOM1_3 operation mode 8 9 TOM14M Selects TOM1_4 operation mode 10 11 TOM15M Selects TOM1_5 operation mode 12 13 TOM16M Selects TOM1_6 operation mode 14 15 TOM17M Selects TOM1_7 operation mode The TOM1 Control Registers are used to select operation modes of TOM1_0 7 PWM output...

Page 388: ...s H 0080 0CC8 INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers When reset indeterminate D Bit Name Function R W 0 15 TOM00CT TOM07CT 16 bit counter value W Writing to the counter in PWM output or single shot PWM output mode has no effect Note These registers must always be accessed in halfwords The TOM0 Counters are a 16 bit counter which after the timer is enabled starts counting synchro...

Page 389: ...DC8 INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers When reset indeterminate D Bit Name Function R W 0 15 TOM10CT TOM17CT 16 bit counter value W Writing to the counter in PWM output or single shot PWM output mode has no effect Note These registers must always be accessed in halfwords The TOM1 Counters are a 16 bit counter which after the timer is enabled starts counting synchronously wit...

Page 390: ...ame Function R W 0 15 TOM00RL0 TOM07RL0 16 bit reload register value Note These registers must always be accessed in halfwords The TOM0 Reload 0 Registers are used to reload the TOM0 Counter Registers TOM00CT through TOM07CT with data The following shows the timing at which the content of the reload 0 register is loaded into the corresponding counter When the counter is enabled in single shot outp...

Page 391: ...W 0 15 TOM10RL0 TOM17RL0 16 bit reload register value Note These registers must always be accessed in halfwords The TOM1 Reload 0 Registers are used to reload the TOM1 Counter Registers TOM10CT through TOM17CT with data The following shows the timing at which the content of the reload 0 register is loaded into the corresponding counter When the counter is enabled in single shot output PWM output o...

Page 392: ...utput Related 16 bit Timers When reset indeterminate D Bit Name Function R W 0 15 TOM00RL1 TOM07RL1 16 bit reload register value Note These registers must always be accessed in halfwords The TOM0 Reload 1 Registers are used to reload the TOM0 Counter Registers TOM00CT through TOM07CT with data The following shows the timing at which the content of the reload 1 register is loaded into the correspon...

Page 393: ...6 bit Timers When reset indeterminate D Bit Name Function R W 0 15 TOM10RL1 TOM17RL1 16 bit reload register value Note These registers must always be accessed in halfwords The TOM1 Reload 1 Registers are used to reload the TOM1 Counter Registers TOM10CT through TOM17CT with data The following shows the timing at which the content of the reload 1 register is loaded into the corresponding counter Wh...

Page 394: ... enable protect 1 Disables rewriting 9 TOM01PRO TOM0_1 enable protect 10 TOM02PRO TOM0_2 enable protect 11 TOM03PRO TOM0_3 enable protect 12 TOM04PRO TOM0_4 enable protect 13 TOM05PRO TOM0_5 enable protect 14 TOM06PRO TOM0_6 enable protect 15 TOM07PRO TOM0_7 enable protect The TOM0 Enable Protect Register is used to control rewriting of the TOM0 count enable bit described in the next page by disab...

Page 395: ... TOM1_3 enable protect 12 TOM14PRO TOM1_4 enable protect 13 TOM15PRO TOM1_5 enable protect 14 TOM16PRO TOM1_6 enable protect 15 TOM17PRO TOM1_7 enable protect The TOM1 Enable Protect Register is used to control rewriting of the TOM1 count enable bit described in the next page by disabling or enabling the rewrite D8 9 10 11 12 13 14 D15 TOM10PRO TOM11PRO TOM12PRO TOM13PRO TOM14PRO TOM15PRO TOM16PRO...

Page 396: ...04CEN TOM05CEN TOM06CEN TOM07CEN The TOM0 Count Enable Register controls operation of the TOM0 counters To enable any counter in software enable the corresponding TOM0 Enable Protect Register for write and set the count enable bit to 1 To stop the counter enable the TOM0 Enable Protect Register for write and set the count enable bit to 0 In single shot output and single shot PWM output modes the c...

Page 397: ... any counter in software enable the corresponding TOM1 Enable Protect Register for write and set the count enable bit to 1 To stop the counter enable the TOM1 Enable Protect Register for write and set the count enable bit to 0 In single shot output and single shot PWM output modes the count enable bit is automatically reset to 0 when the counter stops after reaching the minimum count Therefore the...

Page 398: ...1 Starts counting 12 14 TOM0ENS X0X Disables event enable Selects TOM0_0 7 X10 TID0 output enable source 011 TOM0_7 output 110 TID1 or TOM1_7 output 111 External input TIN18 15 PRS2EN 0 Stops counting Prescaler 2 enable 1 Starts counting Note Operation mode can only be set or changed when the counter is inactive The TID0 Control Prescaler 2 Enable Register is used to select TID0 operation mode fix...

Page 399: ...10 TID1 output enable source 011 TOM1_7 output 110 TID0 or TOM0_7 output 111 External input TIN19 15 PRS3EN 0 Stops counting Prescaler 3 enable 1 Starts counting Note Operation mode can only be set or changed when the counter is inactive The TID1 Control Prescaler 3 Enable Register is used to select TID1 operation mode fixed period count event count multiply by 4 event count or up down event count...

Page 400: ...TOM1_7 output is selected Figure 10 6 7 Configuration of the TOM0 Enable Circuit Figure 10 6 8 Configuration of the TOM1 Enable Circuit INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers WR Dn TOM1m enable protect TOM1mPRO WR EN ON Selects TOM1 enable source TOM1ENS TOM1m enable TOM1mCEN TOM1m enable control F F F F Disables event enable TID1 output TOM1_7 output External input TIN19 Select...

Page 401: ...s alternately reloaded by the reload 0 and the reload 1 registers each time it underflows The reload 0 register set value 1 and the reload 1 register set value 1 respectively are the valid count values To stop the timer write to the enable bit to disable counting and the timer immediately stops not synchronized to the PWM output period The F F output waveform in PWM output mode is inverted F F out...

Page 402: ...0 register H A000 Underflow second time Counts down from reload 1 register set value H C000 1 Data inverted by underflow Data inverted by enable H A000 1 Data inverted by underflow Reload 1 register H C000 Counts down from reload 0 register set value Counts down from reload 0 register set value H A000 PWM output period H C000 H A000 Figure 10 6 9 Typical Operation of TOM in PWM Output Mode INPUT O...

Page 403: ...iod Normally this can be accomplished at a time by accessing the 32 bit address space wordwise beginning with the reload 1 register address The reload 1 and then the reload 0 registers are automatically written to in succession If the reload registers are updated in reverse by updating the reload 0 and then the reload 1 registers only the reload 0 register is updated The values obtained by reading...

Page 404: ...eriod latched Reload 1 buffer H 2000 H 9000 Note Detailed timing information is not shown in this diagram Count clock Reload 0 register Reload 1 register H 0001 H FFFF H 1000 H 0FFF H 2000 H 8000 H 9000 Counter Interrupt by underflow b When updating of the reload registers takes effect in the next period reflected in the period after next Timing at which reload 1 and reload 0 registers are updated...

Page 405: ...transfer request can be generated when the counter underflows The count value is the reload 0 register set value 1 2 Precautions on using TOM in single shot output mode The following describes precautions to be observed when using the TOM in single shot output mode If the counter stops upon underflowing while it is enabled by external input in the same clock cycle the former has priority so that t...

Page 406: ... bit Counts down from the reload 0 register set value Note Detailed timing information is not shown in this diagram Reload 0 register H A000 H A000 Data inverted by enable Data inverted by underflow Counter Reload 1 register Figure 10 6 12 Typical Operation of TOM in Single shot Output Mode without Correction Function INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers ...

Page 407: ...egister When the counter underflows second time it stops counting The reload 0 register set value 1 and the reload 1 register set value 1 respectively are the valid count values To stop the timer in software write to the enable bit to disable counting and the timer immediately stops not synchronized to the PWM output period The F F output waveform in single shot PWM output mode is inverted F F out...

Page 408: ...diagram Reload 0 register H A000 H A000 Underflow second time H F000 Counts down from reload 1 register set value H EFFF Data inverted by underflow Data inverted by underflow Counter Reload 1 register H F000 Counts down from reload 0 register set value PWM output period Figure 10 6 13 Typical Operation of TOM in Single shot PWM Output Mode without Correction Function INPUT OUTPUT TIMERS 10 6 TOM O...

Page 409: ... changes level from low to high or vice versa when the counter starts counting and when it underflows thereby successively generating a pulse waveform until the count stops An interrupt and a DMA transfer request can be generated each time the counter underflows The counter set value 1 and the reload 0 register set value 1 are the valid count values 2 Precautions on using TOM in successive output ...

Page 410: ...s not shown in this diagram Reload 0 register H E000 H A000 Underflow second time H E000 Counts down from the reload 0 register set value H DFFF Data inverted by underflow Data inverted by enable Counts down from the reload 0 register set value H DFFF Data inverted by underflow Unused Reload 1 register Figure 10 6 14 Typical Operation of TOM in Successive Output Mode without Correction Function IN...

Page 411: ...ess F F PWMOFF0 WR RD TMS0 cap3 D15 P110 internal P111 internal P112 internal P113 internal P114 internal P115 internal P110 TO0 P111 TO1 P112 TO2 P113 TO3 P114 TO4 P115 TO5 P110 internal P111 internal P112 internal P113 internal P114 internal P115 internal TIN17S2 IRQ30 P131 TIN17 PWMOFF1 TIN17S IRQ23 SET WR F F F F F F PLVSEL1 PLVDIS1 PWMOFF1 WR F F D6 Address F F PWMOFF1 WR RD TMS0 cap2 D7 P100...

Page 412: ...4 Register D4 bit to 1 Subsequently after writing in above set the D4 bit to 0 and the D5 D7 bits to 000 001 010 011 10X or 11X Note If a write cycle for any other area occurs between and the value set in the D5 D7 bits has no effect 2 Disabling PWM outputs with the pin level on ports P100 P105 or P110 P115 The pin level on ports P100 P105 high or low may be used to disable PWM outputs of TOM1_0 T...

Page 413: ...00 P105 To disable PWM outputs using the Port P110 P115 Output Disable Register PWMOFF0 or Port P100 P105 Output Disable Register PWMOFF1 the respective registers must be set up following the procedure described below To disable PWM outputs using the Port P110 P115 Output Disable Register PWMOFF0 Set the PWMOFF0 Register D14 bit to 1 Subsequently after writing in above set the D14 to 0 and the D15...

Page 414: ...ite timing The H and L transistor short circuiting prevention time can be accomplished by changing the TOM0 setup time in software Up to 8 phase motors can be controlled by a combined use of TID and TOM Figure 10 6 16 System Configuration Diagram Figure 10 6 17 Interconnecting Timers for Three phase Motor Control INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers Circuit board M32172 Power ...

Page 415: ...KHz TOM start TO0 U TO1 U TO2 V TO3 V TO4 W TO5 W Delay Single shot Delay Single shot Short circuiting prevention time Figure 10 6 18 Conceptual Diagram of Motor Control INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers ...

Page 416: ...10 10 118 Rev 1 0 This is a blank page INPUT OUTPUT TIMERS 10 6 TOM Output Related 16 bit Timers ...

Page 417: ...1 1 Outline of the A D Converters 11 2 A D Converter Related Registers 11 3 Functional Description of the A D Converters 11 4 Precautions on Using the A D Converters CHAPTER 11 CHAPTER 11 A D CONVERTERS ...

Page 418: ...age on one channel is A D converted once or comparated note Scan mode Analog input voltages on multiple channels are sequentially A D converted 3 Types of scan modes Single shot scan mode Scan operation is performed only one cycle Continuous scan mode Scan operation is performed repeatedly until halted 4 Special operation modes Forcibly execute single mode during scan mode operation Single mode co...

Page 419: ...ode A D conversion mode comparator mode Operation mode Single mode scan mode Scan mode Single shot scan mode continuous scan mode Conversion start trigger Started in software By setting A D conversion start bit to 1 Started in hardware A D0 Converter Input on external pin TIN16 Underflow of TOM0_6 timer Enable event on TOM0_0 7 Note 2 Completion of A D1 conversion A D1 Converter Input on external ...

Page 420: ...tor Low speed mode Normal 47 1 f BCLK mode Double speed 29 1 f BCLK High speed mode Normal 23 1 f BCLK Double speed 17 1 f BCLK Interrupt request generation When A D conversion comparate single shot scan or one cycle of function continuous scan mode is finished DMA transfer request generation When A D conversion comparate single shot scan or one cycle of function continuous scan mode is finished N...

Page 421: ...est Successive Approximation Method A D Converter Unit Internal data bus A D0 Scan Mode Register AD0SCM0 1 AD0SIM0 1 AVCC0 Read out in 10 bits Read out in 8 bits Shifter 10 bit A D0 Data Register 2 10 bit A D0 Data Register 3 10 bit A D0 Data Register 4 10 bit A D0 Data Register 5 10 bit A D0 Data Register 6 10 bit A D0 Data Register 7 10 bit A D0 Data Register 8 10 bit A D0 Data Register 9 10 bit...

Page 422: ...sive Approximation Method A D Converter Unit Internal data bus A D1 Scan Mode Register AD1SCM0 1 AD1SIM0 1 AVCC0 Read out in 10 bits Read out in 8 bits Shifter 10 bit A D1 Data Register 2 10 bit A D1 Data Register 3 10 bit A D1 Data Register 4 10 bit A D1 Data Register 5 10 bit A D1 Data Register 6 10 bit A D1 Data Register 7 10 bit A D1 Data Register 8 10 bit A D1 Data Register 9 10 bit A D1 Data...

Page 423: ...d during single mode or one cycle of scan loop is finished during scan mode Note If the analog input pins AD0IN8 AD0IN15 or AD1IN6 AD1IN15 are selected with Single Mode Register 1 always be sure to set the AD Digital Input Control Register AD0CHCON or AD1CHCON 2 Comparator mode In comparator mode the A D converter comparates the analog input voltage on a specified channel with the Successive Appro...

Page 424: ...Conversion starts Note i 0 1 n 0 15 Note A D0 conversion start Software trigger By setting the A D0 conversion start bit to 1 Hardware trigger By TOM0_6 underflow input signal on external pin TIN16 TOM0_0 7 enable event or completion of A D1 conversion A D1 conversion start Software trigger By setting the A D1 conversion start bit to 1 Hardware trigger By TOM0_6 underflow input signal on external ...

Page 425: ...p and this group of channels are sequentially scanned beginning with the channel ADiIN0 An A D conversion interrupt request or DMA transfer request can be generated when one cycle of scan operation is finished Figure 11 1 5 A D Convert Operation in Scan Mode A D CONVERTERS 11 1 Outline of the A D Converters A D conversion interrupt request or DMA transfer request ADiIN0 Finished here during single...

Page 426: ...er 0 Repeated until forcibly terminated B 0010 2 ADiIN0 ADiIN0 10 bit A Di Data Register 0 ADiIN2 ADiIN1 ADiIN1 10 bit A Di Data Register 1 ADiIN2 ADiIN2 10 bit A Di Data Register 2 Finishes ADiIN0 10 bit A Di Data Register 0 Repeated until forcibly terminated B 0011 3 ADiIN0 ADiIN0 10 bit A Di Data Register 0 ADiIN3 ADiIN1 ADiIN1 10 bit A Di Data Register 1 ADiIN2 ADiIN2 10 bit A Di Data Register...

Page 427: ...perating in scan mode To start single mode conversion in hardware during scan mode operation select hardware trigger using Single Mode Register 0 s A D conversion start trigger select bit and enter the hardware trigger selected with said register TOM0_6 underflow input on external pin TIN16 TOM0_0 7 enable event or completion of A D1 conversion for the A D0 Converter TOM0_6 underflow input on exte...

Page 428: ...xternal pin TIN16 TOM0_0 7 enable event or completion of A D1 conversion for the A D0 Converter TOM0_6 underflow input on external pin TIN16 TOM1_6 underflow or completion of A D0 conversion for the A D1 Converter is entered after selecting it with the A D conversion start trigger select bits of both Single Mode Register 0 and Scan Mode Register 0 single mode conversion is performed first and then...

Page 429: ...dware trigger signal TOM0_6 underflow input on external pin TIN16 TOM0_0 7 enable event or completion of A D1 conversion for the A D0 Converter TOM0_6 underflow input on external pin TIN16 TOM1_6 underflow or completion of A D0 conversion for the A D1 Converter while scan operation is under way Figure 11 1 8 Restarting Conversion during Single Mode Operation Figure 11 1 9 Restarting Conversion dur...

Page 430: ... requests to generate use Single Mode Register 0 and Scan Mode Register 0 Figure 11 1 10 Selecting between A D Conversion Interrupt and DMA Transfer Requests A D CONVERTERS 11 1 Outline of the A D Converters Scan mode when one cycle of scan is finished Single mode when A D conversion or comparate is finished A D conversion interrupt request to the Interrupt Controller DMA transfer request to the D...

Page 431: ... AD0DT2 10 bit A D0 Data Register3 AD0DT3 10 bit A D0 Data Register4 AD0DT4 10 bit A D0 Data Register5 AD0DT5 10 bit A D0 Data Register6 AD0DT6 10 bit A D0 Data Register7 AD0DT7 10 bit A D0 Data Register8 AD0DT8 H 0080 00A0 H 0080 00A2 H 0080 00A4 H 0080 00A6 H 0080 00A8 H 0080 00AA H 0080 00AC H 0080 00AE 10 bit A D0 Data Register9 AD0DT9 10 bit A D0 Data Register10 AD0DT10 10 bit A D0 Data Regis...

Page 432: ...Register4 AD08DT4 8 bit A D0 Data Register5 AD08DT5 8 bit A D0 Data Register6 AD08DT6 8 bit A D0 Data Register9 AD08DT9 8 bit A D0 Data Register10 AD08DT10 8 bit A D0 Data Register11 AD08DT11 8 bit A D0 Data Register12 AD08DT12 8 bit A D0 Data Register13 AD08DT13 8 bit A D0 Data Register14 AD08DT14 8 bit A D0 Data Register15 AD08DT15 8 bit A D0 Data Register7 AD08DT7 8 bit A D0 Data Register8 AD08...

Page 433: ... A D1 Data Register7 AD1DT7 10 bit A D1 Data Register8 AD1DT8 H 0080 0AA0 H 0080 0AA2 H 0080 0AA4 H 0080 0AA6 H 0080 0AA8 H 0080 0AAA H 0080 0AAC H 0080 0AAE 10 bit A D1 Data Register9 AD1DT9 10 bit A D1 Data Register10 AD1DT10 10 bit A D1 Data Register11 AD1DT11 10 bit A D1 Data Register12 AD1DT12 10 bit A D1 Data Register13 AD1DT13 10 bit A D1 Data Register14 AD1DT14 10 bit A D1 Data Register15 ...

Page 434: ...Register4 AD18DT4 8 bit A D1 Data Register5 AD18DT5 8 bit A D1 Data Register6 AD18DT6 8 bit A D1 Data Register9 AD18DT9 8 bit A D1 Data Register10 AD18DT10 8 bit A D1 Data Register11 AD18DT11 8 bit A D1 Data Register12 AD18DT12 8 bit A D1 Data Register13 AD18DT13 8 bit A D1 Data Register14 AD18DT14 8 bit A D1 Data Register15 AD18DT15 8 bit A D1 Data Register7 AD18DT7 8 bit A D1 Data Register8 AD18...

Page 435: ... interrupt request Select interrupt request DMA request 1 DMA transfer request 5 AD0SCMP 0 A D0 conversion comparate in progress A D0 conversion comparate complete 1 A D0 conversion comparate completed 6 AD0SSTP 0 No operation 0 Stop A D0 conversion 1 Stops A D0 conversion 7 AD0SSTT 0 No operation 0 Start A D0 conversion 1 Starts A D0 conversion Note 1 To select a hardware trigger use the D0 bit A...

Page 436: ...1 interrupt request Interrupt request 1 DMA transfer request 5 AD1SCMP 0 A D1 conversion comparate in progress A D1 conversion comparate complete 1 A D1 conversion comparate completed 6 AD1SSTP 0 No operation 0 Stop A D1 conversion 1 Stops A D1 conversion 7 AD1SSTT 0 No operation 0 Start A D1 conversion 1 Starts A D1 conversion Note To select a hardware trigger use the D0 bit A D1 hardware trigger...

Page 437: ...converter operation in single mode A D conversion or comparate When using neither interrupt nor DMA transfer select A Dn conversion interrupt request and mask it with the ICU s A Dn Converter Interrupt Control Register or select DMA transfer and disable the DMA transfer to be started at completion of A Dn conversion with the DMAn Channel Control Register 4 ADnSCMP A Dn conversion comparate complet...

Page 438: ...Dn conversion start trigger select bit If the A Dn conversion start and A Dn conversion stop bits are set to 1 simultaneously the latter has priority so that the A Dn conversion is stopped When this bit is set to 1 during single mode conversion special operation mode Restart conversion is assumed so that conversion in single mode restarts When this bit is set to 1 during A D conversion in scan mod...

Page 439: ... AD0IN8 1001 Selects AD0IN9 1010 Selects AD0IN10 1011 Selects AD0IN11 1100 Selects AD0IN12 1101 Selects AD0IN13 1110 Selects AD0IN14 1111 Selects AD0IN15 W Writing 0 only is effective Writing 1 to these bits is unaccepted the device operation cannot be guaranteed Note 1 Because the A D0 conversion speed is determined by a combined use of this AD0SSPD bit and the A D0 Conversion Speed Control Regis...

Page 440: ... Selects AD1IN12 1101 Selects AD1IN13 1110 Selects AD1IN14 1111 Selects AD1IN15 W Writing 0 only is effective Writing 1 to these bits is unaccepted the device operation cannot be guaranteed Note 1 Because the A D1 conversion speed during single mode is determined by a combined use of this AD1SSPD bit and the A D1 Conversion Speed Control Register AD1CVSD bit make sure the AD1SSPD and AD1CVSD bits ...

Page 441: ...setting this bit to 1 selects double speed Note Because the A Dn conversion speed during single mode is determined by a combined use of this ADnSSPD bit and the A Dn Conversion Speed Control Register ADnCVSD bit make sure the ADnSSPD and ADnCVSD bits both are set 3 ANnSEL analog input pin select bits D12 D15 These bits select an analog input pin when the A Dn converter is operating in single mode ...

Page 442: ...trigger Select A D0 conversion start trigger 1 Hardware trigger 4 AD0CREQ 0 A D0 interrupt request Select interrupt request DMA request 1 DMA transfer request 5 AD0CCMP 0 A D0 conversion in progress A D0 conversion complete 1 A D0 conversion completed 6 AD0CSTP 0 No operation 0 Stop A D0 conversion 1 Stops A D0 conversion 7 AD0CSTT 0 No operation 0 Start A D0 conversion 1 Starts A D0 conversion No...

Page 443: ...r Select A D1 conversion start trigger 1 Hardware trigger 4 AD1CREQ 0 A D1 interrupt request interrupt request 1 DMA transfer request 5 AD1CCMP 0 A D1 conversion in progress A D1 conversion complete 1 A D1 conversion completed 6 AD1CSTP 0 No operation 0 Stop A D1 conversion 1 Stops A D1 conversion 7 AD1CSTT 0 No operation 0 Start A D1 conversion 1 Starts A D1 conversion Note To select a hardware t...

Page 444: ... operation in single shot scan mode finishes A D conversion is performed from the first channel again This is repeated until stopped by setting the ADnCSTP A Dn conversion stop bit to 1 3 ADnCSEL A Dn conversion start trigger select bit D3 This bit selects whether to apply the A D conversion start trigger in software or in hardware during scan mode of the A Dn converter When software trigger is se...

Page 445: ... Dn conversion start and A Dn conversion stop bits are set to 1 simultaneously the latter has priority so that the A Dn conversion is stopped 7 ADnCSTT A Dn conversion start bit D7 This bit is used to start scan mode of the A Dn converter in software Only when software trigger has been selected with the ADnCSEL A Dn conversion start trigger select bit A D conversion can be started by setting this ...

Page 446: ...N5 being converted 0110 AD0IN6 being converted 0111 AD0IN7 being converted 1000 AD0IN8 being converted 1001 AD0IN9 being converted 1010 AD0IN10 being converted 1011 AD0IN11 being converted 1100 AD0IN12 being converted 1101 AD0IN13 being converted 1110 AD0IN14 being converted 1111 AD0IN15 being converted Note 1 Because the A D0 conversion speed during scan mode is determined by a combined use of th...

Page 447: ...N7 being converted 1000 AD1IN8 being converted 1001 AD1IN9 being converted 1010 AD1IN10 being converted 1011 AD1IN11 being converted 1100 AD1IN12 being converted 1101 AD1IN13 being converted 1110 AD1IN14 being converted 1111 AD1IN15 being converted Note 1 Because the A D1 conversion speed during scan mode is determined by a combined use of this AD1CSPD bit and the A D1 Conversion Speed Control Reg...

Page 448: ...e operation with the A Dn converter For details about the scan loop configuration by specified channel numbers see Table 11 1 2 When the ANnSCAN A Dn scan loop select bits are read out during scan operation they serve as status bits indicating the channel being converted When read during single mode these bits always show the value B 0000 If these bits are read when the A D conversion is stopped b...

Page 449: ...re to set the AD0CVSD and AD0SSPD bits during single mode or the AD0CVSD and AD0CSPD bits during scan mode A D1 Conversion Speed Control Register AD1CVSCR Address H 0080 0A87 When reset H 00 D Bit Name Function R W 8 14 No functions assigned 0 15 AD1CVSD Note 0 Low speed mode Control A D1 conversion seed 1 High speed mode Note The A D1 conversion speed is determined by a combined use of this AD1CV...

Page 450: ... mode Note The A Dn conversion speed is determined by a combined use of this ADnCVSD bit and the A Dn Single Mode Register 1 ADnSSPD bit when operating in single mode or a combined use of this ADnCVSD bit and the A Dn Scan Mode Register 1 ADnCSPD bit when operating in scan mode Be sure to set the ADnCVSD and ADnSSPD bits during single mode or the ADnCVSD and ADnCSPD bits during scan mode A D CONVE...

Page 451: ...ster AD1CHCON Address H 0080 0A8E D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 AD1C H12CN AD1C H11CN AD1C H9CN AD1C H8CN AD1C H15CN AD1C H14CN AD1C H13CN AD1C H10CN AD1C H6CN AD1C H7CN D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 AD0C H12CN AD0C H11CN AD0C H9CN AD0C H8CN AD0C H15CN AD0C H14CN AD0C H13CN AD0C H10CN When reset H 00 D Bit Name Function R W 0 5 No functions assigned Note 2 6 15 AD1CH8CN AD1CH15...

Page 452: ...s are compared bitwise sequentially beginning with the most significant bit and the result is set in the A D0 Successive Approximation Register AD0SAR s each corresponding bit D6 D15 When the A D conversion finishes the value of this register is transferred to the 10 bit A D0 Data Register AD0DTn corresponding to the converted channel When this register is read in the middle of A D conversion it s...

Page 453: ... bit and the result is set in the A D1 Successive Approximation Register AD1SAR s each corresponding bit D6 D15 When the A D conversion finishes the value of this register is transferred to the 10 bit A D1 Data Register AD1DTn corresponding to the converted channel When this register is read in the middle of A D conversion it shows an intermediate result of conversion In comparator mode this regis...

Page 454: ... input voltage comparison voltage Note 1 This register must always be accessed in halfwords Note 2 During comparator mode each bit of this register corresponds to channel 0 through channel 15 When comparator mode is selected with A D0 Single Mode Register 1 AD0SMSL A D0 conversion mode select bit the selected analog input value and the value written to the A D0 Successive Approximation Register ar...

Page 455: ...parison voltage Note 1 This register must always be accessed in halfwords Note 2 During comparator mode each bit of this register corresponds to channel 0 through channel 15 When comparator mode is selected with A D1 Single Mode Register 1 AD1SMSL A D1 conversion mode select bit the selected analog input value and the value written to the A D1 Successive Approximation Register are compared and the...

Page 456: ...0 Data Register 13 AD0DT13 Address H 0080 00AA 10 bit A D0 Data Register 14 AD0DT14 Address H 0080 00AC 10 bit A D0 Data Register 15 AD0DT15 Address H 0080 00AE When reset indeterminate D Bit Name Function R W 0 5 No functions assigned 0 6 15 AD0DT0 AD0DT15 A D conversion result A D0 data Note These registers must always be accessed in halfwords In A D0 Converter single mode the result of A D conv...

Page 457: ...13 AD1DT13 Address H 0080 0AAA 10 bit A D1 Data Register 14 AD1DT14 Address H 0080 0AAC 10 bit A D1 Data Register 15 AD1DT15 Address H 0080 0AAE When reset indeterminate D Bit Name Function R W 0 5 No functions assigned 0 6 15 AD1DT0 AD1DT15 A D conversion result A D1 data Note These registers must always be accessed in halfwords In A D1 Converter single mode the result of A D conversion is stored...

Page 458: ...0 Data Register 13 AD08DT13 Address H 0080 00EB 8 bit A D0 Data Register 14 AD08DT14 Address H 0080 00ED 8 bit A D0 Data Register 15 AD08DT15 Address H 0080 00EF This A D data register has the A D0 Converter s 8 bit conversion result stored in it In A D0 Converter single mode the result of A D conversion is stored in the 8 bit A D0 Data Register of the corresponding channel In single shot or conti...

Page 459: ...3 AD18DT13 Address H 0080 0AEB 8 bit A D1 Data Register 14 AD18DT14 Address H 0080 0AED 8 bit A D1 Data Register 15 AD18DT15 Address H 0080 0AEF This A D data register has the A D1 Converter s 8 bit conversion result stored in it In A D1 Converter single mode the result of A D conversion is stored in the 8 bit A D1 Data Register of the corresponding channel In single shot or continuous scan mode e...

Page 460: ...ply and ground AVCC AVSS from those of the digital block and take a sufficient protective measure against noise For details about the accuracy of conversion see Section 11 3 5 Accuracy of A D Conversion ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 Selector AVSS0 VREF0 10 bit A Di Successive Approximation Register ADiSAR 10 bit A Di Data Register A Di Comparate Data Register A D Control ...

Page 461: ... value stored in the A D Successive Approximation Register is made the valid A D conversion result Figure 11 3 2 Change of A D Successive Approximation Register Content during A D Conversion Note The comparison voltage Vref the voltage entered from the D A Converter into the Comparator is determined according to changes of the content of the A D Successive Approximation Register The comparison vol...

Page 462: ...ecified channel is completed the content of the A D Successive Approximation Register is transferred to the corresponding 10 bit A D Data Registers 0 15 and the convert operations b through g described above are executed for the next channel to be converted In single shot scan mode convert operation stops when A D conversion in one specified scan loop is finished 3 For continuous scan mode When co...

Page 463: ...comparison voltage Vref and the analog input voltage VIN Next store the comparison result in the comparate result flag A D Comparate Data Register D15 bit If Vref VIN then the comparate result flag 0 If Vref VIN then the comparate result flag 1 d Stop comparate operation after storing the comparison result The comparison result is stored in the A D Comparate Data Register AD0CMP or AD1CMP s corres...

Page 464: ... to when the CPU can stably read out the conversion result from the A D Data Register e Scan interval dummy time The time during single shot or continuous scan mode from when the A D Converter finishes A D conversion on a channel to when it starts A D conversion on the next channel A D conversion time start dummy time execution cycle time scan interval dummy time execution cycle time scan interval...

Page 465: ...ock Periods Unit BCLK Transfer Start dummy A D conversion Comparate End Scan interval speed Note 1 Note 2 Note 3 execution cycle execution cycle dummy dummy Note 4 Low speed Normal 4 4 4 294 42 1 4 mode Double speed 4 4 4 168 24 1 4 High speed Normal 4 4 4 126 18 1 4 mode Double speed 4 4 4 84 12 1 4 Note 1 When started by a software trigger Note 2 When started by a hardware trigger Note 3 When wr...

Page 466: ...ed mode Normal Single mode 131 Single shot n channels scanned 130 n 1 continuous scan mode Comparator mode 23 High speed mode Double Single mode 89 Single shot n channels scanned 88 n 1 continmuous scan mode Comparator mode 17 Note 1 For single and comparator modes this refers to the A D conversion or comparate time needed for one channel For single shot and continuous scan modes this refers to th...

Page 467: ...e 89 Single shot n channels scanned 88 n 1 continuous scan mode Comparator mode 17 Note 1 For single and comparator modes this refers to the A D conversion or comparate time needed for one channel For single shot and continuous scan modes this refers to the A D conversion time needed for one scan loop Note 2 For the A D0 Converter this refers to the time from TOM0_6 underflow input on external pin...

Page 468: ...aid to be 2 LSB it means that if the input voltage is 25 mV for example the actual A D conversion result is in the range of H 003 to H 007 whereas the output code that can be expected from an ideal A D converter is H 005 Note that absolute accuracy includes a zero error and full scale error Although when actually using the A D Converter the analog input voltages are in the range of AVSS0 to VREF0 ...

Page 469: ...ut voltage mV Ideal A D conversion characteristic A D conversion characteristic with infinite resolution 5 10 15 20 25 30 35 40 45 50 55 H 007 H 008 H 009 H 00A H 00B 2 LSB 2 LSB Figure 11 3 5 Absolute Accuracy of the A D Converter A D CONVERTERS 11 3 Functional Description of the A D Converters ...

Page 470: ... analog input signals The A D Converter described here does not contain a sample and hold circuit Therefore make sure the analog input levels are fixed during A D conversion Timing at which to read the A D conversion complete bit If it is necessary to read the A D conversion complete bit Single Mode Register 0 D5 bit or Scan Mode Register 0 D5 bit immediately after starting A D conversion be sure ...

Page 471: ...Operation in CSIO Mode 12 4 Receive Operation in CSIO Mode 12 5 Precautions on Using CSIO Mode 12 6 Transmit Operation in UART Mode 12 7 Receive Operation in UART Mode 12 8 Fixed Period Clock Output Function 12 9 Precautions on Using UART Mode CHAPTER 12 CHAPTER 12 SERIAL I O ...

Page 472: ...l I O The communication performed in this mode is synchronized to the transfer clock using the same clock on both transmit and receive sides Data are transferred in a fixed length of 8 bits UART mode asynchronous serial I O The communication performed in this mode is asynchronous The transfer data length can be selected from 7 8 or 9 bits Serial I Os 0 7 each have transmit DMA and receive DMA tran...

Page 473: ...Start bit 1 bit Character length 7 8 or 9 bits Parity bit With or without odd even selectable Stop bit 1 or 2 bits Order of transfer LSB first fixed Baud rate CSIO mode 152 bits second to 2 Mbits second when f BCLK 20 MHz UART mode 19 bits second to 156 Kbits second when f BCLK 20 MHz Error detection CSIO mode Overrun error only UART mode Overrun parity and framing errors Any error if occurs is in...

Page 474: ...nsmit Receive Interrupt Group Interrupt SIO3 receive complete or receive error interrupt SIO2 3 Transmit Receive Interrupt Group Interrupt selectable SIO4 transmit buffer empty interrupt SIO4 transmit interrupt SIO4 receive complete or receive error interrupt SIO4 receive interrupt selectable SIO5 transmit buffer empty interrupt SIO5 transmit interrupt SIO5 receive complete or receive error interr...

Page 475: ...el 3 SIO2 transmit buffer empty Channels 0 and 7 SIO2 receive complete Channel 5 SIO3 transmit buffer empty Channels 4 and 9 SIO3 receive complete Channel 8 SIO4 transmit buffer empty Channel 5 SIO4 receive complete Channel 1 SIO5 transmit buffer empty Channel 7 SIO5 receive complete Channel 2 SIO6 transmit buffer empty Channel 8 SIO6 receive complete Channel 6 SIO7 transmit buffer empty Channel 0...

Page 476: ...LKI1 SCLKO1 To DMA6 To Interrup Controller To Interrup Controller SIO0 SIO1 SIO2 RXD1 TXD1 SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA0 7 RXD2 TXD2 Transmit Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request Receive interrupt Receive DMA transfer request...

Page 477: ...ceive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA6 To DMA1 SIO7 To DMA0 RXD7 TXD7 SIO7 Transmit Shift Register SIO7 Receive Buffer Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA9 SCLKI5 To DMA7 To Interrupt Controller To Interrupt Controller SIO5 RXD5 TXD5 SIO5 Transmit Shift Register SIO5 Receive Shi...

Page 478: ...ister S1MOD SIO0 Transmit Buffer Register S1TXB SIO0 Receive Buffer Register S1RXB SIO1 Receive Control Register S1RCNT SIO0 Baud Rate Register S1BAUR SIO2 Transmit Control Register S2TCNT SIO2 Transmit Receive Mode Register S2MOD SIO2 Transmit Buffer Register S2TXB SIO2 Receive Buffer Register S2RXB SIO2 Receive Control Register S2RCNT SIO2 Baud Rate Register S2BAUR SIO3 Transmit Control Register...

Page 479: ...ster S6RXB SIO6Transmit Receive Mode Register S6MOD SIO6 Transmit Control Register S6TCNT SIO7 Receive Control Register S7RCNT SIO7 Baud Rate Register S7BAUR SIO7 Receive Buffer Register S7RXB SIO7 Transmit Receive Mode Register S7MOD SIO7 Transmit Control Register S7TCNT H 0080 0A24 SIO7 Transmit Buffer Register S7TXB H 0080 0A44 H 0080 0A40 H 0080 0A42 H 0080 0A46 H 0080 0A10 H 0080 0A12 H 0080 ...

Page 480: ...rupts A transmit interrupt is generated by enabling its corresponding TEN Transmit Enable bit while the SIO Interrupt Mask Register is enabled for interrupts 3 Regarding DMA transfer requests from SIO Each SIO can generate transmit DMA transfer and receive complete DMA transfer requests These DMA transfer requests can be generated by enabling the corresponding TEN Transmit Enable or TEN Receive En...

Page 481: ...is generated when the receive buffer is full Figure 12 2 4 Receive complete DMA Transfer Request SERIAL I O 12 2 Serial I O Related Registers Receive DMA transfer request Note If a receive error occurs no receive complete DMA transfer requests are generated RFIN Receive complete bit ...

Page 482: ...ed W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing Transmit receive interrupt requests from SIO2 and SIO3 are described below Setting the interrupt request status bit The interrupt request status bit is set in hardware and cannot be set in software Clearing the interrupt request status bit The interrupt request status bit is cleared by writing ...

Page 483: ...bit retains the value it had before writing Transmit receive interrupt requests from SIO6 and SIO7 are described below Setting the interrupt request status bit The interrupt request status bit is set in hardware and cannot be set in software Clearing the interrupt request status bit The interrupt request status bit is cleared by writing 0 in software Note If the status bit is set in hardware at th...

Page 484: ... Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 12 T2MASK SIO2 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 13 R2MASK SIO2 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 14 T3MASK SIO3 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 15...

Page 485: ... 12 T6MASK SIO6 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 13 R6MASK SIO6 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 14 T7MASK SIO7 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 15 R7MASK SIO7 receive 0 Masks disables interrupt request interrupt mask bit 1 Ena...

Page 486: ...use select bit 1 Receive error interrupt 7 ISR3 0 Receive complete interrupt SIO3 receive interrupt cause select bit 1 Receive error interrupt This register selects the cause of interrupt generated at completion of receive operation When set to 0 Setting this bit to 0 selects Receive complete interrupt receive buffer full A receive complete interrupt is generated even when an error occurred when r...

Page 487: ...pt 7 ISR7 0 Receive complete interrupt SIO7 receive interrupt cause select bit 1 Receive error interrupt This register selects the cause of interrupt generated at completion of receive operation When set to 0 Setting this bit to 0 selects Receive complete interrupt receive buffer full A receive complete interrupt is generated even when an error occurred when receiving data except for an overrun er...

Page 488: ...XD3 receive error b7 Figure 12 2 5 Block Diagram of SIO2 3 Transmit Receive Interrupts Figure 12 2 6 Block Diagram of SIO6 7 Transmit Receive Interrupts SERIAL I O 12 2 Serial I O Related Registers SIO6 7 transmit receive interrupt Data bus b4 IRQT6 F F T6MASK F F b12 b5 IRQR6 F F R6MASK F F b13 b6 IRQT7 F F T7MASK F F b14 b7 IRQR7 F F R7MASK F F b15 Level 4 source inputs SI67STAT H 0080 0A00 TXD6...

Page 489: ...A40 D0 1 2 3 4 5 6 D7 CDIV TSTAT TBE TEN When reset H 12 D Bit Name Function R W 0 1 No functions assigned 0 2 3 CDIV D2 D3 BRG count source select bit 0 0 Selects f BCLK 0 1 Selects divided by 8 clock of f BCLK 1 0 Selects divided by 32 clock of f BCLK 1 1 Selects divided by 256 clock of f BCLK 4 No functions assigned 0 5 TSTAT 0 Transmission idle no data exist Transmit status bit in transmit buf...

Page 490: ... Shift Register nor does data exist in the Transmit Buffer Register It also is cleared upon clearing the transmit enable bit 3 TBE transmit buffer empty bit D6 Set condition This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register with the Transmit Buffer Register thereby emptied It also is set by clearing the transmit enable bit Clear conditio...

Page 491: ...D D8 D9 D10 Serial I O mode select bit 0 0 0 7 bit UART Note 1 0 0 1 8 bit UART 0 1 X 9 bit UART 1 X X 8 bit clock synchronized serial I O 11 CKS internal external clock 0 Internal clock select bit 1 External clock Note 2 12 STB stop bit length select bit 0 1 stop bit UART mode only 1 2 stop bits Note 3 13 PSEL odd even parity select bit 0 Odd parity UART mode only 1 Even parity Note 3 14 PEN pari...

Page 492: ...ts two stop bits During clock synchronized mode the content of this bit has no effect 4 PSEL odd even parity select bit D13 This bit is effective when in UART mode When parity is enabled D14 1 use this bit to select the parity attribute odd or even Setting this bit to 0 selects odd parity setting this bit to 1 selects even parity When parity is disabled D14 0 and when in clock synchronized mode th...

Page 493: ...5 D4 D3 D2 D1 D0 PAR SP ST Note 1 Note 2 7 bit UART mode D7 D6 D5 D4 D3 D2 D1 Clock synchronized mode D0 Note 1 The parity bit can be chosen to be or not to be included Note 2 The stop bit length can be selected between one bit or two bits Direction of transfer ST Start Bit PAR Parity Bit Equivalent to one frame D Data Bit SP Stop Bit When the attribute odd or even represented by the number of 1 s...

Page 494: ...er Registers are used to set transmit data These registers are a write only register so that the register contents cannot be read out When setting transmit data in this register make sure the data is LSB aligned and that the data is written to D9 D15 for 7 bit data UART mode only D8 D15 for 8 bit data or D7 D15 for 9 bit data UART mode only Before writing transmit data to this register be sure to ...

Page 495: ...ceive Buffer Registers are used to store the received data When the SIO finishes receiving data the received data is transferred from the SIO Receive Shift Register to the SIO Receive Buffer Register The SIO Receive Buffer Registers are a read only register For 7 bit data UART mode only the data are set in D9 D15 with D8 and D7 always set to 0 For 8 bit data the data are set in D8 D15 with D7 alwa...

Page 496: ...H 0080 0A46 D0 1 2 3 4 5 6 D7 RSTAT RFIN REN OVR PTY FLM ERS When reset H 00 D Bit Name Function R W 0 No functions assigned 0 1 RSTAT 0 Not receiving idle Receive status bit 1 Receiving data 2 RFIN 0 No data exist in the receive buffer Receive finished bit register 1 Data exist in the receive buffer register 3 REN 0 Disables reception Receive enable bit 1 Enables reception 4 OVR 0 No overrun erro...

Page 497: ...SIO for reception setting this bit to 0 disables the SIO against reception while at the same initializing the receiver unit Pursuant to this bit manipulation the receive status flag and receive finished flag bits as well as the overrun error framing error parity error and errorsum flags all are cleared to 0 If the receive enable bit is cleared to 0 while receiving data the receive operation stops ...

Page 498: ...it to 0 6 FLM Framing error bit D6 This bit is effective in only UART mode It is fixed to 0 during CSIO mode Set condition This bit is set to 1 when the number of received bits does not match the one selected with the SIO Transmit Receive Mode Register Clear condition This bit is cleared upon reading out the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Reg...

Page 499: ...ud rate count source selected with the SIO Mode Register by n 1 where n is the BRG value that is set with this register In the initial state the BRG value is indeterminate so always be sure to set the divide value with this register before using serial I O The value written to the BRG register while sending or receiving data becomes effective beginning with the next cycle after the BRG counter fin...

Page 500: ...e changed to the SCLKO pin so that a divided by 2 clock of BRG output is generated When using an internal clock internal clock CSIO mode or UART mode with f BCLK selected for the BRG count source the BRG value set with this register requires caution During CSIO mode make sure the transfer speed will not exceed 2 Mbits second during UART mode make sure the BRG value is equal to or greater than 7 SE...

Page 501: ...elected from 1 8 32 or 256 by using the CDIV baud rate generator count source select bits Transmit Control Register D2 D3 bits The baud rate generator divides the clock divider output by baud rate register set value 1 and then by 2 which results in generating a transmit receive shift clock When the internal clock is selected in CSIO mode the baud rate is calculated using the equation below 1 BCLK ...

Page 502: ...tion 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit buffer empty interrupt during transmission set its priority level 6 Setting DMAC When you issue DMA transfer requests to the internal DMAC whe...

Page 503: ...Transmit Receive Mode Register Initial settings for CSIO transmission Set register to CSIO mode Select internal or external clock When using DMAC Set DMAC When using interrupt Set the Interrupt Controller Enable disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide by ratio H 00 to H FF Note 2 Set SIO Baud Rate Register Select clock divider s divide by ratio Note 1 Set SIO...

Page 504: ...he lower byte of the transmit buffer register in Note 1 above triggers a start of transmission Note 3 The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register When transmission starts the serial I O transmits data following the procedure below Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register Set the...

Page 505: ...ated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 3 7 Transmit DMA Transfer Reque...

Page 506: ...gister The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y Successive transmission Transmit conditions met Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request Note CSIO transmit operation starts CSIO transmit operation completed Tran...

Page 507: ...uest is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied 12 3 8 Typical CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode Processing by software Interrupt generation Internal clock selected External clock selected CSIO on receive side SCLKO TXD SCLKI RXD Transmit clock SCLKO...

Page 508: ... the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Interrupt generation First data Next data Note 2 Note 3 Note 2 Upon transmit buffer empty interrupt next data is written First data Next data Note 4 Processing by software Internal clock selected External cloc...

Page 509: ...ernal clock selected 3 Setting SIO Baud Rate Register When the internal clock is selected set a baud rate generator value Refer to Section 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register Select the cause of receive interrupt receive finished error Cause of Receive Interrupt Select Register 5 S...

Page 510: ...nd Pin Functions SERIAL I O 12 4 Receive Operation in CSIO Mode Set SIO Transmit Receive Mode Register Initial settings for CSIO reception Set to CSIO mode Select internal or external clock When using DMAC Set DMAC When using interrupt Set the Interrupt Controller Enable disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide by ratio H 00 to H FF Note 2 Set SIO Baud Rate Re...

Page 511: ...t serial data LSB first synchronously with the receive shift clock 12 4 3 Processing at End of CSIO Reception When data reception is completed the following operation is automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request i...

Page 512: ... data may be received successively The receive enable bit is set to 1 Transmit conditions are met No overrun error has occurred Receive data Set SIO Receive Control Register s receive finished bit to 1 Store received data in Receive Buffer Register Set SIO Receive Control Register s overrun error and receive sum error bits to 1 Overrun error Receive conditions met Y N CSIO receive operation starts...

Page 513: ... the next data before you read an overrun error occurs In this case the data received thereafter is not transferred to the SIO Receive Buffer Register To restart reception temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart The said receive enable bit can be cleared when there are no receive errors note encountered by reading the lower byte fro...

Page 514: ... Receive Interrupt Control Register interrupt request bit cleared SIO receive interrupt Note 1 When receive finished interrupt is selected Clock stopped Automatically cleared for each receive operation performed Receive finished bit Read from receive buffer When receive error interrupt is selected Receive finished interrupt Note 2 Interrupt request accepted Note 3 No interrupt request Internal clo...

Page 515: ...cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared Note 4 Receive error interrupt Note 3 Internal clock selected External clock selected CSIO on transmit side SCLKO RXD SCLKI TXD Transmit clock SCLKO Set Receive enable bit CSIO on receive side CSIO on receive side Cleared D7 D6 D0 D7 D6 D0 RXD Set SIO receive interrupt No...

Page 516: ...Register before transmission of the preceding data is completed About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit you need to execute transmit operation by sending dummy data even when you only want to receive data In this case note that if the port function is set for TXD pin by setting the operation mode register to 1 dummy data is...

Page 517: ...s bit 1 To restart reception normally you need to temporarily clear the receive enable bit before you restart This is the only way you can clear the overrun error flag About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty the transmit buffer empty flag 1 while the transmit enable bit is set to 1 transmit enabled an SIO transmit buffer empty DMA...

Page 518: ... The clock divider s divide by value is selected from 1 8 32 or 256 note using the SIO Transmit Control Register s CDIV baud rate generator count source select bits D2 D3 The Baud Rate Generator divides the clock it received from the clock divider by baud rate register set value 1 and further divides the resulting clock by 16 to produce a transmit receive shift clock During UART mode in which the ...

Page 519: ...iately before the transmit data D0 D8 character bits Transmit receive data transferred via serial I O In UART mode data in 7 8 or 9 bits can be transmitted received PAR parity bit Added to the transmit receive characters When parity is enabled parity is automatically set in such a way that the number of 1 s in characters including the parity bit itself is always even or odd as selected by the even...

Page 520: ... D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB D8 D8 D8 D8 Start bit Character data bits Parity bit Stop bit D0 D7 D8 D15 SIO Transmit Buffer Register SIO Receive Buffer Register ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB ST D7 D6 D5 D4 D3 D2 D1 PAR SP S...

Page 521: ...rol Register Select the clock divider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable SIO transmit interrupt 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit interrupt set its priority level 6 Setting DMAC Wh...

Page 522: ...for UART transmission Set register to UART mode Set parity when enabled select odd even When using DMAC Set DMAC related registers When using interrupt Set the Interrupt Controller Enable disable transmit interrupt Set SIO Interrupt Related Registers Divide by ratio H 00 to H FF Note Set SIO Baud Rate Register Select clock divider s divide by ratio Set SIO Transmit Control Register Set input outpu...

Page 523: ... SIO Transmit Buffer Register to the SIO Transmit Shift Register Set the transmit buffer empty bit to 1 Note Start sending data synchronously with the shift clock beginning with the LSB Note A transmit buffer empty interrupt request and or a DMA transfer request can be generated when the transmit buffer is emptied 12 6 5 Successive UART Transmission Once data is transferred from the transmit buffe...

Page 524: ...ated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 6 8 Transmit DMA Transfer Reque...

Page 525: ...gister The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y Successive transmission Transmit conditions met Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request Note UART transmit operation starts UART transmit operation completed Tran...

Page 526: ...it cleared Note 4 Transmit interrupt request is generated when transmission is enabled Note 5 Even after transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Processing by software Interrupt generation UART on receive side TXD RXD Set ...

Page 527: ...ta is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Interrupt generation First data Next data Note 2 Note 4 Note 2 Upon transmit interrupt next data is written First data Next data Note 5 Processing by software UART on receive side TXD RXD Set T...

Page 528: ...ivider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO interrupt related registers Cause of Receive Interrupt Select Register Select the cause of receive interrupt receive finished receive error Interrupt Mask Register Enable disable receive interrupts 5 Setting the Interrupt Controller When you use...

Page 529: ...ed select odd even When using DMAC Set DMAC related registers When using interrupt Set the interrupt controller SIO Receive Interrupt Control Register Set SIO Interrupt Related Registers Divide by ratio H 00 to H FF Note Set SIO Baud Rate Register Select clock divider s divide by ratio Set SIO Transmit Control Register Set input output port Operation Mode Register Serial I O related registers Init...

Page 530: ...s automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request is generated Note 2 A DMA transfer request is generated 2 When error occurs during reception When an error occurs during reception the corresponding error bit OE FE or P...

Page 531: ...ster s receive finished bit to 1 Set receive status bit to 1 Overrun error Parity error or framing error Start bit detected normally Set SIO Receive Control Register s overrun error bit and error sum bit to 1 Set SIO Receive Control Register s corresponding error bit and receive error sum bit to 1 N UART reception completed The following processing is automatically executed in hardware Transmit co...

Page 532: ...ontroller IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit cleared SIO receive interrupt Note 1 When receive finished interrupt is selected Automatically cleared for each receive operation performed Receive finished bit Read from receive buffer When receive error interrupt is selected Receive finished interrupt Note 2 Interrupt request accepted Note 3 No inter...

Page 533: ... Control Register interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared Note 4 Receive error interrupt Note 3 UART on transmit side RXD TXD Set UART on receive side UART on receive side ST D7 SP ST D7 SP RXD Set SIO receive interrupt Note 1 When receive finished interrupt is selected When receive error ...

Page 534: ... SCLKO4 or SCLKO5 pin In this way a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin Note This clock is output all the time not just during data transfer Figure 12 8 1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmit receive ST SP Data ST SP Data 50 50 BRG period Internal BRG output SCLKO output 1 Configuration w...

Page 535: ...he next period after the BRG counter finished counting However when transmit and receive operations are disabled the register value can be changed at the same time you write to the register Transmit receive operations using DMA To transmit receive data in DMA request mode enable the DMAC to accept transfer requests by setting the DMA Mode Register before you start serial communication About overru...

Page 536: ...eceive Control Register overrun error bit SIO Receive Control Register parity error bit SIO Receive Control Register framing error bit The manner in which the receive finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not as described below When no overrun error has occurred Said bits can be cleared by reading the lower byte from the r...

Page 537: ... CAN Module Related Registers 13 3 CAN Protocol 13 4 Initialization of the CAN Module 13 5 Transmitting Data Frames 13 6 Receiving Data Frames 13 7 Transmitting Remote Frames 13 8 Receiving Remove Frames CHAPTER 13 CHAPTER 13 CAN MODULES ...

Page 538: ...bit counter The count period can be setto divide by 1 2 3 or 4 with respect to the CAN bus bit period as the fundamental period BasicCAN mode BasicCAN function is materialized using two local slots Transmit abort function Transmit request can be canceled Loopback function The data transmitted by CAN module itself is received Return bus off function Forcibly placed into error active mode after clea...

Page 539: ...N0 bus error interrupt CAN0 transmit receive error interrupt CAN0 error passive interrupt CAN0 transmit receive error interrupt CAN0 bus off interrupt CAN0 transmit receive error interrupt CAN1 transmit complete interrupt CAN1 transmit receive error interrupt CAN1 receive complete interrupt CAN1 transmit receive error interrupt CAN1 bus error interrupt CAN1 transmit receive error interrupt CAN1 er...

Page 540: ...ge data 4 Time stamp CAN0 Status Register CAN0 Control Register CTX1 CRX1 CAN1 Protocol Controller 2 0B active CAN1 Message Slot 0 15 Control Register CAN1 Global Mask Register CAN1 Local Mask Register A CAN1 Local Mask Register B CAN1 Extended ID Register Message Memory Acceptance Filtering 16 bit Timer CAN1 Time stamp Register CAN1 Configuration Register CAN1 Slot Status Register CAN1 Slot Inter...

Page 541: ...lot 5 Control Register C0MSL5CNT CAN0 Message Slot 7 Control Register C0MSL7CNT CAN0 Message Slot 9 Control Register C0MSL9CNT CAN0 Message Slot 11 Control Register C0MSL11CNT CAN0 Message Slot 13 Control Register C0MSL13CNT CAN0 Message Slot 15 Control Register C0MSL15CNT CAN0 Message Slot 6 Control Register C0MSL6CNT CAN0 Message Slot 8 Control Register C0MSL8CNT CAN0 Message Slot 10 Control Reg...

Page 542: ...0MSL2EID2 CAN0 Message Slot 2 Data 0 C0MSL2DT0 CAN0 Message Slot 2 Data 2 C0MSL2DT2 CAN0 Message Slot 2 Data 4 C0MSL2DT4 CAN0 Message Slot 2 Extended ID1 C0MSL2EID1 CAN0 Message Slot 2 Data Length Register C0MSL2DLC CAN0 Message Slot 2 Data 1 C0MSL2DT1 CAN0 Message Slot 2 Data 3 C0MSL2DT3 CAN0 Message Slot 2 Data 5 C0MSL2DT5 CAN0 Message Slot 2 Data 6 C0MSL2DT6 CAN0 Message Slot 2 Data 7 C0MSL2DT7...

Page 543: ... CAN0 Message Slot 7 Data 1 C0MSL7DT1 CAN0 Message Slot 8 Data 3 C0MSL8DT3 CAN0 Message Slot 8 Data 5 C0MSL8DT5 CAN0 Message Slot 8 Data 6 C0MSL8DT6 CAN0 Message Slot 8 Data 7 C0MSL8DT7 CAN0 Message Slot 8 Time stamp C0MSL8TSP CAN0 Message Slot 8 Standard ID1 C0MSL8SID1 CAN0 Message Slot 8 Standard ID0 C0MSL8SID0 CAN0 Message Slot 7 Extended ID0 C0MSL7EID0 CAN0 Message Slot 7 Extended ID2 C0MSL7EI...

Page 544: ...0MSL12DT7 CAN0 Message Slot 12 Time stamp C0MSL12TSP CAN0 Message Slot 12 Standard ID1 C0MSL12SID1 CAN0 Message Slot 12 Standard ID0 C0MSL12SID0 CAN0 Message Slot 13 Extended ID0 C0MSL13EID0 CAN0 Message Slot 13 Extended ID2 C0MSL13EID2 CAN0 Message Slot 13 Data 0 C0MSL13DT0 CAN0 Message Slot 13 Data 2 C0MSL13DT2 CAN0 Message Slot 13 Data 4 C0MSL13DT4 CAN0 Message Slot 13 Extended ID1 C0MSL13EID1 ...

Page 545: ...2CNT CAN1 Message Slot 14 Control Register C1MSL14CNT CAN1 Error Interrupt Status Register CAN1ERIST CAN1 Error Interrupt Mask Register CAN1ERIMK CAN1 Baud Rate Prescaler CAN1BRP CAN1 Global Mask Register Standard ID1 C1GMSKS1 CAN1 Global Mask Register Extended ID0 C1GMSKE0 CAN1 Global Mask Register Extended ID1 C1GMSKE1 CAN1 Global Mask Register Extended ID2 C1GMSKE2 CAN1 Local Mask Register A St...

Page 546: ...2 Standard ID0 C1MSL2SID0 CAN1 Message Slot 3 Extended ID0 C1MSL3EID0 CAN1 Message Slot 3 Extended ID2 C1MSL3EID2 CAN1 Message Slot 3 Data 0 C1MSL3DT0 CAN1 Message Slot 3 Data 2 C1MSL3DT2 CAN1 Message Slot 3 Data 4 C1MSL3DT4 CAN1 Message Slot 3 Extended ID1 C1MSL3EID1 CAN1 Message Slot 3 Data Length Register C1MSL3DLC CAN1 Message Slot 3 Data 1 C1MSL3DT1 CAN1 Message Slot 3 Data 3 C1MSL3DT3 CAN1 M...

Page 547: ... C1MSL7DT4 CAN1 Message Slot 7 Extended ID1 C1MSL7EID1 CAN1 Message Slot 7 Data Length Register C1MSL7DLC CAN1 Message Slot 7 Data 3 C1MSL7DT3 CAN1 Message Slot 7 Data 5 C1MSL7DT5 CAN1 Message Slot 7 Data 6 C1MSL7DT6 CAN1 Message Slot 7 Data 7 C1MSL7DT7 CAN1 Message Slot 7 Time stamp C1MSL7TSP CAN1 Message Slot 7 Standard ID1 C1MSL7SID1 CAN1 Message Slot 7 Standard ID0 C1MSL7SID0 CAN1 Message Slot...

Page 548: ...1 Message Slot 13 Data 5 C1MSL13DT5 CAN1 Message Slot 13 Data 6 C1MSL13DT6 CAN1 Message Slot 13 Data 7 C1MSL13DT7 CAN1 Message Slot 13 Time stamp C1MSL13TSP CAN1 Message Slot 13 Standard ID1 C1MSL13SID1 CAN1 Message Slot 13 Standard ID0 C1MSL13SID0 CAN1 Message Slot 14 Extended ID0 C1MSL14EID0 CAN1 Message Slot 14 Extended ID2 C1MSL14EID2 CAN1 Message Slot 14 Data 0 C1MSL14DT0 CAN1 Message Slot 14...

Page 549: ...P D6 D7 Time stamp prescaler 0 0 Selects CAN bus bit clock 0 1 Selects divide by 2 of CAN bus bit clock 1 0 Selects divide by 3 of CAN bus bit clock 1 1 Selects divide by 4 of CAN bus bit clock 8 9 No functions assigned 0 10 No functions assigned Always set this bit to 0 0 11 FRST 0 Negates reset Forcible reset 1 Forcibly reset 12 BCM 0 Disables BasicCAN function BasicCAN mode 1 Enables BasicCAN m...

Page 550: ...SP Time stamp prescaler bits D6 D7 These bits select the count clock source for the time stamp counter Note Do not alter the value set with these TSP bits while the CAN module is operating CAN Status Register CRS bit 0 4 FRST Forcible reset bit D11 Setting this bit to 1 disconnects the CAN module from the CAN bus regardless of whether the CAN module is communicating or not with its protocol contro...

Page 551: ...ettings during initialization a Set the IDs of slots 14 and 15 and Local Mask Registers A and B We recommend setting the same value b Set the type of frame to be handled with slots 14 and 15 standard or extended in the CAN Extended ID Register We recommend setting the same type c Set the Message Slot Control Registers for slots 14 and 15 to receive data frames d Set the BCM bit to 1 Note 1 Do not ...

Page 552: ...slots which have had transmit requests set All frames received during this time are processed normally Note 1 No new transmit requests can be set from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset Note 2 When the protocol control unit is reset by setting the RST bit to 1 the CAN Time stamp Count Register and CAN Transmi...

Page 553: ...ssive status 1 Error passive state 3 CBS 0 No error occurred CAN bus error 1 Error occurred 4 BCS 0 Normal mode BasicCAN status 1 BasicCAN mode 5 No functions assigned 0 6 LBS 0 Normal mode Loopback status 1 Loopback mode 7 CRS 0 Operating CAN reset status 1 Reset state 8 RSB 0 Nor receiving Receive status 1 Receiving 9 TSB 0 Not transmitting Transmit status 1 Transmitting 10 RSC 0 Reception not c...

Page 554: ...te Set condition This bit is set to 1 when the value of the Transmit Error Count Register exceeds 255 with the CAN module in a bus off state Clear condition This bit is cleared when the CAN module returns from the bus off state 2 EPS Error passive status bit D2 When the EPS bit 1 it means that the CAN module is in a error passive state Set condition This bit is set to 1 when the value of the Trans...

Page 555: ...oth be set for data frame reception Clear condition This bit is cleared by clearing the BCM bit to 0 5 LBS Loopback status bit D6 When the LBS bit 1 it means that the CAN module is operating in loopback mode Set condition This bit is set to 1 by setting the CAN Control Register LBM loopback mode bit to 1 Clear condition This bit is cleared by clearing the LBM bit to 0 6 CRS CAN reset status bit D7...

Page 556: ... This bit is set to 1 when the CAN module finished receiving data normally regardless of whether there is any receive slot that satisfies receive conditions Clear condition This bit is cleared when the CAN module finished transmitting data normally 10 TSC Transmit complete status bit D11 Set condition This bit is set to 1 when the CAN module finished transmitting data normally Clear condition This...

Page 557: ...3 4 IDE4 Extended ID 4 5 IDE5 Extended ID 5 6 IDE6 Extended ID 6 7 IDE7 Extended ID 7 8 IDE8 Extended ID 8 9 IDE9 Extended ID 9 10 IDE10 Extended ID 10 11 IDE11 Extended ID 11 12 IDE12 Extended ID 12 13 IDE13 Extended ID 13 14 IDE14 Extended ID 14 15 IDE15 Extended ID 15 Each bit in this register selects the type of frame handled by the corresponding message slot Setting this bit to 0 selects the ...

Page 558: ... Segment2 3Tq 011 Phase Segment2 4Tq 100 Phase Segment2 5Tq 101 Phase Segment2 6Tq 110 Phase Segment2 7Tq 111 Phase Segment2 8Tq Note 1 Do not modify the CAN Configuration Register CAN0CONF or CAN1CONF while the CAN module is operating CAN Status Register CRS bit 0 Note 2 The bit configuration in this register must be set to meet the conditions below Number of Tq s in one bit 8 to 25 Tq s SJW min ...

Page 559: ...ion Segment 5Tq 101 Propagation Segment 6Tq 110 Propagation Segment 7Tq 111 Propagation Segment 8Tq 11 SAM 0 Samples once Sampling times 1 Samples three times 12 15 No functions assigned 0 1 SJW bits D0 D1 These bits set the width of reSynchronization Jump Width 2 PH2 bits D2 D4 These bits set the width of Phase Segment2 Note For the M32R E s internal CAN modules IPT Information Processing Time 2 ...

Page 560: ...he end of Phase Segment1 one sampled before 1Tq and one sampled before 2 Tq Baud rate BRP set value Tq period ns Number of Tq s in one bit PROP PH1 PH2 Sampling points 1M bps 3 100 10 7 2 80 3 100 10 6 3 70 3 100 10 5 4 60 4 125 8 5 2 75 4 125 8 4 3 63 500K bps 4 125 16 13 2 88 4 125 16 12 3 81 4 125 16 11 4 75 7 200 10 7 2 80 7 200 10 6 3 70 7 200 10 5 4 60 9 250 8 5 2 75 9 250 8 4 3 63 Table 13 ...

Page 561: ...T s RST bit to 0 Note 1 The protocol control unit is reset and the counter is initialized to H 0000 by setting the CAN Control Register CAN0CNT s RST CAN reset bit to 1 Also the count register can be initialized to H 0000 while the CAN module is operating by setting the TSR time stamp counter reset bit to 1 Note 2 During loopback mode if any ID matching slot exists the CAN module stores the time s...

Page 562: ... off state an indeterminate value is stored in this register The register value is reset to H 00 upon returning to an error active state CAN0 Transmit Error Count Register CAN0TEC Address H 0080 100B CAN1 Transmit Error Count Register CAN1TEC Address H 0080 140B When in an error active error passive state the transmit error count value is stored in this register The counter counts down during norm...

Page 563: ...dule Tq period The CAN baud rate is determined by Tq period x number of Tq s in one bit Tq period CANBRP 1 CPU clock 1 CAN transfer baud rate Tq period x number of Tq s in one bit Number of Tq s in one bit Synchronization Segment Propagation Segment Phase Segment 1 Phase Segment 2 Note 1 Setting H 00 divide by 1 is inhibited Note 2 Do not modify the CAN Baud Rate Prescaler CAN0BRP or CAN1BRP while...

Page 564: ...terrupt request status 3 SSB3 Slot 3 interrupt request status 4 SSB4 Slot 4 interrupt request status 5 SSB5 Slot 5 interrupt request status 6 SSB6 Slot 6 interrupt request status 7 SSB7 Slot 7 interrupt request status 8 SSB8 Slot 8 interrupt request status 9 SSB9 Slot 9 interrupt request status 10 SSB10 Slot 10 interrupt request status 11 SSB11 Slot 11 interrupt request status 12 SSB12 Slot 12 int...

Page 565: ...ter be sure to write 0 for the bits to be cleared and 1 for all other bits Writing 1 in software does not affect any bit of this register the bit retains the value it had before writing Note 1 For remote frame receive slots with the automatic answering function enabled the status is set after receiving a remote frame and again after sending a data frame Note 2 For remote frame transmit slots the s...

Page 566: ...t 6 interrupt request mask 7 IRB7 Slot 7 interrupt request mask 8 IRB8 Slot 8 interrupt request mask 9 IRB9 Slot 9 interrupt request mask 10 IRB10 Slot 10 interrupt request mask 11 IRB11 Slot 11 interrupt request mask 12 IRB12 Slot 12 interrupt request mask 13 IRB13 Slot 13 interrupt request mask 14 IRB14 Slot 14 interrupt request mask 15 IRB15 Slot 15 interrupt request mask This register is used ...

Page 567: ...e interrupt has been generated due to an error 1 EIS CAN bus error interrupt status bit D5 This bit is set to 1 when a communication error is detected This bit can be cleared by writing 0 in software 2 PIS Error passive interrupt status bit D6 This bit is set to 1 when the CAN module goes to an error passive state This bit can be cleared by writing 0 in software 3 OIS Bus off interrupt status bit ...

Page 568: ...bit D5 This bit enables or disables the interrupt request generated by occurrence of a CAN bus error Setting this bit to 1 enables CAN bus error interrupt request 2 PIM Error passive interrupt mask bit D6 This bit enables or disables the interrupt request generated by transition of the CAN module status to an error passive state Setting this bit to 1 enables an error passive interrupt request 3 OI...

Page 569: ... complete b5 IRB5 F F SSB5 F F b5 b6 IRB6 F F SSB6 F F b6 b7 IRB7 F F To 11 other input sources in the next page F F b7 SSB7 Slot 1 transmit receive complete Slot 2 transmit receive complete Slot 3 transmit receive complete Slot 4 transmit receive complete Slot 5 transmit receive complete Slot 6 transmit receive complete Slot 7 transmit receive complete Figure 13 2 9 Block Diagram of CAN0 Transmit...

Page 570: ...he preceding page Data bus Level 19 source inputs Slot 8 transmit receive complete To 3 other input sources in the next page Slot 9 transmit receive complete Slot 10 transmit receive complete Slot 11 transmit receive complete Slot 12 transmit receive complete Slot 13 transmit receive complete Slot 14 transmit receive complete Slot 15 transmit receive complete Figure 13 2 10 Block Diagram of CAN0 T...

Page 571: ...AN0ERIST H 0080 1014 CAN0ERIMK H 0080 1015 CAN bus error occurs Goes to error passive state Goes to bus off state To the preceding page Data bus Level 19 source inputs Figure 13 2 11 Block Diagram of CAN0 Transmit Receive Error Interrupts 3 3 CAN MODULES 13 2 CAN Module Related Registers ...

Page 572: ... error interrupt Data bus Level 19 source inputs Slot 0 transmit receive complete To 11 other input sources in the next page Slot 1 transmit receive complete Slot 2 transmit receive complete Slot 3 transmit receive complete Slot 4 transmit receive complete Slot 5 transmit receive complete Slot 6 transmit receive complete Slot 7 transmit receive complete Figure 13 2 12 Block Diagram of CAN1 Transmi...

Page 573: ...he preceding page Data bus Level 19 source inputs Slot 8 transmit receive complete To 3 other input sources in the next page Slot 9 transmit receive complete Slot 10 transmit receive complete Slot 11 transmit receive complete Slot 12 transmit receive complete Slot 13 transmit receive complete Slot 14 transmit receive complete Slot 15 transmit receive complete Figure 13 2 13 Block Diagram of CAN1 T...

Page 574: ... 3 3 b5 EIM F F EIS F F b13 b6 PIM F F PIS F F b14 b7 OIM F F OIS F F b15 CAN1ERIST H 0080 1414 CAN1ERIMK H 0080 1415 CAN bus error occurs Goes to error passive state Goes to bus off state To the preceding page Data bus Level 19 source inputs CAN MODULES 13 2 CAN Module Related Registers ...

Page 575: ...ions assigned 0 3 7 SID0M SID4M 0 ID not checked Standard ID0 to standard ID4 1 ID checked CAN0 Global Mask Register Standard ID1 C0GMSKS1 Address H 0080 1029 CAN0 Local Register A Standard ID1 C0LMSKAS1 Address H 0080 1031 CAN0 Local Mask Register B Standard ID1 C0LMSKBS1 Address H 0080 1039 CAN1 Global Mask Register Standard ID1 C1GMSKS1 Address H 0080 1429 CAN1 Local Register A Standard ID1 C1L...

Page 576: ...When any bit in this register is set to 1 the corresponding ID bit is compared with the received ID during acceptance filtering If it matches the ID set for the message slot the received data is stored in that slot Note 1 SID0M corresponds to the MSB of the standard ID Note 2 The Global Mask Register can only be modified when none of the slots 0 13 has receive requests set Note 3 The Local Mask Re...

Page 577: ...igned 0 4 7 EID0M EID3M 0 ID not checked Extended ID0 to extended ID3 1 ID checked CAN0 Global Mask Register Extended ID1 C0GMSKE1 Address H 0080 102B CAN0 Local Register A Extended ID1 C0LMSKAE1 Address H 0080 1033 CAN0 Local Mask Register B Extended ID1 C0LMSKBE1 Address H 0080 103B CAN1 Global Mask Register Extended ID1 C1GMSKE1 Address H 0080 142B CAN1 Local Register A Extended ID1 C1LMSKAE1 A...

Page 578: ... Local Mask Register B The Global Mask Register is used for message slots 0 13 while the Local Mask Registers A and B respectively are used for slots 14 and 15 When any bit in this register is set to 0 the corresponding ID bit is masked during acceptance filtering so that the ID is assumed to have matched When any bit in this register is set to 1 the corresponding ID bit is compared with the recei...

Page 579: ...egister C0MSL14CNT Address H 0080 105E CAN0 Message Slot 15 Control Register C0MSL15CNT Address H 0080 105F CAN1 Message Slot 0 Control Register C1MSL0CNT Address H 0080 1450 CAN1 Message Slot 1 Control Register C1MSL1CNT Address H 0080 1451 CAN1 Message Slot 2 Control Register C1MSL2CNT Address H 0080 1452 CAN1 Message Slot 3 Control Register C1MSL3CNT Address H 0080 1453 CAN1 Message Slot 4 Cont...

Page 580: ...uest accepted For receive slots 0 Not receiving idle 1 Storing the received data 7 TRFIN For transmit slots Transmit receive 0 Not transmitted yet finished 1 Finished transmitting For receive slots 0 Not received yet 1 Finished receiving W Only writing 0 is effective Writing 1 has no effect the bit retains the value it had before writing CAN MODULES 13 2 CAN Module Related Registers Note 1 Do not ...

Page 581: ... a data frame receive slot However if a data frame is received before the CAN module finished sending the remote frame the received data is stored in the message slot and the remote frame is not transmitted Set for remote frame reception The message slot receives a remote frame The processing performed after reception depends on how the RL Automatic answering disable bit is set 4 RL Automatic answ...

Page 582: ...me when RA 1 it means that the frame stored in the slot is a remote frame 6 ML Message lost bit D5 This bit is effective for receive slots It is set to 1 when the received data stored in the message slot is overwritten by receive operation before being read out This bit is cleared by writing 0 in software 7 TRSTAT Transmit receive status bit D6 This bit indicates that transmission or reception is ...

Page 583: ...ly that is to be stored in the message slot This bit is cleared by writing 0 in software However this bit cannot be cleared while the TRSTAT transmit receive status bit remains 1 Note Before reading the received data from the message slot be sure to clear the TRFIN transmit receive finished bit If the TRFIN transmit receive finished bit remains set after readout it means that new received data was...

Page 584: ...0 C0MSL14SID0 Address H 0080 11E0 CAN0 Message Slot 15 Standard ID0 C0MSL15SID0 Address H 0080 11F0 CAN1 Message Slot 0 Standard ID0 C1MSL0SID0 Address H 0080 1500 CAN1 Message Slot 1 Standard ID0 C1MSL1SID0 Address H 0080 1510 CAN1 Message Slot 2 Standard ID0 C1MSL2SID0 Address H 0080 1520 CAN1 Message Slot 3 Standard ID0 C1MSL3SID0 Address H 0080 1530 CAN1 Message Slot 4 Standard ID0 C1MSL4SID0 ...

Page 585: ...hen reset indeterminate D Bit Name Function R W 0 2 No functions assigned 0 3 7 SID0 SID4 Standard ID0 to standard ID4 Standard ID0 to standard ID4 These registers comprise a transmit frame receive frame memory space CAN MODULES 13 2 CAN Module Related Registers ...

Page 586: ... Address H 0080 11E1 CAN0 Message Slot 15 Standard ID1 C0MSL15SID1 Address H 0080 11F1 CAN1 Message Slot 0 Standard ID1 C1MSL0SID1 Address H 0080 1501 CAN1 Message Slot 1 Standard ID1 C1MSL1SID1 Address H 0080 1511 CAN1 Message Slot 2 Standard ID1 C1MSL2SID1 Address H 0080 1521 CAN1 Message Slot 3 Standard ID1 C1MSL3SID1 Address H 0080 1531 CAN1 Message Slot 4 Standard ID1 C1MSL4SID1 Address H 008...

Page 587: ...10 When reset indeterminate D Bit Name Function R W 8 9 No functions assigned 0 10 15 SID5 SID10 Standard ID5 to standard ID10 Standard ID5 to standard ID10 These registers comprise a transmit frame receive frame memory space CAN MODULES 13 2 CAN Module Related Registers ...

Page 588: ... Address H 0080 11E2 CAN0 Message Slot 15 Extended ID0 C0MSL15EID0 Address H 0080 11F2 CAN1 Message Slot 0 Extended ID0 C1MSL0EID0 Address H 0080 1502 CAN1 Message Slot 1 Extended ID0 C1MSL1EID0 Address H 0080 1512 CAN1 Message Slot 2 Extended ID0 C1MSL2EID0 Address H 0080 1522 CAN1 Message Slot 3 Extended ID0 C1MSL3EID0 Address H 0080 1532 CAN1 Message Slot 4 Extended ID0 C1MSL4EID0 Address H 008...

Page 589: ...3 Extended ID0 to extended ID3 Extended ID0 to extended ID3 These registers comprise a transmit frame receive frame memory space Note For receive slots whose frame type has been chosen to be the standard ID format the values written to their EID bits when storing the received data are indeterminate CAN MODULES 13 2 CAN Module Related Registers ...

Page 590: ... Address H 0080 11E3 CAN0 Message Slot 15 Extended ID1 C0MSL15EID1 Address H 0080 11F3 CAN1 Message Slot 0 Extended ID1 C1MSL0EID1 Address H 0080 1503 CAN1 Message Slot 1 Extended ID1 C1MSL1EID1 Address H 0080 1513 CAN1 Message Slot 2 Extended ID1 C1MSL2EID1 Address H 0080 1523 CAN1 Message Slot 3 Extended ID1 C1MSL3EID1 Address H 0080 1533 CAN1 Message Slot 4 Extended ID1 C1MSL4EID1 Address H 008...

Page 591: ...1 Extended ID4 to extended ID11 Extended ID4 to extended ID11 These registers comprise a transmit frame receive frame memory space Note For receive slots whose frame type has been chosen to be the standard ID format the values written to their EID bits when storing the received data are indeterminate CAN MODULES 13 2 CAN Module Related Registers ...

Page 592: ... Address H 0080 11E4 CAN0 Message Slot 15 Extended ID2 C0MSL15EID2 Address H 0080 11F4 CAN1 Message Slot 0 Extended ID2 C1MSL0EID2 Address H 0080 1504 CAN1 Message Slot 1 Extended ID2 C1MSL1EID2 Address H 0080 1514 CAN1 Message Slot 2 Extended ID2 C1MSL2EID2 Address H 0080 1524 CAN1 Message Slot 3 Extended ID2 C1MSL3EID2 Address H 0080 1534 CAN1 Message Slot 4 Extended ID2 C1MSL4EID2 Address H 008...

Page 593: ...12 EID17 Extended ID12 to extended ID17 Extended ID12 to extended ID17 These registers comprise a transmit frame receive frame memory space Note For receive slots whose frame type has been chosen to be the standard ID format the values written to their EID bits when storing the received data are indeterminate CAN MODULES 13 2 CAN Module Related Registers ...

Page 594: ...s H 0080 11E5 CAN0 Message Slot 15 Data Length Register C0MSL15DLC Address H 0080 11F5 CAN1 Message Slot 0 Data Length Register C1MSL0DLC Address H 0080 1505 CAN1 Message Slot 1 Data Length Register C1MSL1DLC Address H 0080 1515 CAN1 Message Slot 2 Data Length Register C1MSL2DLC Address H 0080 1525 CAN1 Message Slot 3 Data Length Register C1MSL3DLC Address H 0080 1535 CAN1 Message Slot 4 Data Leng...

Page 595: ...data length 0 0 0 1 1 byte 0 0 1 0 2 byte 0 0 1 1 3 byte 0 1 0 0 4 byte 0 1 0 1 5 byte 0 1 1 0 6 byte 0 1 1 1 7 byte 1 8 byte These registers comprise a transmit frame receive frame memory space When transmitting these registers are used to set the transmit data length When receiving the receive DLC is stored in these registers CAN MODULES 13 2 CAN Module Related Registers ...

Page 596: ...SL14DT0 Address H 0080 11E6 CAN0 Message Slot 15 Data 0 C0MSL15DT0 Address H 0080 11F6 CAN1 Message Slot 0 Data 0 C1MSL0DT0 Address H 0080 1506 CAN1 Message Slot 1 Data 0 C1MSL1DT0 Address H 0080 1516 CAN1 Message Slot 2 Data 0 C1MSL2DT0 Address H 0080 1526 CAN1 Message Slot 3 Data 0 C1MSL3DT0 Address H 0080 1536 CAN1 Message Slot 4 Data 0 C1MSL4DT0 Address H 0080 1546 CAN1 Message Slot 5 Data 0 C...

Page 597: ...me receive frame memory space Note 1 For receive slots if the data length DLC value 0 when storing a data frame an indeterminate value is written to the register Note 2 The first byte in the CAN frame data field corresponds to message slot n data 0 The data is transmitted and received beginning with the MSB side of the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 598: ...SL14DT1 Address H 0080 11E7 CAN0 Message Slot 15 Data 1 C0MSL15DT1 Address H 0080 11F7 CAN1 Message Slot 0 Data 1 C1MSL0DT1 Address H 0080 1507 CAN1 Message Slot 1 Data 1 C1MSL1DT1 Address H 0080 1517 CAN1 Message Slot 2 Data 1 C1MSL2DT1 Address H 0080 1527 CAN1 Message Slot 3 Data 1 C1MSL3DT1 Address H 0080 1537 CAN1 Message Slot 4 Data 1 C1MSL4DT1 Address H 0080 1547 CAN1 Message Slot 5 Data 1 C...

Page 599: ... W 8 15 CMSLnDT1 Message slot n data 1 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 1 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 600: ...SL14DT2 Address H 0080 11E8 CAN0 Message Slot 15 Data 2 C0MSL15DT2 Address H 0080 11F8 CAN1 Message Slot 0 Data 2 C1MSL0DT2 Address H 0080 1508 CAN1 Message Slot 1 Data 2 C1MSL1DT2 Address H 0080 1518 CAN1 Message Slot 2 Data 2 C1MSL2DT2 Address H 0080 1528 CAN1 Message Slot 3 Data 2 C1MSL3DT2 Address H 0080 1538 CAN1 Message Slot 4 Data 2 C1MSL4DT2 Address H 0080 1548 CAN1 Message Slot 5 Data 2 C...

Page 601: ...0 7 CMSLnDT2 Message slot n data 2 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 2 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 602: ...SL14DT3 Address H 0080 11E9 CAN0 Message Slot 15 Data 3 C0MSL15DT3 Address H 0080 11F9 CAN1 Message Slot 0 Data 3 C1MSL0DT3 Address H 0080 1509 CAN1 Message Slot 1 Data 3 C1MSL1DT3 Address H 0080 1519 CAN1 Message Slot 2 Data 3 C1MSL2DT3 Address H 0080 1529 CAN1 Message Slot 3 Data 3 C1MSL3DT3 Address H 0080 1539 CAN1 Message Slot 4 Data 3 C1MSL4DT3 Address H 0080 1549 CAN1 Message Slot 5 Data 3 C...

Page 603: ... W 8 15 CMSLnDT3 Message slot n data 3 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 3 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 604: ...SL14DT4 Address H 0080 11EA CAN0 Message Slot 15 Data 4 C0MSL15DT4 Address H 0080 11FA CAN1 Message Slot 0 Data 4 C1MSL0DT4 Address H 0080 150A CAN1 Message Slot 1 Data 4 C1MSL1DT4 Address H 0080 151A CAN1 Message Slot 2 Data 4 C1MSL2DT4 Address H 0080 152A CAN1 Message Slot 3 Data 4 C1MSL3DT4 Address H 0080 153A CAN1 Message Slot 4 Data 4 C1MSL4DT4 Address H 0080 154A CAN1 Message Slot 5 Data 4 C...

Page 605: ...0 7 CMSLnDT4 Message slot n data 4 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 4 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 606: ...SL14DT5 Address H 0080 11EB CAN0 Message Slot 15 Data 5 C0MSL15DT5 Address H 0080 11FB CAN1 Message Slot 0 Data 5 C1MSL0DT5 Address H 0080 150B CAN1 Message Slot 1 Data 5 C1MSL1DT5 Address H 0080 151B CAN1 Message Slot 2 Data 5 C1MSL2DT5 Address H 0080 152B CAN1 Message Slot 3 Data 5 C1MSL3DT5 Address H 0080 153B CAN1 Message Slot 4 Data 5 C1MSL4DT5 Address H 0080 154B CAN1 Message Slot 5 Data 5 C...

Page 607: ... W 8 15 CMSLnDT5 Message slot n data 5 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 5 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 608: ...SL14DT6 Address H 0080 11EC CAN0 Message Slot 15 Data 6 C0MSL15DT6 Address H 0080 11FC CAN1 Message Slot 0 Data 6 C1MSL0DT6 Address H 0080 150C CAN1 Message Slot 1 Data 6 C1MSL1DT6 Address H 0080 151C CAN1 Message Slot 2 Data 6 C1MSL2DT6 Address H 0080 152C CAN1 Message Slot 3 Data 6 C1MSL3DT6 Address H 0080 153C CAN1 Message Slot 4 Data 6 C1MSL4DT6 Address H 0080 154C CAN1 Message Slot 5 Data 6 C...

Page 609: ...0 7 CMSLnDT6 Message slot n data 6 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 6 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 610: ...SL14DT7 Address H 0080 11ED CAN0 Message Slot 15 Data 7 C0MSL15DT7 Address H 0080 11FD CAN1 Message Slot 0 Data 7 C1MSL0DT7 Address H 0080 150D CAN1 Message Slot 1 Data 7 C1MSL1DT7 Address H 0080 151D CAN1 Message Slot 2 Data 7 C1MSL2DT7 Address H 0080 152D CAN1 Message Slot 3 Data 7 C1MSL3DT7 Address H 0080 153D CAN1 Message Slot 4 Data 7 C1MSL4DT7 Address H 0080 154D CAN1 Message Slot 5 Data 7 C...

Page 611: ... W 0 7 CMSLnDT7 Message slot n data 7 n 0 15 These registers comprise a transmit frame receive frame memory space Note For receive slots if the data length DLC value 7 or less when storing a data frame an indeterminate value is written to the register CAN MODULES 13 2 CAN Module Related Registers ...

Page 612: ...TSP Address H 0080 11EE CAN0 Message Slot 15 Time stamp C0MSL15TSP Address H 0080 11FE CAN1 Message Slot 0 Time stamp C1MSL0TSP Address H 0080 150E CAN1 Message Slot 1 Time stamp C1MSL1TSP Address H 0080 151E CAN1 Message Slot 2 Time stamp C1MSL2TSP Address H 0080 152E CAN1 Message Slot 3 Time stamp C1MSL3TSP Address H 0080 153E CAN1 Message Slot 4 Time stamp C1MSL4TSP Address H 0080 154E CAN1 Mes...

Page 613: ...t Name Function R W 0 15 CMSLnTSP Message slot n time stamp n 0 15 These registers comprise a transmit frame receive frame memory space When transmission reception is completed the value of the CAN Time stamp Count Register is stored in this register CAN MODULES 13 2 CAN Module Related Registers ...

Page 614: ...ce SOF Arbitration field Control field Data field CRC field ACK field EOF 11 1 6 0 64 16 2 7 11 1 1 1 18 6 0 64 16 2 7 SOF Arbitration field Control field CRC field ACK field EOF 11 1 6 16 2 7 11 1 1 1 18 6 16 2 7 Data frame Remote frame Standard format Standard format Extended format The digit in each field denotes the number of bits Extended format 1 1 1 1 Figure 13 3 1 CAN Protocol Frames 1 CAN...

Page 615: ...r overload flag Error frame Overload frame Interfame space Intermission Bus idle SOF of the next frame For error active state 3 0 Suspend transmission For error passive state 3 8 0 SOF of the next frame Bus idle Intermission The digit in each field denotes the number of bits 1 1 Figure 13 3 2 CAN Protocol Frames 2 CAN MODULES 13 3 CAN Protocol ...

Page 616: ...ate is assumed when almost no errors have occurred When an error is detected the CAN Controller sends an active error flag The CAN Controller is in this state immediately after initialization 2 Error passive state This state is assumed when many errors have occurred When an error is detected the CAN Controller sends a passive error flag 3 Bus off state This state is assumed when a large number of ...

Page 617: ... or CAN bus off interrupts or CAN slot interrupt enable the desired interrupt requests by setting the corresponding mask bits to 1 4 Setting the bit timing and sampling times Using the CAN Configuration Register and CAN Baud Rate Prescaler set the bit timing and the number of times the CAN bus is sampled Setting the bit timing Determine the period Tq that constitutes the basis of bit timing as wel...

Page 618: ... the Message Control Registers 14 and 15 to receive a data frame H 40 7 Setting CAN module operation mode Using the CAN Control Register CANCNT select operation mode of the CAN module BasicCAN or loopback mode and the clock source for the time stamp counter 8 Releasing the CAN module from reset After initial settings in 1 through 7 above clear the CAN Control Register CANCNT s forcible reset FRST ...

Page 619: ...CAN error interrupt mask registers Enable disable CAN bus error interrupt Enable disable CAN error passive interrupt Enable disable CAN bus off interrupt Settings of CAN slot interrupt mask registers Enable disable transmit receive complete interrupt for each slot Settings for loopback mode Settings for BasicCAN mode Set CAN extended ID register Set ID in message slots 14 and 15 Set message slot c...

Page 620: ...gnal on the CRX pin with a Tq clock period that is the base clock The sampled signal is assumed to be the CAN bus value Operation timing is shown below 1Tq Timing delay of maximum 1 Tq Internal Tq signal CRX pin Internal CRX signal Figure 13 4 3 Operation Timing CAN MODULES 13 4 Initialization of the CAN Module ...

Page 621: ...d and remains idle If this bit 1 it means that the CAN module is accessing the message slot Therefore wait until the bit is cleared to 0 3 Setting transmit data Set the transmit ID and transmit data in the message slot 4 Setting the extended ID register Set the extended ID register s corresponding bit to 0 when the data needs to be transmitted as a standard frame or 1 when the data needs to be tra...

Page 622: ... extended ID register Set CAN message slot control register Settings completed Write H 00 Standard ID or extended ID Write H 80 transmit request Read CAN message slot control register TRSTAT bit 0 YES NO Verify that transmission is idle Figure 13 5 1 Procedure for Transmitting a Data Frame CAN MODULES 13 5 Transmitting Data Frames ...

Page 623: ...ses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission it clears the CAN Message Slot Control Register s TRSTAT transmit receive status bit to 0 If the transmit abort function for the slot has been enabled the transmit abort request is accepted and the message slot is freed allowing for write to the slot 4 Completing data frame transmission When the CAN module finis...

Page 624: ...ame Transmission 13 5 3 Transmit Abort Function The transmit abort function is used to cancel a transmit request that has once been set This is accomplished by writing H 0F to the CAN Message Slot Control Register for the slot whose transmit request is to be canceled When transmit abort is accepted the CAN module clears the CAN Message Slot Control Register TRSTAT transmit receive status bit to 0 ...

Page 625: ...mit receive status bit to see that reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot Therefore wait until the bit is cleared to 0 3 Setting the ID Set the ID desired to be received in the message slot 4 Setting the extended ID register Set the extended ID register s corresponding bit to 0 when it is desired to receive a standard frame o...

Page 626: ...extended ID register Set CAN message slot control register Settings completed Write H 00 Standard ID or extended ID Write H 40 receive request Read CAN message slot control register TRSTAT bit 0 YES NO Verify that reception is idle Figure 13 6 1 Procedure for Receiving a Data Frame CAN MODULES 13 6 Receiving Data Frames ...

Page 627: ... sets the CAN Message Slot Control Register s TRSTAT transmit receive status and TRFIN transmit receive finished bits to 1 and at the same time writes the received data to the message slot If the TRFIN transmit receive finished bit is already 1 at this time the ML message lost bit also is set to 1 indicating that the message slot has been overwritten The message slot has all of its ID and DLC fiel...

Page 628: ... Finish storing received data Clear receive request Clear receive request B 0000 0111 Finish storing received data Clear receive request Clear receive request B 0000 0101 Finish storing received data Clear receive request Clear receive request Store received data Wait for received data Wait for received data Finish storing received data Finish storing received data CPU read CPU read Figure 13 6 2 ...

Page 629: ...he slot needs to be checked for message lost by inspecting the ML bit clear the TRFIN bit by writing H 4E to the register Note 2 If the TRFIN bit is cleared by writing H 4E H 40 or H 00 to the register it is possible that new data will be stored in the slot while reading the received data from it 2 Reading out from the message slot Read the received data from the message slot 3 Checking the TRFIN ...

Page 630: ...RFIN bit to 0 Read data from message slot Finished reading out received data Read CAN message slot control register TRFIN bit 0 YES NO Write H 4E H 40 or H 00 Figure 13 6 3 Procedure for Reading Out Received Data CAN MODULES 13 6 Receiving Data Frames ...

Page 631: ...e status bit to see that transmission has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot Therefore wait until the bit is cleared to 0 3 Setting the transmit ID Set the ID to be transmitted in the message slot 4 Setting the extended ID register Set the extended ID register s corresponding bit to 0 when it needs to be transmitted as a standard frame...

Page 632: ... ID register Set CAN message slot control register Settings completed Write H 00 Standard ID or extended ID Write H A0 transmit request remote Read CAN message slot control register TRSTAT bit 0 YES NO Verify that transmission is idle Figure 13 7 1 Procedure for Transmitting a Remote Frame CAN MODULES 13 7 Transmitting Remote Frames ...

Page 633: ...N bus arbitration or a CAN bus error occurs If the CAN module loses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission it clears the CAN Message Slot Control Register s TRSTAT transmit receive status bit to 0 If the transmit abort function for the slot has been enabled the transmit abort request is accepted and the message slot is freed allowing for write to the slo...

Page 634: ...lot If the TRFIN transmit receive finished bit is already 1 at this time the ML message lost bit also is set to 1 indicating that the message slot has been overwritten The message slot has all of its ID and DLC fields overwritten with an indeterminate value written to its unused area e g the extended ID field when set for standard frame or an unused data field In addition the time stamp count valu...

Page 635: ...eived data Clear receive request Finish storing the received data B 1010 0001 Store the received data B 1010 0111 B 0000 0111 B 0000 0101 Finish storing the received data Finish storing the received data Store the received data Finish sending a remote frame B 1010 0000 Wait for the data to receive B 1010 1011 B 0000 1011 Clear transmit request B 0000 0001 Finish storing the received data Finish st...

Page 636: ...E to the register Note 2 If the TRFIN bit is cleared by writing H AE or H 00 to the register it is possible that new data will be stored in the slot while reading the received data from it Note 3 The received data frame cannot be read out if the TRFIN bit is cleared by writing H A0 to the register In this case the slot is set to transmit a remote frame 2 Reading out from the message slot Read the ...

Page 637: ...data from message slot Finished reading out received data Read CAN message slot control register TRFIN bit 0 YES NO Write H AE or H 00 Figure 13 7 3 Procedure for Reading Out Received Data When Set for Remote Frame Transmission CAN MODULES 13 7 Transmitting Remote Frames ...

Page 638: ...be received in the message slot 4 Setting the extended ID register Set the extended ID register s corresponding bit to 0 when it is desired to receive a standard frame or 1 when it is desired to receive an extension frame 5 Setting the CAN Message Slot Control Register When remote frame reception needs to be automatically answered data frame transmission Set the CAN Message Slot Control Register R...

Page 639: ... register Settings completed Write H 00 Standard ID or extended ID Write H 60 receive request remote automatic answering enabled Write H 70 receive request remote automatic answering disabled Read CAN message slot control register TRSTAT bit 0 YES NO Verify that reception is idle Figure 13 8 1 Procedure for Receiving a Remote Frame CAN MODULES 13 8 Receiving Remove Frames ...

Page 640: ...same type 3 When the receive conditions are met When the receive conditions described in 2 above are met the CAN module sets the CAN Message Slot Control Register s TRSTAT transmit receive status and TRFIN transmit receive finished bits to 1 and at the same time writes the received data to the message slot In addition the time stamp count value at the time of message reception is written along wit...

Page 641: ...ule starts transmitting the data frame from the slot after setting its corresponding CAN Message Slot Control Register s TRSTAT transmit receive status bit to 1 If failed in CAN bus arbitration or a CAN bus error occurs If the CAN module loses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission it clears the CAN Message Slot Control Register s TRSTAT transmit receive...

Page 642: ... frame Clear receive request Finish transmitting data frame Finish transmitting data frame Transmit data frame Finish storing the received data Store the received data B 0111 1010 Store the received data B 0111 0000 Finish storing the received data Finish storing the received data Clear receive request Store the received data Clear receive request Write H 60 automatic answering enabled Write H 70 ...

Page 643: ...14 1 Outline of the Real Time Debugger RTD 14 2 Pin Function of the RTD 14 3 Functional Description of the RTD 14 4 Typical Connection with the Host CHAPTER 14 CHAPTER 14 REAL TIME DEBUGGER RTD ...

Page 644: ...ansfer clock Generated by external host RAM access area Entire area of internal RAM controlled by A16 A29 Transmit receive data length 32 bits fixed Bit transfer sequence LSB first Maximum transfer rate 2 Mbits second Input output pins 4 lines RTDTXD RTDRXD RTDACK RTDCLK Number of commands Following five functions Monitors continuously Outputs real time RAM contents Forcibly rewrites RAM contents ...

Page 645: ... pulse synchronously with the beginning clock edge of the output data word The width of the low level pulse thus output indicates the type of instruction data that the RTD received 1 clock period VER continuous monitor command 1 clock period VEI RTD interrupt request command 2 clock periods RDR real time RAM content output command 3 clock periods WRR RAM content forcible rewrite command or the dat...

Page 646: ...uest 0 0 1 0 RDR ReaD RAM Real time RAM content output 0 0 1 1 WRR WRite RAM RAM content forcibly rewrite with verify 1 1 1 1 RCV ReCoVer Recover from runaway Note 2 Note 3 0 0 0 1 System reserved use inhibited Note 1 Note 1 Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command is handled as Don t Care bit Bits 16 18 are effective for the command ...

Page 647: ...an only be specified on 32 bit word boundaries The two low order address bits specified by a command are ignored Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device Figure 14 3 1 RDR Command Data Format Figure 14 3 2 Operation of the RDR Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be s...

Page 648: ...1 0 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD Figure 14 3 3 Read Data Transfer Format Note The read data is transferred LSB first 31 D31 1 D0 0 D30 30 D1 Read data Note RTDTXD MSB side LSB side ...

Page 649: ... bits specified by a command are ignored Note also that data are written to the internal RAM in units of 32 bits The external host should transmit the command and address in the first frame and then the write data in the second frame The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data Figure 14 3 4 WRR Command Data Format Note 1 X Don t C...

Page 650: ...ame address immediately after writing to the internal RAM this helps to verify the data written to the internal RAM The read data is output at the timing shown below Note An Specified address D An Data at specified address An D A1 Verify value after write WRR A1 A1 Write data RTDCLK RTDRXD RTDTXD RTDACK WRR A2 A2 Write data D A1 Read value before write 32 clock periods 32 clock periods 32 clock pe...

Page 651: ... Monitor Command Data Format Figure 14 3 7 Operation of the VER Continuous Monitor Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Note 1 WRR command can also be used Note 2 An Specified address D An Data at specified address An 31 X 0 0 0 0 19 18 17 16 X 15 0 X 20 RTDRXD MSB side LSB side X Command VER RDR A1 VER RTDCLK RTDRXD RTDTXD R...

Page 652: ...14 3 9 Operation of the VEI Interrupt Request Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Note 1 WRR command can also be used Note 2 An Specified address D An Data at specified address An 31 X 0 1 1 0 19 18 17 16 X 15 0 X 20 RTDRXD MSB side LSB side X VEI interrupt request generation command Note Note RTD interrupt RDR A1 VEI RTDCLK...

Page 653: ... 14 3 10 RCV Command Data Format Note All of 32 data bits are 1 s The RCV command must always be issued twice in succession Note The next command following the RCV command must have its bits 20 31 all set to 1 Figure 14 3 11 Operation of the RCV Command 31 1 1 1 1 1 19 18 17 16 1 15 0 1 20 RTDRXD MSB side LSB side 1 Command RCV Note Note RCV RCV command stored here RTDCLK RTDRXD RTDTXD RTDACK RCV ...

Page 654: ...se the internal RAM area is located in a 48 KB area ranging from H 0080 4000 to H 0080 FFFF you can set low order 16 bit addresses of that area However access to any locations other than the area where the RAM resides is inhibited Note also that two least significant address bits A31 and A30 are always 0 s because data are read and written to the internal RAM in a fixed length of 32 bits SFR 16KB ...

Page 655: ...atus of the RTD related output pins after a system reset are shown below Table 14 3 2 RTD Pin State after System Reset Pin Name State RTDACK High level output RTDTXD High level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK Don t Care RDR A1 RTDCLK RTDRXD RTDTXD RTDACK RESET System reset...

Page 656: ...e the RTDACK level is checked between transfer frames 14 4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data The clock for synchronous is generated by the host An example for connecting the RTD and host is shown below RTDRXD RTDTXD RTDCLK RTDACK M32R E Host microprocessor RXD TXD SCLK PORT Note ...

Page 657: ...hen issuing the VER command the RTDACK signal goes low for only one clock period Therefore after sending 32 bits in one frame turn off RTDCLK output and check whether RTDACK is low If RTDACK is low you know that the RTD is communicating normally If you want to identify the type of transmitted command by the width of RTDACK use the 32171 s internal measurement timer to count RTDCLK pulses while RTD...

Page 658: ...14 14 16 Rev 1 0 REAL TIME DEBUGGER RTD 14 4 Typical Connection with the Host This is a blank page ...

Page 659: ...15 1 Outline of the PD Module 15 2 PD Module Related Regis ters 15 3 Initialization for PD Sensor Support 15 4 Precautions on Using the PD Module CHAPTER 15 CHAPTER 15 PD MODULE ...

Page 660: ...up counter TEPiP 16 bit input related timer up counter TEPiM One of two modes can be selected in software i 0 1 Event count mode Counts the number of pulses entered from an external pin PD sensor support mode Operates corresponding to input from PD sensors PD calculation function Performs various calculations corresponding to input from PD sensors and stores the result in a register 2 channels Tab...

Page 661: ...Channels 1 9 PD0_ABD PITCH compare match note PD1_ABD compare match Channels 1 9 PD1_ABD PITCH compare match note TIN0A input detection Channels 0 TIN0B input detection Channels 2 TIN1A input detection Channels 5 TIN1B input detection Channels 7 Note Selected using the DMA Transfer Request Source Select Register DMAREQSL PD MODULE 15 1 Outline of the PD Module ...

Page 662: ... Position Calculation Circuit Pnew0 Pold0 Mnew0 Mold0 TIN0AS TIN0BS TIN1AS TIN1BS Internal peripheral clock BCLK IRQ31 IRQ31 IRQ31 IRQ31 IRQ31 IRQ2 IRQ31 IRQ2 DRQ26 DRQ21 DRQ22 DRQ23 DRQ24 DRQ25 Pnew1 Pold1 Mnew1 Mold1 R 2R DA0 DPRAM 256 bytes Cap Cap Cap Cap clk CLR Cap Cap Cap Cap 8 16 Internal peripheral clock BCLK Internal peripheral clock BCLK Internal peripheral clock BCLK DA0 Converter Figu...

Page 663: ...rupt Status Register TINPDIST TPD Control Register TPDCR TPD Measure Register 1 TPDMR1 TPD Measure Register 2 TPDMR2 TPD Measure Register 3 TPDMR3 TPD Measure Register 4 TPDMR4 TPD Measure Register 5 TPDMR5 TPD Measure Register 6 TPDMR6 TPD Measure Register 7 TPDMR7 H 0080 1848 H 0080 1870 H 0080 1868 PD Calculation Interrupt Status Register PDIST TEP0P Control Register TEP0PCR TEP0M Control Regis...

Page 664: ...ITCHLT1 MRLT1 Register MRTL1 PNEWLT1 Register PNEWLT1 POLDT1 Register POLDLT1 MNEWLT1 Register MNEWLT1 MOLDLT1 Register MOLDLT1 PSUBLT1 Register PSUBLT1 MSUBLT1 Register MSUBLT1 RSUMLT1 Register RSUMLT1 H 0080 18AE H 0080 18BA TEP1P Counter TEP1PCT TEP1M Counter TEP1MCT PD1 Data Updating Disable Event Select Register PDNSEL1R PD1 Data Updating Control Register PDNCNT1R ABD1 Mask Register ABD1MK S ...

Page 665: ...hen reset H 00 D Bit Name Function R W 0 7 PRSA Sets the prescaler s divide ratio The Prescaler A generates a count clock for the D A converter s parameter table address counter DACNT from the internal peripheral clock 20 0 MHz when the CPU clock 40 MHz by dividing it by an appropriate value When the value of Prescaler Register A is rewritten while the DACNT is operating the prescaler starts opera...

Page 666: ...Hz when the CPU clock 40 MHz by dividing it by an appropriate value When the value of Prescaler Register B is rewritten while the DACNT is operating the prescaler starts operating with the new value simultaneously when the prescaler underflows The PRSB starts generating a clock after the TPD Control Register TPDEN bit is set to 1 TPD count period f PRSB 1 Note When using the TPD Counter TPDCT alon...

Page 667: ...ividing it by an appropriate value When the value of Prescaler Register 0C or 1C is rewritten while the TEPiP TEPiM counter is operating the prescaler starts operating with the new value simultaneously when the prescaler underflows Note 1 The PRS0C PRS1C starts generating a clock after the TEP0P TEM1P Control Register TEP0PEN TEM1PEN bit is set to 1 Note 2 When using the TEPiP TEPiM counters along...

Page 668: ...a is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed Simply because data is written to the DACNT Reload Register does not mean that the DACNT Counter is loaded with the data D0 1 2 3 4 5 6 D7 DACNTRL When reset H 00 D Bit Name Function R W 0 7 DACNTRL 8 bit reload register value PD MODULE 15 2 PD Module Related Registers ...

Page 669: ...ing edge 10 Falling edge 11 Both edges Use the TIN Input Processing Control Register to select the active edge of the TIN input signal at which to generate the measure clear and count source signals for each timer 1 Input has no effect Input on the TIN pin has no effect with no signals generated for each timer 2 Rising edge Signals for each timer are generated upon detecting the rising edge of the...

Page 670: ...12 Rev 1 0 TIN Count clock Figure 15 2 3 Rising Edge Detection Figure 15 2 4 Falling Edge Detection Figure 15 2 5 Both Edge Detection PD MODULE 15 2 PD Module Related Registers TIN Count clock TIN Count clock ...

Page 671: ... 1 Enables interrupt 2 TIN0BEIM Note 3 TIN0AEIM Note 4 TIN1BIM 5 TIN1AIM 6 TIN0BIM 7 TIN0AIM This register controls disabling enabling of interrupts for the interrupt requests generated by each TIN input processing circuit Setting any bit to 1 in this register enables the corresponding TIN input interrupt request Note The D0 D3 bits are provided for use with PD sensors When not using the module al...

Page 672: ...has no effect the bit retains the value it had before writing This register indicates whether there is an interrupt request for TIN input from any pin 1 TIN input detection error interrupt request bits D8 D9 D10 D11 These bits indicate interrupt requests from PD sensors Detailed description being written now 2 TIN input detection interrupt request bits D12 D13 D14 D15 These bits are set to 1 when ...

Page 673: ...F F b3 b12 TIN1BIS F F TIN1BIM F F b4 Level 8 source inputs TINPD1CR H 0080 1804 TINPD2CR H 0080 1805 TIN1BEedge TINAE1edge TIN0Bedge TIN0Aedge TIN1Bedge b13 TIN1AIS F F TIN1AIM F F b5 TIN1Aedge b14 TIN0BIS F F TIN0BIM F F b6 TIN0Bedge b15 TIN0AIS F F TIN0AIM F F b7 TIN0Aedge Figure 15 2 6 Block Diagram of the TIN Interrupt Circuit PD MODULE 15 2 PD Module Related Registers ...

Page 674: ...count enable 1 Enables count This register controls enabling disabling of the DACNT Counter to or not to count When the DACNTEN bit is set to 1 the DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA Setting the DACNTEN bit to 0 disables the DACNT Counter so that it stops counting with the count value retained PD MODULE 15 2 PD ...

Page 675: ...sure the DACNT Control Register DACNTCR s DACNTEN bit and this register s TPDEN bit are set to 1 simultaneously by accessing the registers in halfword 2 TPDEN bit D15 When this bit is set to 1 the TPD Counter starts counting up from its set value synchronously with the clock period that has been set with the PRSB Setting this bit to 0 disables the TPD Counter so that it stops counting with the cou...

Page 676: ...ad Register and restarts counting down from the newly set value The diagram below shows operation of the DACNT Counter when the DACNT Counter and the DACNT Reload Register respectively have the values H A0 and H B0 set as their initial values D0 1 2 3 4 5 6 D7 DACNT When reset H 0000 D Bit Name Function R W 0 7 DACNT 8 bit counter value Figure 15 2 7 Example of DACNT Counter Operation PD MODULE 15...

Page 677: ...n each mode 1 Normal mode The TPD Counter operates as a free running up counter Shown below is an example of count operation of the TPD Counter when it is enabled after setting H 6000 in it as its initial value D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TPDCT When reset H 0000 D Bit Name Function R W 0 15 TPDCT 16 bit counter value Figure 15 2 8 Typical Operation of the TPD Counter in Normal Mode 2 P...

Page 678: ...it Name Function R W 0 15 TPDMR0 7 16 bit measured value The TPD Measure Registers 0 2 4 and 6 are used to capture the count value so that when an event input on any TIN pin is detected the count value at that point in time is latched into the corresponding measure register The TPD Measure Registers 1 3 5 and 7 are used to capture the values of the TPD Measure Registers 0 2 4 and 6 so that when an...

Page 679: ... event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs TIN1A event occurs TIN1B event occurs TIN0A event occurs TIN0B event occurs TPDMR0 TPDMR1 TPDMR2 TPDMR3 TPDMR4 TPDMR5 TPDMR6 TPDMR7 Enable bit H FFFF H 0000 TPD counter H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 4000 H 0000 H 6000 H 0000 H 8000 H 0000 H A000 H 0000 H A000 H 8000 H 6000 H A000 H 8000 H 4000 H 6000...

Page 680: ...on interrupts When any bit in this register is set to 1 the corresponding interrupt of the PD Interrupt Status Register is enabled D0 1 2 3 4 5 6 D7 APCM1IM SER1IM PCM1IM ACM1IM APCM0IM SER0IM PCM0IM ACM0IM When reset H 00 D Bit Name Function R W 0 APCM1IM 0 Disables interrupt 1 SER1IM 1 Enables interrupt 2 PCM1IM 3 ACM1IM 4 APCM0IM 5 SER0IM 6 PCM0IM 7 ACM0IM PD MODULE 15 2 PD Module Related Regis...

Page 681: ...of this manual where the PITCHi Compare Registers are discussed This bit is cleared by writing 0 4 ACMiIS This bit is set to 1 when the ABDi value and the ABDi Compare Register s set value matched For details about the ABD compare operation see the section of this manual where the ABDi Compare Registers are discussed This bit is cleared by writing 0 Note The mask function may be used for determini...

Page 682: ... b3 b12 APCM0IS F F APCM0IM F F b4 Level 8 source inputs PDICR H 0080 1830 PDIST H 0080 1831 APCM1edge SER1edge PCM1edge ACM1edge APCM0edge b13 SER0IS F F SER0IM F F b5 b14 PCM0IS F F PCM0IM F F b6 b15 ACM0IS F F ACM0IM F F b7 SER0edge PCM0edge ACM0edge Figure 15 2 10 Block Diagram of PD Circuit Calculation Complete Interrupt PD MODULE 15 2 PD Module Related Registers ...

Page 683: ...tion detection 2 b01 11 bit accuracy accuracy 2 b10 12 bit accuracy 2 b11 Use inhibited PD MODULE 15 2 PD Module Related Registers When fcpu 40 MHz Sine wave D A conversion address D A conversion data table Base count range Resolution count frequency usage range PRS H 00 19 5KHz 5 0MHz PRS H 03 H 00 H FF 256 data H 0000 H 03FF 10bits 9 77KHz 2 5MHz PRS H 07 H 00 H FF 256 data H 0000 H 07FF 11bits ...

Page 684: ...vent count mode in which the TEPiP Counter operates as an event counter up counter counting events on the corresponding TIN input pin Setting this bit to 1 selects PD sensor support mode in which the TEPiP Counter operates corresponding to input from PD sensors Note Rewriting this bit while the TEPiP Counter is operating is inhibited 2 TEPiPEN bit Setting this bit to 1 enables the TEPiP Counter fo...

Page 685: ...t mode in which the TEPiM Counter operates as an event counter up counter counting events on the corresponding TIN input pin Setting this bit to 1 selects PD sensor support mode in which the TEPiM Counter operates corresponding to input from PD sensors Note Rewriting this bit while the TEPiM Counter is operating is inhibited 2 TEPiMEN bit Setting this bit to 1 enables the TEPiM Counter for countin...

Page 686: ...e TEPiP TEPiM Counters have two operations that can be selected with the TEPiP TEPiM Control Register TEPiPEN TEPiMEN bit A typical operation of the TEPiP TEPiM Counters in each mode is shown PD MODULE 15 2 PD Module Related Registers 15 2 15 TEP Counters TEP0P Counter TEP0PCT Address H 0080 1844 TEP1P Counter TEP1PCT Address H 0080 1884 TEP0M Counter TEP0MCT Address H 0080 1846 TEP1M Counter TEP1...

Page 687: ...e 2 PD sensor support mode Detailed description being written now PD MODULE 15 2 PD Module Related Registers A B A 1 B 1 C D C 1 TIN0A event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs TIN0A event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs D 1 A 2 B 2 C 3 D 4 TEP0PEN TEP0MEN TEP1PEN TEP1MEN TEP0P TEP0M TEP1P TEP1M ...

Page 688: ...red can have its data updated under software control This register is used to select an event that disables updating of said register data Consequently the data stored in the register at the time the selected event occurred can be retained until updating is reenabled Updating of the register data is enabled by setting the PDi Data Updating Control Register directly in software 1 No selection PDNSE...

Page 689: ...This is always possible regardless of how the PDi Data Updating Disable Event Select Register is set When TOM0_6 timer event has been selected with the PDi Data Updating Disable Event Select Register the bits in this register are set to 1 by occurrence of TOM0_6 timer event If this timer event occurs at the same time the PDNCNTi bits are cleared to 0 in software the former has priority the bit is ...

Page 690: ...ts corresponding bit of the comparison result is handled as Don t care The diagram below shows the relationship of bits between the ABDi Mask Register and the ABDiLT Register and ABDi Compare Register Figure 15 2 12 Data Formats when Comparing Register Values to Determine Matching PD MODULE 15 2 PD Module Related Registers D0 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D1 D13 D14 D15 D0 D2 D3 D4 D5 D6 D7 ...

Page 691: ...e Note SNEW1MK b 00000000 SS 256 SS 257 Select S error b 10000000 SS 128 SS 129 detection range b 11000000 SS 64 SS 65 b 11100000 SS 32 SS 33 b 11110000 SS 16 SS 17 b 11111000 SS 8 SS 9 b 11111100 SS 4 SS 5 b 11111110 SS 2 SS 3 b 11111111 SS 1 SS 2 Note The detection ranges shown here assume the SSLT Register D11 bit is the least significant bit These registers are used to set the S error detectio...

Page 692: ...et At this time the low order bits of the comparison result can be masked out as Don t care bits by using the ABDi Mask Register Note 1 When setting the ABDiCM Register always be sure to set the bits in this register to 0 that correspond to those which are set to 0 in the ABDi Mask Register Note 2 ABD compare match processing is always performed based on the latest measured value regardless of how...

Page 693: ...nter Register value and when they match a PITCH compare match interrupt request is set Note PITCH compare match processing is always performed based on the latest measured value regardless of how the PDi Data Updating Control Register is set D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 PIT0CM PIT1CM When reset H 0000 D Bit Name Function R W 0 15 PIT0CM PIT1CM 16 bit compare value PD MODULE 15 2 PD Modu...

Page 694: ...gister is used to store the value equivalent to a change of position Note To read data from this register access it as signed halfword data D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 FD0 FD1 When reset H 0000 D Bit Name Function R W 0 11 FD0 FD1 12 bit FD value 12 15 No functions assigned 0 PD MODULE 15 2 PD Module Related Registers ...

Page 695: ... the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction The PITCH counter value is stored in this register PITCH Counter The PITCHi Counter is an up down counter whose count direction is determined by comparing the two high order bits of the latest and the previous ABDiLTD Register values The following shows how the up down direction actually is determined PD MODULE 1...

Page 696: ... when 11 bit accuracy is selected or the D10 D15 bits when 10 bit accuracy is selected that are always 0 when read out D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 ABD0 ABD1 When reset H 0000 D Bit Name Function R W 0 15 ABD0 ABD1 12 bit ABD value Note 1 This register must always be accessed in halfwords Note 2 When performing predictive calculations access the PITCHLT and ABDLT Registers wordwise to r...

Page 697: ...calculated using the value in this register by the equation below I ABDLT ABDLT FDLT RSUMLT T Note 1 T H 1000 Note 2 Access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 RSUM0 RSUM1 When reset H 0000 D Bit Name Function R W 0 15 RSUM0 RSUM1 16 bit correction factor Note This register must always be accessed as signed ha...

Page 698: ... latest value of the SSLT data used for S error judgment The four low order bits are 0 when read out D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 SSLT0 SSLT1 When reset H 0000 D Bit Name Function R W 0 11 SSLT0 SSLT1 12 bit SSLT value 12 15 No functions assigned 0 Note This register must always be accessed in halfwords PD MODULE 15 2 PD Module Related Registers ...

Page 699: ...the Prescalers A and B Use the Prescaler A to set the address count period for the DA0 Data Register The value to be set in the Prescaler A depends on the selected accuracy of position detection so set the appropriate value as shown below When 10 bit accuracy is selected H 03 When 11 bit accuracy is selected H 07 When 12 bit accuracy is selected H 0F For each of these settings the sine wave period...

Page 700: ...ch set the compare value in these registers Setting the PITCH0 and PITCH1 Compare Registers When using PITCH compare match set the compare value in these registers 8 Setting the Interrupt Controller When using PD interrupts set the priority level of each interrupt 9 Setting the TIN and PD Interrupt Control Registers Use the TIN Interrupt Control Register to enable or disable TIN related interrupts...

Page 701: ...t Control Registers Set TIN Input Processing Control Register Set Input output Port Operation Mode Register Initialization complete Set DACNT and TPD Control Registers Set TEP0P TEP0M TEP1P and TEP1M Control Registers Parameter Table Data Set table data necessary to generate sine wave DA Control Register Select continuous mode for DA0 and enable its output Select from 10 11 or 12 bit resolutions P...

Page 702: ...er disabling data updating it is possible to read out the calculation result based on the latest event input by altering register settings back again In no case will event inputs pass undetected even when data updating is disabled When performing predictive calculations be sure to disable updating of PD data before reading out the FDLT PITCHLT ABDLT and RSUMLT Registers PD MODULE 15 4 Precautions ...

Page 703: ...16 1 Outline of the D A Converters 16 2 D A Converter Related Registers 16 3 Functional Description of the D A Converters CHAPTER 16 CHAPTER 16 D A CONVERTERS ...

Page 704: ...inuous mode is available for only the D A0 Converter and not for the D A1 Converter Table 16 1 1 outlines the D A Converters Figures 16 1 1 and 16 1 2 show block diagrams of the D A Converters Figure 16 1 3 shows an equivalent circuit of the D A Converters D A CONVERTERS 16 1 Outline of the D A Converters Table 16 1 1 Outline of the D A Converters Item Content Analog output 2 channels D A conversi...

Page 705: ...Single mode Continuous mode 256 bytes DA Counter DACNT PRSA AD1IN4 8 8 PD Module TPD reset BCLK 8 8 8 Figure 16 1 1 Block Diagram of the D A0 Converter Figure 16 1 2 Block Diagram of the D A1 Converter D A CONVERTERS 16 1 Outline of the D A Converters D A1 Conversion Register DA1ON DA1 AD1IN5 Internal Data Bus AD1IN5 8 8 8 bit R 2R Resistor Ladder ...

Page 706: ...it is the same as for the D A1 Converter Note 3 When not using the D A converters set the D A Control Register s analog output enable bit DA0ON DA1ON to 0 and write the data H 00 to the D A Conversion Register DA0CNV DA1CNV to prevent current from flowing into the R 2R resistors This helps to minimize the unwanted current consumption Figure 16 1 3 Equivalent Circuit Diagram of the D A0 Converter D...

Page 707: ...ster 28 DA0DT28 D A0 Data Register 29 DA0DT29 D A0 Data Register 30 DA0DT30 D A0 Data Register 31 DA0DT31 D A0 Data Register 32 DA0DT32 D A0 Data Register 33 DA0DT33 D A0 Data Register 34 DA0DT34 D A0 Data Register 35 DA0DT35 D A0 Data Register 36 DA0DT36 D A0 Data Register 37 DA0DT37 D A0 Data Register 38 DA0DT38 D A0 Data Register 39 DA0DT39 D A0 Data Register 40 DA0DT40 D A0 Data Register 41 DA...

Page 708: ...a Register 122 DA0DT122 D A0 Data Register 123 DA0DT123 D A0 Data Register 124 DA0DT124 D A0 Data Register 125 DA0DT125 D A0 Data Register 126 DA0DT126 D A0 Data Register 127 DA0DT127 D A0 Data Register 128 DA0DT128 D A0 Data Register 129 DA0DT129 D A0 Data Register 130 DA0DT130 D A0 Data Register 131 DA0DT131 D A0 Data Register 132 DA0DT132 D A0 Data Register 133 DA0DT133 D A0 Data Register 134 D...

Page 709: ... DA0DT209 D A0 Data Register 210 DA0DT210 D A0 Data Register 211 DA0DT211 D A0 Data Register 212 DA0DT212 D A0 Data Register 213 DA0DT213 D A0 Data Register 214 DA0DT214 D A0 Data Register 215 DA0DT215 D A0 Data Register 216 DA0DT216 D A0 Data Register 217 DA0DT217 D A0 Data Register 218 DA0DT218 D A0 Data Register 219 DA0DT219 D A0 Data Register 220 DA0DT220 D A0 Data Register 221 DA0DT221 D A0 D...

Page 710: ...4 5 6 D7 PRSA When reset H 00 D Bit Name Function R W 0 7 PRSA Sets the prescaler s divide by value The Prescaler A generates a count clock for the D A converter s parameter table address counter DACNT from the internal peripheral clock 20 0 MHz when the CPU clock 40 MHz by dividing it by an appropriate value When the value of Prescaler Register A is rewritten while the DACNT is operating the pres...

Page 711: ...bit reload register value The DACNT Reload Register is used to reload data into the DACNT Counter Data is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed Simply because data is written to the DACNT Reload Register does not mean that the DACNT Counter is loaded with the data D A CONVERTERS 16 2 D A Converter Related Registers ...

Page 712: ...DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA Setting the DACNTEN bit to 0 disables the DACNT Counter so that it stops counting with the count value retained D0 1 2 3 4 5 6 D7 DACNTEN When reset H 00 D Bit Name Function R W 0 6 No functions assigned 0 7 DACNTEN 0 Stops count 1 Enables count D A CONVERTERS 16 2 D A Converte...

Page 713: ...egister and restarts counting down from the newly set value The diagram below shows operation of the DACNT Counter when the DACNT Counter and the DACNT Reload Register respectively have the values H A0 and H B0 set as their initial values D0 1 2 3 4 5 6 D7 DACNT When reset H 00 D Bit Name Function R W 0 7 DACNT 8 bit counter value Count clock Enable bit H FF H 00 DACNT Reload Register DACNT Counte...

Page 714: ...tinuous mode is selected Note The D A1 Converter does not have continuous mode This mode is available for only the D A0 Converter 2 DA1ON DA1 analog output enable bit D6 This bit controls whether or not to output the conversion result of the D A1 Converter Setting this bit to 1 enables analog output so that the conversion result is output to the external pin DA1 Setting this bit to 0 disables anal...

Page 715: ...e Function R W 0 7 DA0CNV DA1CNV 8 bit D A conversion data single mode Writing a value 0 255 to the D A Conversion Register DA0CNV DA1CNV causes D A conversion to start The analog voltage V that is output by the D A converter depends on the value n n 0 255 that has been set in the D A Conversion Register DA0CNV DA1CNV D A CONVERTERS 16 2 D A Converter Related Registers V VREF 256 Note VREF referen...

Page 716: ...5 DA0DTn When reset indeterminate D Bit Name Function R W 0 7 DA0DTn 8 bit D A conversion data continuous mode The D A0 Data Registers n n 0 255 are used for D A conversion in continuous mode The values set in the D A0 Data Registers are sequentially D A converted and output as analog quantities D A CONVERTERS 16 2 D A Converter Related Registers ...

Page 717: ...the external pin DAi until the DAiON bit is set to 0 analog output disabled The output voltage V is determined by the equation given below 16 3 2 Continuous Mode The values set in the D A0 Data Registers n n 0 255 are sequentially converted into analog quantities which are then output from the external pin DA0 Setting a value in the D A Data Register n causes D A conversion to start If the D A Con...

Page 718: ...16 16 16 Rev 1 0 This is a blank page D A CONVERTERS 16 3 Functional Description of the D A Converters ...

Page 719: ...17 1 External Bus Interface Related Signals 17 2 Read Write Operations 17 3 Bus Arbitration 17 4 Example for Connecting External Extension Memory CHAPTER 17 CHAPTER 17 EXTERNAL BUS INTERFACE ...

Page 720: ...ytes ___ The CS0 signal points to a 2 Mbyte area when in processor mode or a 1 Mbyte area when in external extended mode For details see Chapter 3 Address Space ___ ___ Note During external extended mode the A12 and A13 pins are shared with the CS2 and CS3 pins respectively Therefore functions of these pins must be selected with the Port P4 and P22 Peripheral Output Select Register In processor mo...

Page 721: ...this pin can be used as P70 by setting the P7 Operation Mode Register P70MOD bit to 0 ___ BUSMOD 1 Write WR is selected indicating that valid data is transferred on the data bus during external write access This output is held high during an external read cycle and when accessing an internal function ____ 8 Wait WAIT When the 32172 32173 started an external bus cycle it automatically inserts wait ...

Page 722: ...rmal operation EXTERNAL BUS INTERFACE 17 1 External Bus Interface Related Signals ____ HACK pin outputs a low level signal during hold and while going to a hold state To return from ____ the hold state to a normal operating state release the HREQ input signal back high When not using the HREQ and HACK functions these pins can be used as P72 and P73 by setting the P7 Operation Mode Register P72MOD ...

Page 723: ...en reset H 00 D Bit Name Function R W 0 P00MOD 0 DB0 Port P00 operation mode 1 P00 1 P01MOD 0 DB1 Port P01 operation mode 1 P01 2 P02MOD 0 DB2 Port P02 operation mode 1 P02 3 P03MOD 0 DB3 Port P03 operation mode 1 P03 4 P04MOD 0 DB4 Port P04 operation mode 1 P04 5 P05MOD 0 DB5 Port P05 operation mode 1 P05 6 P06MOD 0 DB6 Port P06 operation mode 1 P06 7 P07MOD 0 DB7 Port P07 operation mode 1 P07 No...

Page 724: ...ration mode 1 P13 12 P14MOD 0 DB12 Port P14 operation mode 1 P14 13 P15MOD 0 DB13 Port P15 operation mode 1 P15 14 P16MOD 0 DB14 Port P16 operation mode 1 P16 15 P17MOD 0 DB15 Port P17 operation mode 1 P17 Note Settings made to the P1 Operation Mode Register are effective only when the CPU is operating in external extended mode D8 9 10 11 12 13 14 D15 P10MOD P11MOD P12MOD P13MOD P14MOD P15MOD P16M...

Page 725: ...3 operation mode 1 P23 4 P24MOD 0 A27 Port P24 operation mode 1 P24 5 P25MOD 0 A288 Port P25 operation mode 1 P25 6 P26MOD 0 A29 Port P26 operation mode 1 P26 7 P27MOD 0 A30 Port P27 operation mode 1 P27 Note Settings made to the P2 Operation Mode Register are effective only when the CPU is operating in external extended mode D0 1 2 3 4 5 6 D7 P20MOD P21MOD P22MOD P23MOD P24MOD P25MOD P26MOD P27MO...

Page 726: ...eration mode 1 P33 12 P34MOD 0 A19 Port P34 operation mode 1 P34 13 P35MOD 0 A20 Port P35 operation mode 1 P35 14 P36MOD 0 A21 Port P36 operation mode 1 P36 15 P37MOD 0 A22 Port P37 operation mode 1 P37 Note Settings made to the P3 Operation Mode Register are effective only when the CPU is operating in external extended mode D8 9 10 11 12 13 14 D15 P30MOD P31MOD P32MOD P33MOD P34MOD P35MOD P36MOD ...

Page 727: ... D Bit Name Function R W 0 No functions assigned 0 1 P41MOD _______ ______ 0 BLW BLE Port P41 operation mode 1 P41 2 P42MOD _______ ______ 0 BHW BHE Port P42 operation mode 1 P42 3 P43MOD ____ 0 RD Port P43 operation mode 1 P43 4 P44MOD ______ 0 CS0 Port P44 operation mode 1 P44 5 P45MOD ______ 0 CS1 Port P45 operation mode 1 P45 6 No functions assigned 0 7 P47MOD 0 A14 Port P47 operation mode 1 P...

Page 728: ...rt P72 operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK TXD3 12 P74MOD 0 P74 Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P77 Port P77 operation mode 1 RTDCLK D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD EXTERNAL BUS INTERFACE 17 1 Exter...

Page 729: ...this pin has a debug event function its use requires caution Note 3 P222 P224 P226 and P227 are not included D0 1 2 3 4 5 6 D7 P220MOD P225MOD When reset H 00 D Bit Name Function R W 0 P220MOD 0 P220 Port P220 operation mode 1 CTX0 1 4 No functions assigned 0 5 P225MOD 0 P225 Port P225 operation mode 1 Use inhibited 6 7 No functions assigned 0 EXTERNAL BUS INTERFACE 17 1 External Bus Interface Rel...

Page 730: ...t Select Register P22SMOD Address H 0080 0776 D0 1 2 3 4 5 6 D7 P46SMOD D0 1 2 3 4 5 6 D7 P225SMOD When reset H 00 D Bit Name Function R W 0 4 No functions assigned 0 5 P225SMOD 0 A12 Select port P225 peripheral output ______ 1 CS2 6 7 No functions assigned 0 Note Settings made to the P22 Peripheral Output Select Register are effective only when the CPU is operating in external extended mode EXTER...

Page 731: ...e the RD BHW BLW BCLK and WAIT signals can be used When connecting memory chips in boot mode however the Bus Mode Control Register has no effect so that the external bus interface operates assuming that the bus mode control BUSMOD bit 0 When the bus mode control BUSMOD bit 1 the byte enable signal is output separately for __ ___ ___ __ ____ each byte area When in this mode the RD BHE BLE WR and WA...

Page 732: ... write is asserted low allowing data to be written at that position ____ When an external bus cycle starts wait states are inserted as long as WAIT remains low ____ Therefore the WAIT signal must always be held high unless necessary Note that an external bus cycle even during the shortest access has at least one wait state inserted shortest bus cycle consists of 2 BCLK cycles ___ ___ Note CS2 and ...

Page 733: ...K A12 A30 BHW BLW DB0 DB15 WAIT RD Note The circles above show the positions at which signals are sampled H H DB0 DB15 WAIT H 1 wait state 1 wait state CS0 CS1 CS2 CS3 Read Write Figure 17 2 2 Read Write Timing during Shortest External Access EXTERNAL BUS INTERFACE 17 2 Read Write Operations ...

Page 734: ...ons at which signals are sampled H L H DB0 DB15 WAIT Don t Care L H 1 external wait state 2 internal wait states 1 external wait state 2 internal wait states Write 4 cycles CS0 CS1 CS2 CS3 CS0 CS1 CS2 CS3 Read Write Figure 17 2 3 Read Write Timing Accessed with 2 Internal 1 External Wait States EXTERNAL BUS INTERFACE 17 2 Read Write Operations ...

Page 735: ...y byte position ____ When an external bus cycle starts wait states are inserted as long as WAIT remains low ____ Therefore the WAIT signal must always be held high unless necessary Note that an external bus cycle even during the shortest access has at least one wait state inserted shortest bus cycle consists of 2 BCLK cycles When not using the WAIT function set the P7 Operation Mode Register P71MO...

Page 736: ...circles above show the positions at which signals are sampled Note 2 BCLK is not output H H DB0 DB15 WAIT H 1 wait state 1 wait state BHE BLE WR BHE BLE CS0 CS1 CS2 CS3 CS0 CS1 CS2 CS3 Read Write Figure 17 2 5 Read Write Timing during Shortest External Access EXTERNAL BUS INTERFACE 17 2 Read Write Operations ...

Page 737: ...d Note 2 BCLK is not output H L H DB0 DB15 WAIT Don t Care L H 1 external wait state 2 internal wait states 1 external wait state 2 internal wait states Write 4 cycles WR BHE BLE WR BHE BLE CS0 CS1 CS2 CS3 CS0 CS1 CS2 CS3 Read Write Figure 17 2 6 Read Write Timing Accessed with 2 Internal 1 External Wait States EXTERNAL BUS INTERFACE 17 2 Read Write Operations ...

Page 738: ...on the system bus ____ To return from the hold state to a normal operating state release the HREQ input signal back high Figure 17 3 1 Bus Arbitration Timing EXTERNAL BUS INTERFACE 17 3 Bus Arbitration DB0 DB15 BCLK Bus cycle Idle Goes to hold Hold state Return Next bus cycle Note 1 The circles above show the positions at which signals are sampled Note 2 Hi Z denotes a high impedance state Note 3 ...

Page 739: ...Hi Z Hi Z Hi Z CS0 CS1 CS2 CS3 2 When Bus Mode Control Register 1 Byte enable separate mode ____ When the input signal at the HREQ pin is asserted low and the hold request is accepted the CPU ____ enters a hold state in which it outputs a low from the HACK pin During hold the bus related signals go to a high impedance state allowing data transfers to be performed on the system bus ____ To return f...

Page 740: ... extension memory to the chip the MSB and the LSB sides must be reversed EXTERNAL BUS INTERFACE 17 4 Example for Connecting External Extension Memory Memory mapping Internal flash memory 256KB Bus wait states can be set to 1 through 4 Normally used for port function Use WAIT only when four or more wait states are required H 0000 0000 H 001F FFFF H 0040 0000 H 0020 0000 H 0004 0000 Unused H 0010 00...

Page 741: ...ernal Extension Memory Memory mapping Internal flash memory 256KB H 0000 0000 H 0020 0000 H 0004 0000 Unused H 0010 0000 2M CS1 area 32172 32173 A 13 30 D 0 15 RD CS0 CS1 BLW BHW Ghost area H 0028 0000 1M CS0 area 2M CS2 area 2M CS3 area H 0040 0000 Ghost area H 0048 0000 H 0080 0000 H 0060 0000 Unused CS2 CS2 external memory area 512MB CS1 external memory area 512MB CS0 external memory area 512MB...

Page 742: ...an be set to 1 through 4 Note 2 Normally used for port function Use WAIT only when four or more wait states are required Memory mapping Internal flash memory 256KB H 0000 0000 H 0020 0000 H 0004 0000 Unused H 0010 0000 2M CS1 area 32172 32173 A 14 30 D 0 15 RD CS0 CS2 BLW BHW Ghost area H 0024 0000 1M CS0 area 2M CS2 area 2M CS3 area H 0040 0000 Ghost area H 0044 0000 H 0080 0000 H 0060 0000 Ghost...

Page 743: ...the MSB and the LSB sides must be reversed EXTERNAL BUS INTERFACE 17 4 Example for Connecting External Extension Memory SRAM M32172F2 A12 A30 D0 D15 RD CS0 CS1 BLE BHE Bus wait states can be set to 1 through 4 WAIT Normally used for port function Use WAIT only when four or more wait states are required Flash memory A18 A0 D15 D0 RD CS max1MB A18 A0 D15 D0 RD D0 D15 CS BHE D0 D7 BLE D8 D15 max1MB W...

Page 744: ...al extension memory to the chip the MSB and the LSB sides must be reversed EXTERNAL BUS INTERFACE 17 4 Example for Connecting External Extension Memory Memory mapping Internal flash memory 256KB External memory area 1MB Memory can be connected with only 2 ns data delay when CL 50 pF Normally used for port function Use WAIT only when four or more wait states are required H 0000 0000 H 0040 0000 H 0...

Page 745: ...18 1 Outline of the Wait Controller 18 2 Wait Controller Related Registers 18 3 Typical Operation of the Wait Controller CHAPTER 18 CHAPTER 18 WAIT CONTROLLER ...

Page 746: ...rocessor mode CS0 area 2 Mbytes CS1 area 2 Mbytes Number of wait cycles ____ One to four wait cycles set in software any wait cycles inserted by WAIT pin that can be inserted input Bus cycle during external access has at least one wait cycle inserted which is the shortest access possible ___ ___ ___ ___ In external extended four chip select signals CS0 CS1 CS2 and CS3 are output for external exten...

Page 747: ...rough CS3 Areas When accessing an external extended area the Wait Controller controls the number of wait cycles to be inserted in the bus cycle by checking the number of wait cycles set in software and those set ____ by an input signal from the WAIT pin The number of wait cycles that can be controlled by software is 1 to 4 External access incurs at least one wait cycle which is the shortest bus cy...

Page 748: ...ddress from H 0030 0000 to H 003F FFFF Note 2 A ghost of the CS0 area appears in the area ranging in address from H 0018 0000 to H 001F FFFF Note 3 A ghost of the CS1 area appears in the area ranging in address from H 0028 0000 to H 003F FFFF Note 4 A ghost of the CS2 area appears in the area ranging in address from H 0048 0000 to H 005F FFFF Note 5 A ghost of the CS0 area appears in areas ranging...

Page 749: ...__ software any wait cycles inserted by WAIT pin input Software settings have priority however CS1 area H 0020 0000 H 002F FFFF Note 2 WAIT CONTROLLER 18 1 Outline of the Wait Controller Note 1 A 1 Mbyte ghost of the CS0 area appears in the area ranging in address from H 0010 0000 to H 001F FFFF Note 2 A 1 Mbyte ghost of the CS1 area appears in the area ranging in address from H 0030 0000 to H 003...

Page 750: ...er related register map is shown below Figure 18 2 1 Wait Controller Related Register Map WAIT CONTROLLER 18 2 Wait Controller Related Registers H 0080 0180 Address D0 D7 0 address 1 address D8 D15 Wait Cycles Control Register WTCCR Blank areas are reserved for future use ...

Page 751: ...it states 10 2 wait cycles 11 1 wait cycle 2 3 CS0WTC 00 4 wait cycles when reset Control the number of 01 3 wait cycles CS0 wait states 10 2 wait cycles 11 1 wait cycle 4 5 CS3WTC 00 4 wait cycles when reset Control the number of 01 3 wait cycles CS3 wait states 10 2 wait cycles 11 1 wait cycle 6 7 CS1WTC 00 4 wait cycles when reset Control the number of 01 3 wait cycles CS1 wait states 10 2 wait...

Page 752: ...with the wait controller 1 When Bus Mode Control Register 0 ___ External read write operations are performed using the address bus data bus and signals CS0 ___ ___ ___ __ ___ ___ ____ CS1 CS2 CS3 RD BHW BLW WAIT and BCLK Figure 18 3 1 Internal Bus Access during Bus Free State Note THi Z denotes a high impedance state WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller Bus free state inte...

Page 753: ... above indicate points at which signals are sampled WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller Read 2 cycles H H H H One wait cycle BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 2 cycles One wait cycle BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Write ...

Page 754: ...ints at which signals are sampled WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H Don t Care H H Don t Care H 2 internal wait cycles Read 3 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 3 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Write 2 internal wait cycles ...

Page 755: ...ess with 3 Internal Wait Cycles Note Circles above indicate points at which signals are sampled H Don t Care H H Don t Care H 3 internal wait cycles Read 4 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 4 cycles BCLK A12 A30 CS0 CS1 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 3 internal wait cycles ...

Page 756: ...ess with 4 Internal Wait Cycles Note Circles above indicate points at which signals are sampled H Don t Care H H Don t Care H 4 internal wait cycles Read 5 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 5 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Write 4 internal wait cycles ...

Page 757: ...nal Wait Cycles Note Circles above indicate points at which signals are sampled H Don t Care H H Don t Care H 4 internal wait cycles Read 6 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 6 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Write 4 internal wait cycles L L 1 external wait cycle 1 external wait cycle ...

Page 758: ...t Cycles Note Circles above indicate points at which signals are sampled H Don t Care H H Don t Care H 2 internal wait cycles Read 3 n cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Read Write 3 n cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD Write 2 internal wait cycles L L n external wait cycles n external wait cycles L L L L ...

Page 759: ...es a high impedance state Note 2 BCLK is not output 2 When Bus Mode Control Register 1 ___ External read write operations are performed using the address bus data bus and signals CS0 ___ ___ ___ __ ___ ___ ____ __ CS1 CS2 CS3 RD BHE BLE WAIT and WR H H Hi z H H Bus free state internal bus access BCLK A12 A30 CS0 CS1 CS2 CS3 BHW BLW DB0 DB15 WAIT RD WR ...

Page 760: ...s at which signals are sampled Note 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Read 2 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 2 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write WR WR 1 internal wait cycle 1 internal wait cycle ...

Page 761: ...signals are sampled Note 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Don t Care 2 internal wait cycles Read 3 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 3 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write 2 internal wait cycles WR WR Don t Care ...

Page 762: ...signals are sampled Note 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Don t Care 3 internal wait cycles Read 4 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 4 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write 3 internal wait cycles WR WR Don t Care ...

Page 763: ...signals are sampled Note 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Don t Care 4 internal wait cycles Read 5 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 5 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write 4 internal wait cycles WR WR Don t Care ...

Page 764: ...ed Note 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Don t Care 4 internal wait cycles Read 6 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 6 cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write 4 internal wait cycles WR WR Don t Care L L 1 external wait cycle 1 external wait cycle ...

Page 765: ... 2 BCLK is not output WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller H H H H Don t Care 2 internal wait cycles Read 3 n cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Read Write 3 n cycles BCLK A12 A30 CS0 CS1 CS2 CS3 BHE BLE DB0 DB15 WAIT RD Write 2 internal wait cycles WR WR Don t Care L L n external wait cycles n external wait cycles L L L L ...

Page 766: ...18 18 22 Rev 1 0 WAIT CONTROLLER 18 3 Typical Operation of the Wait Controller This is a blank page ...

Page 767: ...19 1 Outline 19 2 Example of RAM Backup when Power is Down 19 3 Example of RAM Backup for Saving Power Consumption 19 4 Exiting RAM Backup Mode Wakeup CHAPTER 19 CHAPTER 19 RAM BACKUP MODE ...

Page 768: ...ion in the system can effectively reduced 19 2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 19 2 1 The following explains how the RAM can be backed up by using this circuit as an example RAM BACKUP MODE 19 1 Outline Figure 19 2 1 Typical Circuit for RAM Backup at Power Outage Note 1 Power outage is detected by the DC IN regulator inpu...

Page 769: ...e DC IN regulator input voltage Note 2 These pins are used to detect a RAM backup signal Note 3 This pin outputs a high when the power is on and outputs a low when the power is down Note 4 Backup power supply 2 0 to 3 3 V VREFn SBI ADnINi M32R E C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power su...

Page 770: ...nal in Figure 17 2 3 Whether the power is down or not must be determined with respect to the DC IN regulator input voltage in order to allow for a software processing time at power outage To enable RAM backup mode make the following settings 1 Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally in Figure 19 2 3 When the power s...

Page 771: ...t as an example Figure 19 3 1 Typical Circuit for RAM Backup to Save on Power Consumption Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when the power is on and is set for input mode when in RAM backup mode Note 3 These pins are used to detect a RAM backup signal RAM backup signal Note 1 External circuit Port X IB RAM backup power supply DC IN Input Output Regulato...

Page 772: ...necting pin should output a high This causes the transistor s base voltage IB to go high so that current is fed from the power supply to the VCC pin via the transistor Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when the power is on and is set for input mode when in RAM backup mode Note 3 These pins are used to detect a RAM backup signal RAM backup signal Note 1 ...

Page 773: ...ly to the VCC pin via the transistor C in Figure 19 3 3 Consequently the power to the VCC pin is shut off D in Figure 19 3 3 Due to settings in 1 to 3 the voltage applied to the VDD pin becomes 3 3 V 10 and voltages applied to all other pins drop to 0 V thus placing the M32R E in RAM backup mode in Figure 19 2 3 Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when th...

Page 774: ...is indeterminate Therefore be sure to set the output high level in the Port X Data Register before you set port X for output mode Unless this method is followed port output may go low at the same time port output is set after the clock oscillation has stabilized causing the device to enter RAM backup mode RESET SBI ADnINi VCCI OSC VCC VDD Oscillation stabilization time External input signal goes l...

Page 775: ...before entering RAM backup mode in Figure 19 4 1 4 If the RAM contents and check data did not match when checked in 3 initialize the RAM in Figure 19 4 1 If the RAM contents and check data matched use the retained data in the program 5 After initializing each internal circuit in Figure 19 4 1 return the main routine in Figure 19 4 1 Note For wakeup from power outage RAM backup mode settings for po...

Page 776: ...19 19 10 Rev 1 0 RAM BACKUP MODE 19 4 Exiting RAM Backup Mode Wakeup This is a blank page ...

Page 777: ...CHAPTER 20 CHAPTER 20 OSCILLATION CIRCUIT 20 1 Oscillator Circuit 20 2 Clock Generator Circuit ...

Page 778: ...cillator Circuit A clock generating circuit can be configured by connecting a ceramic or crystal resonator between the XIN and XOUT pins external to the chip Figure 20 1 1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin VCNT For constants Rf CIN COUT and Rd consult your resonator...

Page 779: ...wn below P7 Operation Mode Register P7MOD Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD When reset H 00 D Bit Name Function R W 8 P70MOD 0 P70 Port P70 operation mode 1 BCLK 9 P71MOD 0 P71 Port P71 operation mode ____ 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK 12 P74MOD 0 P74 P...

Page 780: ...r on The oscillator circuit comprised of a ceramic or crystal resonator has a finite time after power on at which its oscillation is instable Therefore create a certain amount of oscillation stabilization time that suits the oscillator circuit used Figure 20 1 2 shows an oscillation stabilization time at power on RESET XIN Oscillation stabilization time OSC VCC ...

Page 781: ... OSCILLATION CIRCUIT 20 2 Clock Generator Circuit 20 2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits XIN 8MHz 10MHz BCLK 16MHz 20MHz CPU clock 32MHz 40MHz X4 1 2 1 2 internal peripheral clock 8MHz 10MHz 1 4 ...

Page 782: ...20 20 6 Rev 1 0 OSCILLATION CIRCUIT 20 2 Clock Generator Circuit This is a blank page ...

Page 783: ...n of the JTAG Circuit 21 3 JTAG Registers 21 4 Basic Operation of the JTAG 21 5 Boundary Scan Description Language 21 6 Precautions on Board Design when Connecting the JTAG 21 7 Processing Pins when Not Using the JTAG CHAPTER 21 CHAPTER 21 JTAG ...

Page 784: ...Input Synchronous serial data input pin used to enter test instruction code and test data This input is sampled on rising edges of JTCK JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data This signal changes state on falling edges of JTCK and is output only in Shift IR or Shift DR state JTMS Test mode select Input Test mode select inpu...

Page 785: ...y scan path A set of data registers which are accessed through the boundary scan path Test access port abbreviated TAP controller to control the JTAG unit s state transitions Control logic to select input output etc A configuration of the JTAG circuit is shown below JTCK JTMS JTRST TAP controller Instruction register 6 bits JTAGIR Decoder JTDO ID code register JTAGIDR Bypass register JTAGBPR Bound...

Page 786: ...te that if this operation is performed the device may inadvertently handle b 110001 as instruction code which makes it unable to operate normally Capture IR Exit1 IR Update IR The 32172 32173 s JTAG interface supports the following instructions Three instructions stipulated as essential in IEEE 1149 1 EXTEST SAMPLE PRELOAD BYPASS Device ID register access instruction IDCODE Table 21 3 1 JTAG Instr...

Page 787: ...scan test Connected between the JTDI and JTDO pins this register is selected when issuing BYPASS instruction This register when in Capture DR state has b 0 fixed value loaded into it 3 ID Code Register JTAGIDR The ID Code Register is a 32 bit register used to identify the device and manufacturer It holds the following information Version information 4 bits b 0000 Part number 16 bits b 0011 0010 00...

Page 788: ...rom outside through the boundary scan path The sampled value is output to an external device at the same time data is set from outside As register operation bits are shifted right between each shift register stage Update operation The data set from outside during shift is driven As register operation the value set in the shift register stage is transferred to the parallel output stage The JTAG int...

Page 789: ...IR does not all have to be like this Data input G 0 1 D T Q D T R Q Shift DR or Shift IR Clock DR or Clock IR Update DR or Update IR Test reset From preceding cell To next cell Data output Parallel output stage Shift register stage Input multiplexer Note Values 0 and 1 in this diagram denote the state of JTMS input signal Select DR Scan Test Logic Reset Run Test Idle 0 1 0 Capture DR 0 Shift DR 0 ...

Page 790: ...e the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit Because instruction code is set in the instruction register which is comprised of 6 bits the Shift IR state continues for a period of 6 JTCK cycles To stop the shift operation in the middle go to Pause IR state via temporarily Exit1 IR state by setting JTMS input from high to low Also to return ...

Page 791: ...ts 1 0 0 0 1 1 LSB value JTMS TAP state JTDI JTDO High impedance Shift output from the instruction register is fixed to b 110001 Finished storing instruction code in the instruction register s shift register stage Instruction code is set in the parallel output stage at fall of JTCK in Update IR state JTDI input is sampled at rise of JTCK in Shift IR state JTDO is output at fall of JTCK in Shift IR...

Page 792: ...e data that was set in 2 is serially output from the JTDO in At the same time the setup data serially entered from the JTDI pin is set in the data register s shift register stage bit by bit By continuing the Shift DR state as long as the number of bits of the selected data register by entering JTMS low all bits of data can be set in and read out from the shift register stage To stop the shift oper...

Page 793: ... set in LSB side JTCK Select DR Scan Capture DR Shift DR Exit1 DR Update DR Run Test Idle Run Test Idle Don t Care Don t Care JTMS JTDI JTDO Finished storing setup data in the shift register stage of the selected data register Setup data is set in the parallel output stage at fall of JTCK in Update DR state JTDI input is sampled at rise of JTCK in Shift DR state TAP state LSB value High impedance ...

Page 794: ...e idle state hold JTMS input low 3 Set JTMS high to exit Run Test Idle state and perform IR path sequence In IR path sequence specify the data register you want to inspect or set 4 Subsequently perform DR path sequence For the data register specified in IR path sequence enter setup data from the JTDI pin and read out reference data from the JTDO pin 5 If after DR path sequence is completed you wan...

Page 795: ...ng Capture DR state Specify the data register you want to inspect or set Test Logic Reset state Run Test Idle state IR path sequence TAP states Instruction code 0 Setup data 0 JTDI Note 1 Fixed value b 110001 Note 3 JTDO Note 2 Setup data is entered serially from JTDI Reference data is serially output from JTDO 1 Basic access Same data register can be operated on to inspect or set data continuousl...

Page 796: ...ut input output buffer or link of each pin that defines the logical direction of signal flow Physical pin map The physical pin map correlates the chip s logical ports to the physical pins on each package Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description Instruction set statement The instruction set statement writes bit patterns to be ...

Page 797: ...inkage bit P30 inout bit P31 inout bit P32 inout bit P33 inout bit P34 inout bit P35 inout bit P36 inout bit P37 inout bit P20 inout bit P21 inout bit P22 inout bit P23 inout bit VCCE_20 linkage bit VSS_21 linkage bit P24 inout bit P25 inout bit P26 inout bit P27 inout bit P00 inout bit P01 inout bit P02 inout bit P03 inout bit P04 inout bit P05 inout bit P06 inout bit P07 inout bit P10 inout bit ...

Page 798: ...74 inout bit P175 inout bit VCCE_65 linkage bit P82 inout bit P83 inout bit P84 inout bit P85 inout bit P86 inout bit P87 inout bit VSS_72 linkage bit FVCC_73 linkage bit P61 inout bit P62 inout bit P63 inout bit P64 in bit P70 inout bit P71 inout bit P72 inout bit P73 inout bit P74 inout bit P75 inout bit P76 inout bit P77 inout bit P93 in bit P94 inout bit P95 inout bit P96 inout bit P97 in bit ...

Page 799: ... bit P131 in bit P132 in bit P133 in bit P134 in bit P135 in bit P136 in bit P137 in bit VCCE_132 linkage bit P150 inout bit P153 inout bit P41 inout bit P42 inout bit VCCI_137 linkage bit VSS_138 linkage bit P43 inout bit P44 inout bit P45 inout bit P46 inout bit P47 inout bit P220 inout bit use STD_1149_1_1994 all attribute COMPONENT_CONFORMANCE of M32173F2VFP entity is STD_1149_1_1993 attribute...

Page 800: ...4 P27 25 P00 26 P01 27 P02 28 P03 29 P04 30 P05 31 P06 32 P07 33 P10 34 P11 35 P12 36 P13 37 P14 38 P15 39 P16 40 P17 41 VREF_42 42 AVCC_43 43 AD0IN0 44 AD0IN1 45 AD0IN2 46 AD0IN3 47 AD0IN4 48 AD0IN5 49 AD0IN6 50 AD0IN7 51 AD1IN0 52 AD1IN1 53 AD1IN2 54 AD1IN3 55 DA0 56 DA1 57 P172 58 P173 59 AVSS_60 60 VCCI_61 61 VSS_62 62 P174 63 P175 64 VCCE_65 65 P82 66 P83 67 P84 68 P85 69 P86 70 P87 71 VSS_72...

Page 801: ... 86 P94 87 P95 88 P96 89 P97 90 RESET 91 MOD0 92 MOD1 93 FP 94 VCCE_95 95 VSS_96 96 P110 97 P111 98 P112 99 P113 100 P114 101 P115 102 P116 103 P117 104 P100 105 P101 106 P102 107 VDD_108 108 TMS 109 TCK 110 TRST 111 TDO 112 TDI 113 P103 114 P104 115 P105 116 P106 117 P107 118 P124 119 P125 120 P126 121 P127 122 VCCI_123 123 P130 124 P131 125 P132 126 P133 127 P134 128 P135 129 P136 130 P137 131 V...

Page 802: ...ty is 6 attribute INSTRUCTION_OPCODE of M32173F2VFP entity is BYPASS 111111 SAMPLE 000001 EXTEST 000000 IDCODE 000010 USERCODE 000011 MDM_SYSTEM 001000 MDM_CONTROL 001001 MDM_SETUP 001010 MTM_CONTROL 001111 MON_CODE 010000 MON_DATA 010001 MON_PARAM 010010 MON_ACCESS 010011 DMA_RADDR 011000 DMA_RDATA 011001 DMA_RTYPE 011010 DMA_ACCESS 011011 RTDENB 100000 attribute INSTRUCTION_CAPTURE of M32173F2VF...

Page 803: ...A_RADDR DMA_RDATA_REG 32 DMA_RDATA DMA_RTYPE_REG 3 DMA_RTYPE DMA_ACCESS_REG 3 DMA_ACCESS RTDENB_REG 1 RTDENB attribute BOUNDARY_LENGTH of M32173F2VFP entity is 265 attribute BOUNDARY_REGISTER of M32173F2VFP entity is num cell port function safe ccell disval rslt 264 BC_4 P103 observe_only X 263 BC_1 P103 output3 X 262 0 Z 262 BC_1 control 0 261 BC_4 P104 observe_only X 260 BC_1 P104 output3 X 259 ...

Page 804: ...ontrol 0 216 BC_4 P46 observe_only X 215 BC_1 P46 output3 X 214 0 Z 214 BC_1 control 0 213 BC_4 P47 observe_only X 212 BC_1 P47 output3 X 211 0 Z 211 BC_1 control 0 210 BC_4 P220 observe_only X 209 BC_1 P220 output3 X 208 0 Z 208 BC_1 control 0 207 BC_4 P221 observe_only X 206 BC_4 P225 observe_only X 205 BC_1 P225 output3 X 204 0 Z 204 BC_1 control 0 203 BC_4 P30 observe_only X 202 BC_1 P30 outpu...

Page 805: ...X 156 0 Z 156 BC_1 control 0 155 BC_4 P00 observe_only X 154 BC_1 P00 output3 X 153 0 Z 153 BC_1 control 0 152 BC_4 P01 observe_only X 151 BC_1 P01 output3 X 150 0 Z 150 BC_1 control 0 149 BC_4 P02 observe_only X 148 BC_1 P02 output3 X 147 0 Z 147 BC_1 control 0 146 BC_4 P03 observe_only X 145 BC_1 P03 output3 X 144 0 Z 144 BC_1 control 0 143 BC_4 P04 observe_only X 142 BC_1 P04 output3 X 141 0 Z ...

Page 806: ...X 97 0 Z 97 BC_1 control 0 96 BC_4 P83 observe_only X 95 BC_1 P83 output3 X 94 0 Z 94 BC_1 control 0 93 BC_4 P84 observe_only X 92 BC_1 P84 output3 X 91 0 Z 91 BC_1 control 0 90 BC_4 P85 observe_only X 89 BC_1 P85 output3 X 88 0 Z 88 BC_1 control 0 87 BC_4 P86 observe_only X 86 BC_1 P86 output3 X 85 0 Z 85 BC_1 control 0 84 BC_4 P87 observe_only X 83 BC_1 P87 output3 X 82 0 Z 82 BC_1 control 0 81 ...

Page 807: ...erve_only X 34 BC_4 MOD1 observe_only X 33 BC_4 FP observe_only X 32 BC_4 P110 observe_only X 31 BC_1 P110 output3 X 30 0 Z 30 BC_1 control 0 29 BC_4 P111 observe_only X 28 BC_1 P111 output3 X 27 0 Z 27 BC_1 control 0 26 BC_4 P112 observe_only X 25 BC_1 P112 output3 X 24 0 Z 24 BC_1 control 0 23 BC_4 P113 observe_only X 22 BC_1 P113 output3 X 21 0 Z 21 BC_1 control 0 20 BC_4 P114 observe_only X 19...

Page 808: ...XOUT buffer bit OSCVCC_6 linkage bit VCNT_7 linkage bit P30 inout bit P31 inout bit P32 inout bit P33 inout bit P34 inout bit P35 inout bit P36 inout bit P37 inout bit P20 inout bit P21 inout bit P22 inout bit P23 inout bit VCCE_20 linkage bit VSS_21 linkage bit P24 inout bit P25 inout bit P26 inout bit P27 inout bit P00 inout bit P01 inout bit P02 inout bit P03 inout bit P04 inout bit P05 inout b...

Page 809: ...174 inout bit P175 inout bit VCCE_65 linkage bit P82 inout bit P83 inout bit P84 inout bit P85 inout bit P86 inout bit P87 inout bit VSS_72 linkage bit FVCC_73 linkage bit P61 inout bit P62 inout bit P63 inout bit P64 in bit P70 inout bit P71 inout bit P72 inout bit P73 inout bit P74 inout bit P75 inout bit P76 inout bit P77 inout bit P93 in bit P94 inout bit P95 inout bit P96 inout bit P97 in bit...

Page 810: ...t P135 in bit P136 in bit P137 in bit VCCE_132 linkage bit P150 inout bit P153 inout bit P41 inout bit P42 inout bit VCCI_137 linkage bit VSS_138 linkage bit P43 inout bit P44 inout bit P45 inout bit P46 inout bit P47 inout bit P220 inout bit use STD_1149_1_1994 all attribute COMPONENT_CONFORMANCE of M32172F2VFP entity is STD_1149_1_1993 attribute PIN_MAP of M32172F2VFP entity is PHYSICAL_PIN_MAP ...

Page 811: ...P06 32 P07 33 P10 34 P11 35 P12 36 P13 37 P14 38 P15 39 P16 40 P17 41 VREF_42 42 AVCC_43 43 AD0IN0 44 AD0IN1 45 AD0IN2 46 AD0IN3 47 AD0IN4 48 AD0IN5 49 AD0IN6 50 AD0IN7 51 AD1IN0 52 AD1IN1 53 AD1IN2 54 AD1IN3 55 DA0 56 DA1 57 P172 58 P173 59 AVSS_60 60 VCCI_61 61 VSS_62 62 P174 63 P175 64 VCCE_65 65 P82 66 P83 67 P84 68 P85 69 P86 70 P87 71 VSS_72 72 Figure 21 5 15 BSDL Description for the 32172 4...

Page 812: ...3 86 P94 87 P95 88 P96 89 P97 90 RESET 91 MOD0 92 MOD1 93 FP 94 VCCE_95 95 VSS_96 96 P110 97 P111 98 P112 99 P113 100 P114 101 P115 102 P116 103 P117 104 P100 105 P101 106 P102 107 VDD_108 108 TMS 109 TCK 110 TRST 111 TDO 112 TDI 113 P103 114 P104 115 P105 116 P106 117 P107 118 P124 119 P125 120 P126 121 P127 122 VCCI_123 123 P130 124 P131 125 P132 126 P133 127 P134 128 P135 129 P136 130 P137 131 ...

Page 813: ...ue attribute INSTRUCTION_LENGTH of M32172F2VFP entity is 6 attribute INSTRUCTION_OPCODE of M32172F2VFP entity is BYPASS 111111 SAMPLE 000001 EXTEST 000000 IDCODE 000010 USERCODE 000011 MDM_SYSTEM 001000 MDM_CONTROL 001001 MDM_SETUP 001010 MTM_CONTROL 001111 MON_CODE 010000 MON_DATA 010001 MON_PARAM 010010 MON_ACCESS 010011 DMA_RADDR 011000 DMA_RDATA 011001 DMA_RTYPE 011010 DMA_ACCESS 011011 RTDENB...

Page 814: ..._RADDR DMA_RDATA_REG 32 DMA_RDATA DMA_RTYPE_REG 3 DMA_RTYPE DMA_ACCESS_REG 3 DMA_ACCESS RTDENB_REG 1 RTDENB attribute BOUNDARY_LENGTH of M32172F2VFP entity is 265 attribute BOUNDARY_REGISTER of M32172F2VFP entity is num cell port function safe ccell disval rslt 264 BC_4 P103 observe_only X 263 BC_1 P103 output3 X 262 0 Z 262 BC_1 control 0 261 BC_4 P104 observe_only X 260 BC_1 P104 output3 X 259 0...

Page 815: ...ontrol 0 216 BC_4 P46 observe_only X 215 BC_1 P46 output3 X 214 0 Z 214 BC_1 control 0 213 BC_4 P47 observe_only X 212 BC_1 P47 output3 X 211 0 Z 211 BC_1 control 0 210 BC_4 P220 observe_only X 209 BC_1 P220 output3 X 208 0 Z 208 BC_1 control 0 207 BC_4 P221 observe_only X 206 BC_4 P225 observe_only X 205 BC_1 P225 output3 X 204 0 Z 204 BC_1 control 0 203 BC_4 P30 observe_only X 202 BC_1 P30 outpu...

Page 816: ...X 156 0 Z 156 BC_1 control 0 155 BC_4 P00 observe_only X 154 BC_1 P00 output3 X 153 0 Z 153 BC_1 control 0 152 BC_4 P01 observe_only X 151 BC_1 P01 output3 X 150 0 Z 150 BC_1 control 0 149 BC_4 P02 observe_only X 148 BC_1 P02 output3 X 147 0 Z 147 BC_1 control 0 146 BC_4 P03 observe_only X 145 BC_1 P03 output3 X 144 0 Z 144 BC_1 control 0 143 BC_4 P04 observe_only X 142 BC_1 P04 output3 X 141 0 Z ...

Page 817: ...X 97 0 Z 97 BC_1 control 0 96 BC_4 P83 observe_only X 95 BC_1 P83 output3 X 94 0 Z 94 BC_1 control 0 93 BC_4 P84 observe_only X 92 BC_1 P84 output3 X 91 0 Z 91 BC_1 control 0 90 BC_4 P85 observe_only X 89 BC_1 P85 output3 X 88 0 Z 88 BC_1 control 0 87 BC_4 P86 observe_only X 86 BC_1 P86 output3 X 85 0 Z 85 BC_1 control 0 84 BC_4 P87 observe_only X 83 BC_1 P87 output3 X 82 0 Z 82 BC_1 control 0 81 ...

Page 818: ...erve_only X 34 BC_4 MOD1 observe_only X 33 BC_4 FP observe_only X 32 BC_4 P110 observe_only X 31 BC_1 P110 output3 X 30 0 Z 30 BC_1 control 0 29 BC_4 P111 observe_only X 28 BC_1 P111 output3 X 27 0 Z 27 BC_1 control 0 26 BC_4 P112 observe_only X 25 BC_1 P112 output3 X 24 0 Z 24 BC_1 control 0 23 BC_4 P113 observe_only X 22 BC_1 P113 output3 X 21 0 Z 21 BC_1 control 0 20 BC_4 P114 observe_only X 19...

Page 819: ...l Figure 21 6 1 Precautions on Connecting the User Board and JTAG JTAG 21 6 Precautions on Board Design when Connecting the JTAG M32R E JTDI JTMS JTCK JTRST User board JTAG tool Make sure the wiring lengths are the same and avoid bending wirings as much as possible Also do not use through holes within wirings JTDO 33Ω 33Ω VCCE 5V 33Ω 33Ω 33Ω 2KΩ 10KΩ 10KΩ 10KΩ 10KΩ 0 1µF SDI connector JTAG connect...

Page 820: ...in wirings JTDO 33Ω 33Ω VCCE 5V 33Ω 33Ω 33Ω 33Ω 2KΩ 10KΩ 10KΩ 10KΩ 10KΩ DBI 10KΩ 33Ω TRCLK 33Ω TRSYNC 33Ω TRDATA 0 7 33Ω EVENT 0 1 0 1µF SDI connector JTAG connector Power TDI TMS TCK TRST TDO DBI TRCLK TRSYNC GND When connecting the emulator TRDATA 0 7 EVENT 0 1 8 2 Figure 21 6 2 Precautions on Connecting the User Board and JTAG for the 255FBGA JTAG 21 6 Precautions on Board Design when Connectin...

Page 821: ... sure the pins on the microcomputer are processed properly as shown below Figure 21 7 1 Processing Pins when Not Using the JTAG for the 144LGFP JTAG 21 7 Processing Pins when Not Using the JTAG M32R E JTDI JTMS JTCK JTRST User board JTDO VCCE 5V 0 to 100K 0 to 100K 0 to 10K 0 to 10K 0 to 10K ...

Page 822: ...Not Using the JTAG for the 175FBGA JTAG 21 7 Processing Pins when Not Using the JTAG M32R E JTDI JTMS JTCK JTRST User board JTDO VCCE 5V 0 to 100K 0 to 100K DBI TRCLK TRSYNC TRDATA 0 7 EVENT 0 1 0 to 100K 0 to 100K 0 to 100K 0 to 100K OPEN OPEN OPEN OPEN ...

Page 823: ...22 1 Configuration of the Power Supply Circuit 22 2 Power On Sequence 22 3 Power Shutdown Sequence CHAPTER 22 CHAPTER 22 POWER UP POWER SHUTDOWN SEQUENCE ...

Page 824: ...cuit Table 22 1 1 List of Power Supply Functions Type of Power Supply Pin Name Function 5 0 V system VCCE Supplies power to external I O ports AVCC0 Power supply for A D converter VREF0 Reference voltage for A D converter 3 3 V system VCCI Supplies power to internal logic FVCC Power supply for internal flash memory VDD Power supply for internal RAM backup OSC VCC Power supply for oscillator and PL...

Page 825: ... power supply after turning on the 5 V power supply ____________ After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC VCCI FVCC VCCE VCCI FVCC OSC VCC VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC VCC 5V 5V 5V 5V 3 3V 3 3V 3 3V 3 3V 0V 0V 0V 0V ...

Page 826: ...ter turning on the 5 V power supply ____________ After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC VCCI FVCC VCCE VCCI FVCC OSC VCC VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC VCC 5V 5V 5V 5V 3 3V 3 3V 3 3V 3 3V 0V 2 0V 0V 0V 0V 0V 0V 0V 0V...

Page 827: ... POWER UP POWER SHUTDOWN SEQUENCE 22 3 Power Shutdown Sequence Figure 22 3 1 Power Shutdown Sequence When Not Using RAM Backup ____________ Pull the RESET pin input low ____________ Turn off the 5 V and the 3 V power supply after the RESET pin goes low Note Power shutdown requirements VDD VCCI FVCC OSC VCC VCCI VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC VCC 5V 5V 5V 5V 3 3V 3 3V 3 3V 3 3V 0V 0V 0V 0...

Page 828: ..._____ Pull the HREQ pin input low to halt the CPU at end of bus cycle Or disable RAM access in software The M32R E allows P72 to be used as HREQ irrespective of its operation mode ____________ With the CPU halted pull the RESET pin input low Or while RAM access is disabled pull ____________ the RESET pin input low ____________ Turn off the 5 V and the 3 3 V power supply after the RESET pin goes lo...

Page 829: ...rter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V 3 3V OSC VCC FVCC VDD VCCI AVCC0 VCCE M32R E I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 0V 3 3V 5V power supply 3 3V power supply Figure 22 3 3 Microcomputer Ready to Run State VCCE 5 V VCCI system 3 3 V VDD 3 3 V Figure 22 3 4 CPU Reset State ...

Page 830: ...rcuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3 3V power supply OSC VCC FVCC VDD VCCI AVCC0 VCCE M32R E 0V 0V 3 3V 2 0V I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3 3V power supply Figure 22 3 5 CPU Halt State Figure 22 3 6 SRAM Data Backup State ...

Page 831: ...imum Ratings 23 2 Recommended Operating Conditions 23 3 DC Characteristics 23 4 A D Conversion Characteristics 23 5 D A Conversion Characteristics 23 6 AC Characteristics CHAPTER 23 CHAPTER 23 ELECTRICAL CHARACTERISTICS ...

Page 832: ...g Ambient Temperature Note o C Tstg Storage Temperature o C V Internal Logic Power Supply Voltage VDD VCCI FVCC OSC VCC VDD VCCI FVCC OSC VCC 0 3 4 2 0 3 4 2 VDD VCCI FVCC OSC VCC VDD VCCI FVCC OSC VCC 0 3 4 2 0 3 4 2 VCCE External I O Buffer Voltage VCCE AVCC VREF Xout 0 3 6 5 0 3 6 5 0 3 6 5 40 125 65 150 0 3 OSC VCC 0 3 0 3 VCCE 0 3 0 3 OSC VCC 0 3 500 0 3 VCCE 0 3 V V Other Other VCCE AVCC VRE...

Page 833: ...AIT 0 8VCCE 0 43VCCE VCCE 0 2VCCE 0 0 0 16VCCE High Level Mean Output Current P0 P11 P14 P22 Note 4 Low Level Peak Output Current P0 P11 P14 P22 Note 3 Low Level Mean Output Current P0 P11 P14 P22 Note 4 External Clock Input Frequency 5 10 10 V V V V V V V V V V Ports P0 P22 RESET MOD0 MOD1 FP Ports P0 P1 in only external extended processor modes WAIT Ports P0 P22 RESET MOD0 MOD1 FP 3 0 3 0 4 5 3 ...

Page 834: ... 43VCCE VCCE 0 2VCCE 0 0 0 16VCCE High Level Peak Output Current P0 P11 P14 P22 Note 3 High Level Mean Output Current P0 P11 P14 P22 Note 4 Low Level Peak Output Current P0 P11 P14 P22 Note 3 Low Level Mean Output Current P0 P11 P14 P22 Note 4 External Clock Input Frequency 5 V V V V V V V V V V Ports P0 P22 RESET MOD0 MOD1 FP Ports P0 P1 in only external extended processor modes WAIT Ports P0 P22...

Page 835: ...o C Hysteresis Note 3 RTDCLK RTDRXD SCLKI0 1 4 5 RXD0 1 2 3 4 5 6 7 TINB0 1 RESET FP MOD0 1 JTMS JTRST JTDI VCCE 5V VT VT Hysteresis Note 4 SBI HREQ VCCE 5V 0 3 V µA mA VCCE 0 1 IDDhold f XIN 10 0MHz When operating 1 ICCI 3V 3 3 V System Power Supply Current Note 2 mA 75 75 f XIN 10 0MHz When reset f XIN 10 0MHz When operating 12 125 TIN0 11 TINA0 1 Note 1 Total current of VCCE AVCC VREF in single...

Page 836: ...f XIN 10 0MHZ IAVCC AVCC Power Supply Current when Operating f XIN 10 0MHZ mA mA mA FVCC Power Supply Current when Operating Note 1 f XIN 10 0MHZ FICC mA Symbol Parameter Rated Value Unit MIN TYP MAX Test Condition f XIN 10 0MHZ 10 120 3 3 35 50 20 Note 1 This refers to the maximum value including programming and erase currents Note 2 This refers to the maximum value including currents needed when...

Page 837: ...K RTDRXD SCLKI0 1 4 5 RXD0 1 2 3 4 5 6 7 TINB0 1 RESET FP MOD0 1 JTMS JTRST JTDI VCCE 5V VT VT Hysteresis Note 4 SBI HREQ VCCE 5V 0 3 V µA mA VCCE 0 1 IDDhold f XIN 8 0MHz When operating 1 ICCI 3V 3 3V System Power Supply Current Note 2 mA 60 70 f XIN 8 0MHz When reset f XIN 8 0MHz When operating 12 110 TIN0 11 TINA0 1 Note 1 Total current of VCCE AVCC VREF in single chip mode See the next page fo...

Page 838: ...er Supply Current when Operating f XIN 8 0MH Z OSC ICC OSC VCC Power Supply Current when Operating f XIN 8 0MH Z IDD VDD Power Supply Current when Operating Note 2 f XIN 8 0MH Z AICC AVCC Power Supply Current when Operating f XIN 8 0MH Z mA mA mA 10 FVCC Power Supply Current when Operating Note 1 f XIN 8 0MH Z FICC mA Symbol Parameter Rated Value Unit MIN TYP MAX Test Condition f XIN 8 0MH Z 105 1...

Page 839: ...CI 3 3 V 0 3 V unless otherwise specified Symbol Parameter Rated Value Ifvcc1 FVCC Power Supply Current when Programming mA lfvcc2 FVCC Power Supply Current when Erasing mA MIN TYP MAX Unit 50 40 Test Condition Flash Rewrite Ambient Temperature Topr 0 70 o C cycle Rewrite Durability 100 ELECTRICAL CHARACTERISTICS 23 3 DC Characteristics ...

Page 840: ...rter is inactive Input voltage conditions are 0 ANi AVCC Temperature conditions are Ta 40 to 85 C ELECTRICAL CHARACTERISTICS 23 4 DC Characteristics A D Conversion Characteristics Referenced to AVCC VREF VCCE 5 12 V Ta 40 to 125 C f XIN 8 0 MHz unless otherwise specified Note 1 The absolute accuracy indicates the accuracy of output codes produced by the A D converter with respect to analog inputs ...

Page 841: ...ue Resolution Bits Absolute Accuracy MIN TYP MAX Unit 8 1 Test Condition Setup Time 3 µS tsu Output Resistance 20 KΩ Reference Power Supply Input Current Ro IVREF Note 4 10 1 5 mA Note This applies to the case where the device is using one D A converter and the D A register value for the u nused D A converter is H 00 The A D converter s ladder resistance is not included ELECTRICAL CHARACTERISTICS ...

Page 842: ... MIN MAX Condition 23 6 AC Characteristics 23 6 1 Timing Requirements Unless otherwise noted timing conditions are VCCE 5 V 0 5 V VCCI 3 3 V 0 3 V Ta 40 to 125 C The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF however 80 pF for JTAG related In cases where the output load capacitance varies they may deviate from the rated switch...

Page 843: ...s 43 Data Input Setup Time before Read tsu D RDH 30 ns 44 Data Input Hold Time after Read th RDH D 45 ns 0 tc BCLK 2 23 3 td RDH BLWL Write Delay Time after Read ns 56 tc BCLK 10 td RDH BHWL 2 td BLWH RDL Read Delay Time after Write ns 57 tc BCLK 10 td BHWH RDL 2 Write Low Pulse Width Byte enable mode ns 68 tw WRL td RDH BLEL Write Delay Time after Read Byte enable mode ns 80 tc BCLK 10 td RDH BHE...

Page 844: ...ing Transition Time tf ns ns 59 Input Falling Transition Time Other than JTRST pin JTRST pin Other than JTRST pin JTRST pin JTCK JTDI JTMS JTDO When using TAP When not using TAP JTCK JTDI JTMS JTDO 10 10 2 10 10 2 ms ms See Figure 23 6 11 Symbol Rated Value Unit MIN MAX Condition When using TAP When not using TAP 7 Bus arbitration timing tsu HREQL BCLKH HREQ Input Setup Time before BCLK ns 35 HREQ...

Page 845: ...XD RTDCLKL th RTDCLKH RTDRXD RTDCLK Input Cycle Time RTDCLK Input High Pulse Width RTDCLK Input Low Pulse Width RTDACK Delay Time after RTDCLK Input RTDACK Valid Time after RTDCLK Input RTDTXD Delay Time after RTDCLK Input RTDRXD Input Setup Time RTDRXD Input Hold Time 500 230 230 60 100 160 160 tw RTDCLKH 160 ns ns ns ns ns ns 84 85 86 87 89 88 ELECTRICAL CHARACTERISTICS 23 6 AC Characteristics ...

Page 846: ...rameter Rated Value Unit MIN MAX Condition td CLK D TxD Output Delay Time 12 Symbol Parameter Unit Rated Value MIN MAX td CLK D TxD Output Delay Time ns 60 Condition 6 Symbol Parameter Unit Rated Value MIN MAX ns 160 Condition th CLK D TxD Hold Time 82 ns 0 See Figure 23 6 2 See Figure 23 6 2 b CSIO mode with external clock selected 1 Input output ports 23 6 2 Switching Characteristics 2 Serial I ...

Page 847: ... Pulse Width Data Output Disable Time after BCLK tpxz BCLKH DZ ns 30 11 11 12 12 16 19 24 24 10 11 td BCLKL BLWL td BCLKL BHWL tv BCLKL D tv BCLKL BLWL 18 tc BCLK 2 5 5 See Figure 23 6 7 23 6 8 23 6 9 Symbol Parameter Rated Value Unit MIN MAX Condition td A RDL ns 39 Chip Select Delay Time before Read td CS RDL ns 40 Valid Address Time after Read tv RDH A 41 ns 0 tc BCLK 2 15 Valid Chip Select Tim...

Page 848: ...ess Delay Time before Write Byte enable mode td A WRL 69 ns Chip Select Delay Time before Write Byte enable mode td CS WRL 70 ns Valid Address Time after Write Byte enable mode tv WRH A 71 ns Valid Chip Select Time after Write Byte enable mode tv WRH CS 72 ns Byte enable delay time before write Byte enable mode td BLE WRL td BHE WRL 73 ns Byte enable delay time after write Byte enable mode tv WRH ...

Page 849: ... th CLK D 0 8VCCE 0 2VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE tc CLK tw CLKH tw CLKL 4 5 6 7 8 12 10 11 9 0 2VCCE 0 8VCCE th CLK D 82 Port output td E P 0 8VCCE 0 2VCCE BCLK 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE Port input 0 2VCCE 0 8VCCE tsu P E th E P 1 2 3 Figure 23 6 1 Input Output Port Timing Figure 23 6 2 Serial I O Timing b CSIO mode with external clock selected a CSIO mode with inter...

Page 850: ...g Figure 23 6 4 TOi Timing TINi 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE tw TINi 14 BCLK TOi td BCLK TOi 0 8VCCE 0 2VCCE 0 2VCCE 15 0 8Vcc 0 8Vcc 0 8Vcc 0 8Vcc 0 2Vcc 0 2Vcc 0 2Vcc TIN8 10 TIN9 11 92 92 92 92 92 92 TIN8 11 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE tw TINi 91 Figure 23 6 6 TIN8 11 Input Timing When multiply by 4 event count or up down event count mode ...

Page 851: ...D0 D15 RD tv BCLKH RDL 18 17 16 21 22 0 16VCCE 0 43VCCE 0 16VCCE 0 43VCCE 0 16VCCE WAIT tsu WAITL BCLKH 0 16VCCE tpzx BCLKL DZ 0 16VCCE td BCLKL RDL tsu D RDH th RDH D tv RDH A tv RDH CS 44 45 46 tw RDL th BCLKH D tw RDH 0 43VCCE tsu D BCLKH td BHWH RDL td BLWH RDL 56 0 16VCCE td BCLKH A td BCLKH CS 42 43 23 19 20 40 39 55 57 31 32 29 33 34 tpxz BCLKH DZ 30 tv BCLKH A tv BCLKH CS 41 0 43VCCE 0 16V...

Page 852: ...L BHWL RD 18 17 16 21 22 0 43VCCE 0 16VCCE 0 16VCCE 0 43VCCE 0 16VCCE WAIT 0 16VCCE td BCLKL D tpzx BCLKL DZ tpxz BLWH DZ td CS BLWL tw BHWL tpxz BHWH DZ td CS BHWL td A BLWL td A BHWL tw BLWL tv BLWH A tv BHWH A tv BLWH CS tv BHWH CS 54 53 td BCLKH A td BCLKH CS 19 20 57 47 48 51 49 50 25 26 28 29 27 30 33 34 td BCLKL BLWL 0 16VCCE td BCLKL RDL 23 0 16VCCE 0 43VCCE 0 43VCCE td RDH BHWL td RDH BLW...

Page 853: ...0 16VCCE 0 43VCCE 0 43VCCE 0 16VCCE td WRL D tpxz WRH DZ tv WRH D 71 72 77 75 76 0 16VCCE 0 16VCCE BLE BHE WR tw WRL 68 73 74 69 70 td BHEL WRL td BLEL WRL 0 16VCCE 0 43VCCE td RDH BHEL td RDH BLEL td BHEH RDL td BLEH RDL tv WRH A tv WRH CS tv WRH BLEL tv WRH BHEL td CS WRL td A WRL 80 81 Data output D0 D15 Figure 23 6 9 Write Timing Byte enable mode Figure 23 6 10 Bus Arbitration Timing tsu HREQL...

Page 854: ... JTMS Data output JTDO JTRST tw JTCKL 61 65 66 67 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 62 0 2VCCE 0 2VCCE 0 8VCCE 0 2VCCE Note Stipulated values are guaranteed values when the test pin load capacitance CL 80 pF Figure 23 6 11 Input Transition Time on JTAG pins JTCK JTDI JTMS JRST tr tf 0 8VCCE 0 2VCCE 58 59 0 8VCCE 0 2VCCE Note Stipulated values are guaranteed values when the test pin l...

Page 855: ... Characteristics RTDCLK RTDACK RTDTXD RTDRXD tc RTDCLK tw RTDCLKH tw RTDCLKL 0 5VCCE 0 5VCCE 0 5VCCE td RTDCLKH RTDACK tv RTDCLKH RTDACK 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE td RTDCLKH RTDTXD 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE th RTDCLKH RTDACK tsu RTDRXD RTDCLKL 84 85 86 87 88 89 90 83 ...

Page 856: ...23 23 26 Rev 1 0 This is a blank page ELECTRICAL CHARACTERISTICS 23 6 AC Characteristics ...

Page 857: ...24 1 A D Conversion Characteristics CHAPTER 24 CHAPTER 24 STANDARD CHARACTERISTICS ...

Page 858: ...24 24 2 Rev 1 0 To be written at a later time STANDARD CHARACTERISTICS 24 1 A D Conversion Characteristics 24 1 A D Conversion Characteristics ...

Page 859: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...

Page 860: ...aterial Cu Alloy 144P6Q A Plastic 144pin 20 20mm body LQFP 0 125 0 2 Symbol Min Nom Max A A2 b c D E HE L L1 y b2 Dimension in Millimeters HD A1 0 225 I2 1 0 MD 20 4 ME 20 4 8 0 0 1 1 0 0 65 0 5 0 35 22 2 22 0 21 8 22 2 22 0 21 8 0 5 20 1 20 0 19 9 20 1 20 0 19 9 0 175 0 125 0 105 0 27 0 22 0 17 1 4 0 05 1 7 e Recommended Mount Pad MD l2 b 2 M E e A HD D H E E 1 36 37 72 73 108 109 144 F b e L A 2...

Page 861: ...Appendix 2 1 M32R E Instruction Processing Time APPENDIX 2 APPENDIX 2 INSTRUCTION PROCESSING TIME ...

Page 862: ...instruction fetch and D decode stages not just E execution stage must also be taken into account The table below shows the instruction processing time in each pipelined stage of the M32R Table 2 1 1 Instruction Processing Time of Each Pipeline Stage Number of execution cycles in each stage Note Instruction IF D E MEM WB Load instructions LD LDB LDUB LDH LDUH LOCK R 1 1 R 1 Store instructions ST ST...

Page 863: ...struction processing may take more time than the calculated value R read cycle Cycles When existing in instruction queue 1 When reading internal resource ROM RAM 1 When reading internal resource SFR byte halfword 2 When reading internal resource SFR word 4 When reading external memory byte halfword 5 Note When reading external memory word 9 Note When successively fetching instructions from externa...

Page 864: ...Appendix 2 INSTRUCTION PROCESSING TIME Appendix 2 1 M32R E Instruction Processing Time Appendix 2 4 Rev 1 0 This is a blank page ...

Page 865: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...

Page 866: ...s noise into the microcomputer Shorter the total wiring length the smaller the possibility of drawing noise into the microcomputer ____________ 1 Wiring of the RESET pin _____________ Reduce the length of wiring connecting to the RESET pin Especially when connecting a _____________ capacitor between the RESET and VSS pins make sure it is connected to each pin with the shortest possible wiring with...

Page 867: ...2 Wiring of clock input output pins Reduce the length of wiring connecting to the clock input output pins When connecting a capacitor to the oscillator make sure its ground lead wire and the VSS pin on the microcomputer are connected with the shortest possible wiring within 20 mm Also make sure the VSS pattern for clock oscillation is used for only the oscillator circuit and is separated from othe...

Page 868: ... 1 mF between VSS and VCC lines in such a way as to meet the requirements described below The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are equal The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are the shortest possible The VSS and VCC lines are comprised of wiring in greater width than that...

Page 869: ...ter input pin normally is an output signal from a sensor In many cases a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted so that wiring to the analog input pin inevitably is long Because a long wiring serves as an antenna which draws noise into the microcomputer the signal fed into the analog input pin tends to be noise ridden Furthermore if ...

Page 870: ... signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer especially the oscillator as possible Reasons Systems using the microcomputer contain signal lines to control for example a motor LED and thermal head When a large current flows in these signal lines it generates noise d...

Page 871: ...l lines and other noise sensitive signal lines Reasons Rapidly level changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls Especially if they intersect clock related signal lines they will cause the clock waveform to become distorted which may result in the microcomputer operating erratically or getting out of control XIN XOUT VSS High speed seri...

Page 872: ...s Insert resistors of 100 W or more in series to input output ports Software measures For input ports read out data in a program two or more times to verify that levels match For output ports rewrite the data register at certain intervals because there is a possibility of the output data being inverted by noise Rewrite the direction register at certain intervals Figure 3 1 8 Processing Input Outpu...

Page 873: ...d by Committee of editing of Mitsubishi Semiconductor User s Manual Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 2001 MITSUBISHI ELECTRIC CORPORATION ...

Page 874: ...s Manual 32172 32173 Group HEAD OFFICE 2 2 3 MARUNOUCHI CHIYODA KU TOKYO 100 8310 JAPAN New publication effective Jul 2001 Specifications subject to change without notice 2001 MITSUBISHI ELECTRIC CORPORATION ...

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