Mitsubishi 32172, User Manual

Page: 499 / 874

12
12-29
Rev.1.0
12.2.8 SIO Baud Rate Registers
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SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117>
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SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127>
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SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137>
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SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147>
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SIO4 Baud Rate Register (S4BAUR) <Address: H'0080 0A17>
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SIO5 Baud Rate Register (S5BAUR) <Address: H'0080 0A27>
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SIO6 Baud Rate Register (S6BAUR) <Address: H'0080 0A37>
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SIO7 Baud Rate Register (S7BAUR) <Address: H'0080 0A47>
D8 9 10 11 12 13 14 D15
BRG
<When reset: indeterminate>
D Bit Name Function R W
8-15 BRG The baud rate count source selected
(Baud rate divide value) with the SIO Mode Register is divided
by (n +1) where n = BRG divide value
set here.
BRG (Baud rate divide value) (D8-D15)
The SIO Baud Rate Registers are used to divide the baud rate count source selected with the
SIO Mode Register by (n + 1) where n is the BRG value that is set with this register.
In the initial state, the BRG value is indeterminate, so always be sure to set the divide value with
this register before using serial I/O. The value written to the BRG register while sending or
receiving data becomes effective beginning with the next cycle after the BRG counter finished
counting.
When using an internal clock in CSIO mode (i.e., producing SCLKO output signal), the internal
BCLK is first divided by the clock divider and the resulting clock frequency is divided by (n + 1)
where n = BRG set value and is further divided by 2 to produce the transmit/receive shift clock.
When using an external clock in CSIO mode, the BRG is not used (transmit/receive operations
are synchronized to an externally sourced clock).
In UART mode, the internal BCLK is first divided by the clock divider and the resulting clock
SERIAL I/O
12.2 Serial I/O Related Registers