Mitsubishi 32172, User Manual

Page: 735 / 874

17
17-17
Rev.1.0
(2) When Bus Mode Control Register = 1 (WR signal separate mode)
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External read/write operations are performed using the address and data buses and the CS0,
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CS1, CS2, CS3, RD, BHE, BLE, WAIT, and WR signals. In an external read cycle, the RD signal
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goes low and the BHE or BLE signal for the byte position to read goes low, so that the data at only
the necessary byte position is read.
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In an external write cycle, the WR signal goes low and the BHE or BLE signal for the byte position
to write is asserted low, allowing data to be written at the necessary byte position.
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When an external bus cycle starts, wait states are inserted as long as WAIT remains low.
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Therefore, the WAIT signal must always be held high unless necessary. Note that an external
bus cycle, even during the shortest access, has at least one wait state inserted (shortest bus
cycle consists of 2 BCLK cycles). When not using the WAIT function, set the P7 Operation Mode
Register P71MOD bit to 0. The pin can be used as P71.
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Note: CS2 and CS3 can be output in only external extended mode.
Figure 17.2.4 Read/Write Operations during Bus-free State/Internal Bus Access
EXTERNAL BUS INTERFACE
17.2 Read/Write Operations
Bus-free state
Internal bus access
"H"
BCLK
A12 – A30
CS0, CS1, CS2, CS3
DB0 – DB15
WAIT
RD
"H"
Hi-z
"H"
Note 1: Hi-Z denotes a high-impedance state.
Note 2: BCLK is not output.
WR
BHE, BLE
"H"