21
21-5
Rev.1.0
JTAG
21.3 JTAG Registers
21.3.2 Data Registers
(1) Boundary Scan Register (JTAGBSR)
The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this
register are assigned to each pin on the 32172/32173.
Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or
SAMPLE/PRELOAD instruction. In "Capture-DR" state, this register captures the status of input
pins or internal logic output values. In "Shift-DR" state, while outputting the sampled value, it is
used to set pin functions (input/output pin and tristate output pin direction) and output values by
entering data for boundary-scan test.
(2) Bypass Register (JTAGBPR)
The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32172/
32173 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this
register is selected when issuing BYPASS instruction. This register when in "Capture-DR" state
has b'0 (fixed value) loaded into it.
(3) ID Code Register (JTAGIDR)
The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds
the following information:
• Version information (4 bits)
: b'0000
• Part number (16 bits)
: b'0011 0010 0010 0000
• Manufacturer ID (11 bits)
: b'000 0001 1100
This register is connected between the JTDI and JTDO pins, and is selected when issuing
IDCODE instruction. When in "Capture-DR" state, this register has the said IDCODE data loaded
into it, which is output from the JTDO pin in "Shift_DR" state.
This register is a read-only register, so that the data written from the JTDI pin during DR pass
sequence is ignored. Therefore, make sure JTDI input = low during "Shift-DR" state.
0
3 4
19 20
30 31
Version
Part number
Manufacturer ID
1
4 bits
16 bits
11 bits
Note: For details about "Capture-DR" and "Shift-DR" states, refer to Section 21.4.
Summary of Contents for 32172
Page 20: ... This is a blank page 16 ...
Page 21: ...1 1 Overview 1 2 Block Diagram 1 3 Pin Functions 1 4 Pin Layout CHAPTER 1 CHAPTER 1 OVERVIEW ...
Page 44: ...1 1 24 Rev 1 0 This is a blank page Overview 1 4 Pin Layout ...
Page 58: ...2 2 14 Rev 1 0 This is a blank page CPU 2 6 Data Formats ...
Page 122: ...4 4 26 Rev 1 0 This is a blank page EIT 4 13 Precautions on EIT ...
Page 200: ...7 7 6 Rev 1 0 This is a blank page RESET 7 4 Precautions to Be Taken Immediately after Reset ...
Page 298: ...9 9 58 Rev 1 0 This is a blank page DMAC 9 4 Precautions on Using DMAC ...
Page 776: ...19 19 10 Rev 1 0 RAM BACKUP MODE 19 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 782: ...20 20 6 Rev 1 0 OSCILLATION CIRCUIT 20 2 Clock Generator Circuit This is a blank page ...
Page 856: ...23 23 26 Rev 1 0 This is a blank page ELECTRICAL CHARACTERISTICS 23 6 AC Characteristics ...
Page 857: ...24 1 A D Conversion Characteristics CHAPTER 24 CHAPTER 24 STANDARD CHARACTERISTICS ...
Page 859: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 865: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...