4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
86
102
28
ta _delay_ et y
Read and write0
0: According to internal logic (see bit 29)
1: Retry now
27
ta _ ead_ab
耀
t_en Read and write0
If ta_get timeout for internal read request, whether to let ta_get-ab Yao-t respond
26:25 Rese ved
-
0
twenty four
ta _w te_ab
耀
t_en Read and write0
If ta get times out for internal write request, whether to let ta get-ab Yao t respond
twenty three
ta _maste _ab
耀
t Read and write0
Whether to allow maste-ab Yaot
22:20 ta _subseq_t me Yaout
Read and write
000
ta get subsequent delay timeout
000: 8 cycles
Other: Not supported
19:16 ta _ n t_t me Yaout
Read and write
0000
ta get initial delay timeout
In PCI mode
0: 16 cycles
1-7: Disable counter
8-15: 8-15 cycle
In PCIX mode, the timeout count is fixed at 8 cycles.
delay visits
0: 8 delay access
8: 1 delay access
9: 2 delay visit
10: 3 delay visit
11: 4 delay visit
Page 107
Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
12: 5 delay visit
13: 6 delay visit
14: 7 delay visit
15: 8 delay visit
15: 4 ta _p ef_b Yao unda y Read and write
000h
Prefetchable boundary configuration (in units of 16 bytes)
FFF: 64KB to 16byte
FFE: 64KB to 32byte
FF8: 64KB to 128byte
3
ta _p ef_b
耀
und_en
Read and write0
Use ta _p ef_b
耀
unda y configuration
0: prefetch to device boundary
1: Use ta _p ef_b
耀
unda y
2
Rese
-
0
1
ta _spl tw_ct l
Read and write0
ta get spl t write control
0: Block access except P Yao sted Mem Yao Cheng y W Cheng te
1: Block all access until spl t is completed
0
mas_lat_t meyaut
Read and write0
Disable mate access timeout
0: Allow maste to access timeout
1: not allowed
REG_44
31: 0 Rese ved
-
-
REG_48
31: 0 ta _pend ng_seq
Read and write0
ta get unprocessed request number vector
The corresponding bit can be cleared by writing 1
REG_4C
31:30 Rese ved
-
-
29
mas_w te_defe
Read and write0
Allow subsequent reads to skip past unfinished writes
(Only valid for PCI)
28
mas_ ead_defe
Read and write0
Allow subsequent reads and writes to bypass previous unfinished reads
(Only valid for PCI)
27
mas_
耀
_defe _cnt
Read and write0
Maximum number of IO requests out
0: controlled by
1: 1