4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
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Four 64-bit super-scalar GS464e high-performance processor cores are integrated on-chip;
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On-chip integrated 8MB split shared three-level cache (composed of 4 individual modules, each module has a capacity of 2MB);
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Maintain the cache consistency of multi-core and I / O DMA access through the directory protocol;
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Two 64-bit DDR2 / 3 controllers with ECC and 667MHz are integrated on-chip;
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3B3000 integrates two 16-bit 1.6GHz HyperTransport controllers (hereinafter referred to as HT);
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3A3000 on-chip HT1 is a 16-bit 1.6GHz HT controller, HT0 is not available;
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Each 16-bit HT port is split into two 8-way HT ports for use.
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On-chip integrated 32-bit 33MHz PCI;
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Integrate 1 LPC, 2 UARTs, 1 SPI, 16 GPIO interfaces on-chip.
Compared with Loongson 3A2000 / 3B2000, the main improvements are as follows:
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Processor core microstructure upgrade;
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Memory controller structure and frequency upgrade;
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HT controller structure and frequency upgrade;
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The performance of the whole chip is optimized and improved.
The overall architecture of Loongson 3A3000 / 3B3000 chip is based on two-level interconnection. The structure is shown in Figures 1-3 below.
Figure 1-3 Loongson 3A3000 / 3B3000 chip structure
The first level interconnection uses a 6x6 crossbar switch, which is used to connect four GS464e cores (as a master device) and four shares
Cache module (as a slave device), and two IO ports (each port uses a Master and a Slave).
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
Each IO port connected to the first-level interconnect switch is connected to a 16-bit HT controller, and each 16-bit HT port can also
Used as two 8-bit HT ports. The HT controller is connected to the first-level interconnect switch through a DMA controller. The DMA controller
The controller is responsible for the DMA control of the IO and the maintenance of the consistency between the slices. The DMA controller of Godson 3 can also be configured
Realize prefetching and matrix transposition or transfer.
The second level interconnection uses a 5x4 crossbar switch to connect 4 shared Cache modules (as the master device), two DDR2 / 3
Memory controller, low-speed high-speed I / O (including PCI, LPC, SPI, etc.) and configuration register module inside the chip.
The above two-level interconnect switches all use separate data channels for reading and writing. The width of the data channel is 128 bits.