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HyperTransport3.0 link bus clock frequency is 1/4.
Offset:
0x13C
name:
Training 3 count register
Table 10- 78 T anan ng 3 count register
Bit field
Bit field name
Bit width reset value Visit description
31: 0
T3 time
32
0x7fffff
R / W Training 3 Count register
10.5.28
Software frequency configuration register
It is used to switch the controller to the link frequency and controller frequency supported by any protocol and PLL during the working process;
The specific switching method is: on the premise of enabling the software configuration mode, set bit 1 of the software frequency configuration register, and
Write parameters related to the new clock, including div_refc and div_loop that determine the output frequency of the PLL
Frequency coefficients phy_hi_div and phy_lo_div, and the frequency division coefficient core_div of the controller. Then enter the warm
reset or LDT disconnect, the controller will automatically reset the PLL and configure new clock parameters.
The calculation formula of the clock frequency is:
HyperTransport 1.0:
PHY_LINK_CLK = 50MHz × div_loop / div_refc / phy_div
HT_CORE_CLK
=
100MHz × div_loop / div_refc / core_div
HyperTransport 3.0:
PHY_LINK_CLK = 100MHz × div_loop / div_refc
HT_CORE_CLK
=
100MHz × div_loop / div_refc / core_div
The time to wait for the PLL to relock is about 30us by default when the system clk is 33M;
Write a custom upper limit of wait count in the memory;
Offset:
0x178
Reset value:
0x00000000
name:
Software frequency configuration register
Table 10-79 Software Frequency Configuration Register
Bit field
Bit field name
Bit width reset value Visit description
31:27
PLL relock
counter
5
0x0
R / W counter upper limit configuration register, set counter select
, The upper limit of the counter is
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
{PLL_relock_counter, 5'h1f}, otherwise the upper limit of count
10'3ff
26
Counter select
1
0x0
R / W
Lock timer custom enable:
1'b0 uses the default upper counting limit;
1'b1 is calculated by PLL_relock_counter
25: 22 Soft_phy_lo_div
4
0x0
R / W High PHY Divider
21: 18 Soft_phy_hi_div
4
0x0
R / W Low PHY Divider
17: 16 Soft_div_refc
2
0x0
R / W PLL internal frequency division factor