4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
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CORE1_AWMASK0
0x3ff01908
RW
CORE1 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable
The trigger condition is
(AW_IN & AWMASK) == (AWCOND & AWMASK)
CORE1_AWCOND1
0x3ff01910
RW
The trigger condition of AW must be satisfied by both COND0 and COND1
CORE1_AWMASK1
0x3ff01918
RW
CORE1_ARCOND0
0x3ff01920
RW
CORE1's AXI interface AR trigger condition, similar to AW
CORE1_ARMASK0
0x3ff01928
RW
CORE1_ARCOND1
0x3ff01930
RW
CORE1_ARMASK1
0x3ff01938
RW
CORE1_WCOND0
0x3ff01940
RW
CORE1's AXI interface W trigger condition, similar to AW
CORE1_WMASK0
0x3ff01948
RW
CORE1_WCOND1
0x3ff01950
RW
CORE1_WMASK1
0x3ff01958
RW
CORE1_WCOND2
0x3ff01960
RW
CORE1_WMASK2
0x3ff01968
RW
CORE1_BCOND0
0x3ff01970
RW
CORE1's AXI interface B trigger condition, similar to AW
CORE1_BMASK0
0x3ff01978
RW
CORE1_RCOND0
0x3ff01980
RW
CORE1's AXI interface R trigger condition, similar to AW
CORE1_RMASK0
0x3ff01988
RW
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
CORE1_RCOND1
0x3ff01990
RW
CORE1_RMASK1
0x3ff01998
RW
CORE1_RCOND2
0x3ff019a0
RW
CORE1_RMASK2
0x3ff019a8
RW
TUD1_CONF0
0x3ff019e0
RW
TUD1 configuration register 0
[47: 0]: count_target
[55:48]: monitor_enable
TUD1_CONF1
0x3ff019e8
RW
TUD0 configuration register 1
[2: 0]: DCDL_sel_signal
[5: 3]: DCDL_sel_clock
[9: 6]: signal_sel
[13:10]: clok_sel
[20:14]: reading_sel
[21]: counter_clock_sel
[22]: sticky
[23]: reset_g
[24]: stop
[25]: start
[26]: cg_en