Loongson 3A3000, User Manual

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4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
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127: 126 BBMUX_SEL_3 RW 0x0 BBMUX_SEL_3 setting value
other
- RW
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Note: PLL ouput = (clk_ref * div_loopc) / div_out.
The VCO frequency of the L1 PLL (the part in parentheses in the above formula) must be in the range 1.2GHz-3.2GHz. Should be
It is also applicable to MEM PLL and HT PLL. The VCO frequency of the L2 PLL must be in the range 3.2GHz-6.4GHz.
Table 2- 14 Chip memory and HT clock software frequency multiplication setting register (physical address 0x1fe001c0)
Bit field Field name access Reset value description
0 SEL _MEM_PLL RW 0x0 MEM clock non-software bypass entire PLL
1 SOFT_SET_MEM_PLL RW 0x0
Allow software to set MEM PLL
2 BYPASS_MEM_PLL RW 0x0 Bypass MEM_PLL
5: 3
6 LOCKED_MEM_PLL R 0x0 Whether MEM_PLL is locked
7 PD_MEM_PLL RW 0x0
Turn off MEM PLL
13: 8 MEM_PLL_DIV_REFC RW 0x1
MEM PLL input parameters
When selecting NODE clock (NODE_CLOCK_SEL
When 1), it is used as frequency division input
23:14 MEM_PLL_DIV_LOOPC RW 0x41 MEM PLL input parameters
29:24 MEM_PLL_DIV_OUT RW 0x0 MEM PLL input parameters
30 NODE_CLOCK_SEL RW 0x0
0: Use MEM_PLL as the MEM clock
1: Use NODE_CLOCK as the crossover input
32 SEL_HT0_PLL RW 0x0 HT0 non-software bypass PLL
33 SOFT_SET_HT0_PLL RW 0x0
Allow software to set HT0 PLL
34 BYPASS_HT0_PLL RW 0x0 Bypass HT0_PLL
35 LOCKEN_HT0_PLL RW 0x0
Allow lock HT0 PLL
37:36 LOCKC_HT0_PLL RW 0x0
Determine whether the HT0 PLL is locked with phase accuracy
38 LOCKED_HT0_PLL R 0x0 Whether HT0_PLL is locked
45:40 HT0_DIV_HTCORE RW 0x1 HT0 Core PLL input parameters
48 SEL_HT1_PLL RW 0x0 HT1 non-software bypass PLL
49 SOFT_SET_HT1_PLL RW 0x0
Allow software to set HT1 PLL
50 BYPASS_HT1_PLL RW 0x0 Bypass HT1_PLL
51 LOCKEN_HT1_PLL RW 0x0
Allow HT1 PLL to be locked
53:52 LOCKC_HT1_PLL RW 0x0
Determine whether the HT1 PLL is locked with phase accuracy
54 LOCKED_HT1_PLL R 0x0 Whether HT1_PLL is locked
61:56 HT1_DIV_HTCORE RW 0x1 HT1 Core PLL input parameters
other
RW
Keep
Table 2- 15 Chip processor core software frequency division setting register (physical address 0x1fe001d0)
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
Bit field Field name access Reset value description
2: 0 core0_freqctrl RW 0x7
Core 0 division control value
3 core0_en RW 0x1
Core 0 clock enable
6: 4 core1_freqctrl RW 0x7
Core 1 division control value