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Loongson 3A3000 / 3B3000 Processor User Manual
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HT0_Hi_Rstn
Bus Rstn
HyperTransport bus Rstn signal,
When HT0_Lo_Mode is 1, it is controlled by HT0_Hi;
When HT0_Lo_Mode is 0, it is controlled by the opposite device.
When HT0_8x2 is 1, control the upper 8-bit bus;
When HT0_8x2 is 0, it is invalid.
HT0_Hi_Ldt_Stopn
Bus Ldt_Stopn
HyperTransport bus Ldt_Stopn signal,
When HT0_Lo_Mode is 1, it is controlled by HT0_Hi;
When HT0_Lo_Mode is 0, it is controlled by the opposite device.
When HT0_8x2 is 1, control the upper 8-bit bus;
When HT0_8x2 is 0, it is invalid.
HT0_Hi_Ldt_Reqn
Bus Ldt_Reqn
HyperTransport bus Ldt_Reqn signal,
When HT0_8x2 is 1, control the upper 8-bit bus;
When HT0_8x2 is 0, it is invalid.
HT0_Rx_CLKp [1: 0]
HT0_Rx_CLKn [1: 0]
HT0_Tx_CLKp [1: 0]
HT0_Tx_CLKp [1: 0]
CLK [1: 0]
HyperTransport bus CLK signal
When HT0_8x2 is 1, CLK [1] is controlled by HT0_Hi
CLK [0] is controlled by HT0_Lo
When HT0_8x2 is 0, CLK [1: 0] is controlled by HT0_Lo
HT0_Rx_CTLp [1: 0]
HT0_Rx_CTLn [1: 0]
HT0_Tx_CTLp [1: 0]
HT0_Tx_CTLn [1: 0]
CTL [1: 0]
HyperTransport bus CTL signal
When HT0_8x2 is 1, CTL [1] is controlled by HT0_Hi
CTL [0] is controlled by HT0_Lo
When HT0_8x2 is 0, CTL [1] is invalid
CTL [0] is controlled by HT0_Lo
HT0_Rx_CADp [15: 0]
HT0_Rx_CADn [15: 0]
HT0_Tx_CADp [15: 0]
HT0_Tx_CADn [15: 0]
CAD [15: 0]
HyperTransport bus CAD signal
When HT0_8x2 is 1, CAD [15: 8] is controlled by HT0_Hi
CAD [7: 0] is controlled by HT0_Lo
When HT0_8x2 is 0, CAD [15: 0] is controlled by HT0_Lo
The initialization of HyperTransport starts automatically after each reset is completed, and the HyperTransport bus after a cold start
It will automatically work at the lowest frequency (200MHz) and the smallest width (8bit), and try to initiate a bus initialization handshake. initialization
Whether it is in the completed state can be read from the register "Init Complete" (see Section 10.5.2). After initialization,
The width of the bus can be read from the registers "Link Width Out" and "Link Width In" (see Section 10.5.2).
After initialization, the user can rewrite the registers "Link Width Out", "Link Width In" and "Link
Freq ”, at the same time, you need to configure the corresponding register of the other device. After the configuration is completed, you need to warm reset the bus or pass
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
The "HT_Ldt_Stopn" signal performs a reinitialization operation so that the rewritten value of the register takes effect. Reinitialized
After completion, the HyperTransport bus will work at the new frequency and width. It should be noted that both ends of HyperTransport
The configuration of the device needs to be one-to-one, otherwise the HyperTransport interface will not work properly.
10.2 HyperTransport protocol support
Godson 3A3000 / 3B3000's HyperTransport bus supports most commands in version 1.03 / 3.0 protocol, and
In addition, some extended instructions are added to the extended consistency protocol that supports multi-chip interconnection. In the above two modes,
The commands that the HyperTransport receiver can receive are shown in the following table. It should be noted that HyperTransport is not supported
Bus atomic operation commands.
Table 10- 2 Hype, T, and ansp commands that can be received by the receiving end
coding
aisle
command
Standard mode
Extension (consistency)
000000
-
NOP
Empty package or flow control
000001
NPC
FLUSH
No operation
x01xxx
NPC
or
PC
Write
bit 5: 0-Nonposted
1-Posted
bit 2: 0 – Byte
bit 5: Must be 1, POSTED
bit 2: 0 – Byte
